Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / arch / arm / mach-omap2 / io.c
blobd408b15b4fbfd97ecd3d82aaa46cc86788e63a8c
1 /*
2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
25 #include <asm/tlb.h>
26 #include <asm/mach/map.h>
28 #include <linux/omap-dma.h>
30 #include "omap_hwmod.h"
31 #include "soc.h"
32 #include "iomap.h"
33 #include "voltage.h"
34 #include "powerdomain.h"
35 #include "clockdomain.h"
36 #include "common.h"
37 #include "clock.h"
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
40 #include "clock44xx.h"
41 #include "omap-pm.h"
42 #include "sdrc.h"
43 #include "control.h"
44 #include "serial.h"
45 #include "sram.h"
46 #include "cm2xxx.h"
47 #include "cm3xxx.h"
48 #include "prm.h"
49 #include "cm.h"
50 #include "prcm_mpu44xx.h"
51 #include "prminst44xx.h"
52 #include "cminst44xx.h"
53 #include "prm2xxx.h"
54 #include "prm3xxx.h"
55 #include "prm44xx.h"
58 * omap_clk_soc_init: points to a function that does the SoC-specific
59 * clock initializations
61 static int (*omap_clk_soc_init)(void);
64 * The machine specific code may provide the extra mapping besides the
65 * default mapping provided here.
68 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
69 static struct map_desc omap24xx_io_desc[] __initdata = {
71 .virtual = L3_24XX_VIRT,
72 .pfn = __phys_to_pfn(L3_24XX_PHYS),
73 .length = L3_24XX_SIZE,
74 .type = MT_DEVICE
77 .virtual = L4_24XX_VIRT,
78 .pfn = __phys_to_pfn(L4_24XX_PHYS),
79 .length = L4_24XX_SIZE,
80 .type = MT_DEVICE
84 #ifdef CONFIG_SOC_OMAP2420
85 static struct map_desc omap242x_io_desc[] __initdata = {
87 .virtual = DSP_MEM_2420_VIRT,
88 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
89 .length = DSP_MEM_2420_SIZE,
90 .type = MT_DEVICE
93 .virtual = DSP_IPI_2420_VIRT,
94 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
95 .length = DSP_IPI_2420_SIZE,
96 .type = MT_DEVICE
99 .virtual = DSP_MMU_2420_VIRT,
100 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
101 .length = DSP_MMU_2420_SIZE,
102 .type = MT_DEVICE
106 #endif
108 #ifdef CONFIG_SOC_OMAP2430
109 static struct map_desc omap243x_io_desc[] __initdata = {
111 .virtual = L4_WK_243X_VIRT,
112 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
113 .length = L4_WK_243X_SIZE,
114 .type = MT_DEVICE
117 .virtual = OMAP243X_GPMC_VIRT,
118 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
119 .length = OMAP243X_GPMC_SIZE,
120 .type = MT_DEVICE
123 .virtual = OMAP243X_SDRC_VIRT,
124 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
125 .length = OMAP243X_SDRC_SIZE,
126 .type = MT_DEVICE
129 .virtual = OMAP243X_SMS_VIRT,
130 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
131 .length = OMAP243X_SMS_SIZE,
132 .type = MT_DEVICE
135 #endif
136 #endif
138 #ifdef CONFIG_ARCH_OMAP3
139 static struct map_desc omap34xx_io_desc[] __initdata = {
141 .virtual = L3_34XX_VIRT,
142 .pfn = __phys_to_pfn(L3_34XX_PHYS),
143 .length = L3_34XX_SIZE,
144 .type = MT_DEVICE
147 .virtual = L4_34XX_VIRT,
148 .pfn = __phys_to_pfn(L4_34XX_PHYS),
149 .length = L4_34XX_SIZE,
150 .type = MT_DEVICE
153 .virtual = OMAP34XX_GPMC_VIRT,
154 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
155 .length = OMAP34XX_GPMC_SIZE,
156 .type = MT_DEVICE
159 .virtual = OMAP343X_SMS_VIRT,
160 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
161 .length = OMAP343X_SMS_SIZE,
162 .type = MT_DEVICE
165 .virtual = OMAP343X_SDRC_VIRT,
166 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
167 .length = OMAP343X_SDRC_SIZE,
168 .type = MT_DEVICE
171 .virtual = L4_PER_34XX_VIRT,
172 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
173 .length = L4_PER_34XX_SIZE,
174 .type = MT_DEVICE
177 .virtual = L4_EMU_34XX_VIRT,
178 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
179 .length = L4_EMU_34XX_SIZE,
180 .type = MT_DEVICE
182 #if defined(CONFIG_DEBUG_LL) && \
183 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
185 .virtual = ZOOM_UART_VIRT,
186 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
187 .length = SZ_1M,
188 .type = MT_DEVICE
190 #endif
192 #endif
194 #ifdef CONFIG_SOC_TI81XX
195 static struct map_desc omapti81xx_io_desc[] __initdata = {
197 .virtual = L4_34XX_VIRT,
198 .pfn = __phys_to_pfn(L4_34XX_PHYS),
199 .length = L4_34XX_SIZE,
200 .type = MT_DEVICE
203 #endif
205 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
206 static struct map_desc omapam33xx_io_desc[] __initdata = {
208 .virtual = L4_34XX_VIRT,
209 .pfn = __phys_to_pfn(L4_34XX_PHYS),
210 .length = L4_34XX_SIZE,
211 .type = MT_DEVICE
214 .virtual = L4_WK_AM33XX_VIRT,
215 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
216 .length = L4_WK_AM33XX_SIZE,
217 .type = MT_DEVICE
220 #endif
222 #ifdef CONFIG_ARCH_OMAP4
223 static struct map_desc omap44xx_io_desc[] __initdata = {
225 .virtual = L3_44XX_VIRT,
226 .pfn = __phys_to_pfn(L3_44XX_PHYS),
227 .length = L3_44XX_SIZE,
228 .type = MT_DEVICE,
231 .virtual = L4_44XX_VIRT,
232 .pfn = __phys_to_pfn(L4_44XX_PHYS),
233 .length = L4_44XX_SIZE,
234 .type = MT_DEVICE,
237 .virtual = L4_PER_44XX_VIRT,
238 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
239 .length = L4_PER_44XX_SIZE,
240 .type = MT_DEVICE,
242 #ifdef CONFIG_OMAP4_ERRATA_I688
244 .virtual = OMAP4_SRAM_VA,
245 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
246 .length = PAGE_SIZE,
247 .type = MT_MEMORY_RW_SO,
249 #endif
252 #endif
254 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
255 static struct map_desc omap54xx_io_desc[] __initdata = {
257 .virtual = L3_54XX_VIRT,
258 .pfn = __phys_to_pfn(L3_54XX_PHYS),
259 .length = L3_54XX_SIZE,
260 .type = MT_DEVICE,
263 .virtual = L4_54XX_VIRT,
264 .pfn = __phys_to_pfn(L4_54XX_PHYS),
265 .length = L4_54XX_SIZE,
266 .type = MT_DEVICE,
269 .virtual = L4_WK_54XX_VIRT,
270 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
271 .length = L4_WK_54XX_SIZE,
272 .type = MT_DEVICE,
275 .virtual = L4_PER_54XX_VIRT,
276 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
277 .length = L4_PER_54XX_SIZE,
278 .type = MT_DEVICE,
280 #ifdef CONFIG_OMAP4_ERRATA_I688
282 .virtual = OMAP4_SRAM_VA,
283 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
284 .length = PAGE_SIZE,
285 .type = MT_MEMORY_RW_SO,
287 #endif
289 #endif
291 #ifdef CONFIG_SOC_OMAP2420
292 void __init omap242x_map_io(void)
294 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
295 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
297 #endif
299 #ifdef CONFIG_SOC_OMAP2430
300 void __init omap243x_map_io(void)
302 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
303 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
305 #endif
307 #ifdef CONFIG_ARCH_OMAP3
308 void __init omap3_map_io(void)
310 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
312 #endif
314 #ifdef CONFIG_SOC_TI81XX
315 void __init ti81xx_map_io(void)
317 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
319 #endif
321 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
322 void __init am33xx_map_io(void)
324 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
326 #endif
328 #ifdef CONFIG_ARCH_OMAP4
329 void __init omap4_map_io(void)
331 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
332 omap_barriers_init();
334 #endif
336 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
337 void __init omap5_map_io(void)
339 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
340 omap_barriers_init();
342 #endif
344 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
346 * Sets the CORE DPLL3 M2 divider to the same value that it's at
347 * currently. This has the effect of setting the SDRC SDRAM AC timing
348 * registers to the values currently defined by the kernel. Currently
349 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
350 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
351 * or passes along the return value of clk_set_rate().
353 static int __init _omap2_init_reprogram_sdrc(void)
355 struct clk *dpll3_m2_ck;
356 int v = -EINVAL;
357 long rate;
359 if (!cpu_is_omap34xx())
360 return 0;
362 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
363 if (IS_ERR(dpll3_m2_ck))
364 return -EINVAL;
366 rate = clk_get_rate(dpll3_m2_ck);
367 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
368 v = clk_set_rate(dpll3_m2_ck, rate);
369 if (v)
370 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
372 clk_put(dpll3_m2_ck);
374 return v;
377 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
379 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
382 static void __init omap_hwmod_init_postsetup(void)
384 u8 postsetup_state;
386 /* Set the default postsetup state for all hwmods */
387 #ifdef CONFIG_PM_RUNTIME
388 postsetup_state = _HWMOD_STATE_IDLE;
389 #else
390 postsetup_state = _HWMOD_STATE_ENABLED;
391 #endif
392 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
394 omap_pm_if_early_init();
397 static void __init __maybe_unused omap_common_late_init(void)
399 omap_mux_late_init();
400 omap2_common_pm_late_init();
401 omap_soc_device_init();
404 #ifdef CONFIG_SOC_OMAP2420
405 void __init omap2420_init_early(void)
407 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
408 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
409 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
410 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
411 NULL);
412 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
413 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
414 omap2xxx_check_revision();
415 omap2xxx_prm_init();
416 omap2xxx_cm_init();
417 omap2xxx_voltagedomains_init();
418 omap242x_powerdomains_init();
419 omap242x_clockdomains_init();
420 omap2420_hwmod_init();
421 omap_hwmod_init_postsetup();
422 omap_clk_soc_init = omap2420_clk_init;
425 void __init omap2420_init_late(void)
427 omap_common_late_init();
428 omap2_pm_init();
429 omap2_clk_enable_autoidle_all();
431 #endif
433 #ifdef CONFIG_SOC_OMAP2430
434 void __init omap2430_init_early(void)
436 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
437 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
438 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
439 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
440 NULL);
441 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
442 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
443 omap2xxx_check_revision();
444 omap2xxx_prm_init();
445 omap2xxx_cm_init();
446 omap2xxx_voltagedomains_init();
447 omap243x_powerdomains_init();
448 omap243x_clockdomains_init();
449 omap2430_hwmod_init();
450 omap_hwmod_init_postsetup();
451 omap_clk_soc_init = omap2430_clk_init;
454 void __init omap2430_init_late(void)
456 omap_common_late_init();
457 omap2_pm_init();
458 omap2_clk_enable_autoidle_all();
460 #endif
463 * Currently only board-omap3beagle.c should call this because of the
464 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
466 #ifdef CONFIG_ARCH_OMAP3
467 void __init omap3_init_early(void)
469 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
470 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
471 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
472 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
473 NULL);
474 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
475 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
476 omap3xxx_check_revision();
477 omap3xxx_check_features();
478 omap3xxx_prm_init();
479 omap3xxx_cm_init();
480 omap3xxx_voltagedomains_init();
481 omap3xxx_powerdomains_init();
482 omap3xxx_clockdomains_init();
483 omap3xxx_hwmod_init();
484 omap_hwmod_init_postsetup();
485 omap_clk_soc_init = omap3xxx_clk_init;
488 void __init omap3430_init_early(void)
490 omap3_init_early();
491 if (of_have_populated_dt())
492 omap_clk_soc_init = omap3430_dt_clk_init;
495 void __init omap35xx_init_early(void)
497 omap3_init_early();
498 if (of_have_populated_dt())
499 omap_clk_soc_init = omap3430_dt_clk_init;
502 void __init omap3630_init_early(void)
504 omap3_init_early();
505 if (of_have_populated_dt())
506 omap_clk_soc_init = omap3630_dt_clk_init;
509 void __init am35xx_init_early(void)
511 omap3_init_early();
512 if (of_have_populated_dt())
513 omap_clk_soc_init = am35xx_dt_clk_init;
516 void __init ti81xx_init_early(void)
518 omap2_set_globals_tap(OMAP343X_CLASS,
519 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
520 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
521 NULL);
522 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
523 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
524 omap3xxx_check_revision();
525 ti81xx_check_features();
526 omap3xxx_voltagedomains_init();
527 omap3xxx_powerdomains_init();
528 omap3xxx_clockdomains_init();
529 omap3xxx_hwmod_init();
530 omap_hwmod_init_postsetup();
531 if (of_have_populated_dt())
532 omap_clk_soc_init = ti81xx_dt_clk_init;
533 else
534 omap_clk_soc_init = omap3xxx_clk_init;
537 void __init omap3_init_late(void)
539 omap_common_late_init();
540 omap3_pm_init();
541 omap2_clk_enable_autoidle_all();
544 void __init omap3430_init_late(void)
546 omap_common_late_init();
547 omap3_pm_init();
548 omap2_clk_enable_autoidle_all();
551 void __init omap35xx_init_late(void)
553 omap_common_late_init();
554 omap3_pm_init();
555 omap2_clk_enable_autoidle_all();
558 void __init omap3630_init_late(void)
560 omap_common_late_init();
561 omap3_pm_init();
562 omap2_clk_enable_autoidle_all();
565 void __init am35xx_init_late(void)
567 omap_common_late_init();
568 omap3_pm_init();
569 omap2_clk_enable_autoidle_all();
572 void __init ti81xx_init_late(void)
574 omap_common_late_init();
575 omap3_pm_init();
576 omap2_clk_enable_autoidle_all();
578 #endif
580 #ifdef CONFIG_SOC_AM33XX
581 void __init am33xx_init_early(void)
583 omap2_set_globals_tap(AM335X_CLASS,
584 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
585 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
586 NULL);
587 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
588 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
589 omap3xxx_check_revision();
590 am33xx_check_features();
591 am33xx_powerdomains_init();
592 am33xx_clockdomains_init();
593 am33xx_hwmod_init();
594 omap_hwmod_init_postsetup();
595 omap_clk_soc_init = am33xx_dt_clk_init;
598 void __init am33xx_init_late(void)
600 omap_common_late_init();
602 #endif
604 #ifdef CONFIG_SOC_AM43XX
605 void __init am43xx_init_early(void)
607 omap2_set_globals_tap(AM335X_CLASS,
608 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
609 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
610 NULL);
611 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
612 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
613 omap_prm_base_init();
614 omap_cm_base_init();
615 omap3xxx_check_revision();
616 am43xx_powerdomains_init();
617 am43xx_clockdomains_init();
618 am43xx_hwmod_init();
619 omap_hwmod_init_postsetup();
620 omap_clk_soc_init = am43xx_dt_clk_init;
623 void __init am43xx_init_late(void)
625 omap_common_late_init();
627 #endif
629 #ifdef CONFIG_ARCH_OMAP4
630 void __init omap4430_init_early(void)
632 omap2_set_globals_tap(OMAP443X_CLASS,
633 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
634 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
635 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
636 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
637 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
638 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
639 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
640 omap_prm_base_init();
641 omap_cm_base_init();
642 omap4xxx_check_revision();
643 omap4xxx_check_features();
644 omap4_pm_init_early();
645 omap44xx_prm_init();
646 omap44xx_voltagedomains_init();
647 omap44xx_powerdomains_init();
648 omap44xx_clockdomains_init();
649 omap44xx_hwmod_init();
650 omap_hwmod_init_postsetup();
651 omap_clk_soc_init = omap4xxx_dt_clk_init;
654 void __init omap4430_init_late(void)
656 omap_common_late_init();
657 omap4_pm_init();
658 omap2_clk_enable_autoidle_all();
660 #endif
662 #ifdef CONFIG_SOC_OMAP5
663 void __init omap5_init_early(void)
665 omap2_set_globals_tap(OMAP54XX_CLASS,
666 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
667 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
668 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
669 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
670 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
671 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
672 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
673 omap_prm_base_init();
674 omap_cm_base_init();
675 omap44xx_prm_init();
676 omap5xxx_check_revision();
677 omap54xx_voltagedomains_init();
678 omap54xx_powerdomains_init();
679 omap54xx_clockdomains_init();
680 omap54xx_hwmod_init();
681 omap_hwmod_init_postsetup();
682 omap_clk_soc_init = omap5xxx_dt_clk_init;
685 void __init omap5_init_late(void)
687 omap_common_late_init();
689 #endif
691 #ifdef CONFIG_SOC_DRA7XX
692 void __init dra7xx_init_early(void)
694 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
695 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
696 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
697 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
698 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
699 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
700 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
701 omap_prm_base_init();
702 omap_cm_base_init();
703 omap44xx_prm_init();
704 dra7xx_powerdomains_init();
705 dra7xx_clockdomains_init();
706 dra7xx_hwmod_init();
707 omap_hwmod_init_postsetup();
708 omap_clk_soc_init = dra7xx_dt_clk_init;
711 void __init dra7xx_init_late(void)
713 omap_common_late_init();
715 #endif
718 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
719 struct omap_sdrc_params *sdrc_cs1)
721 omap_sram_init();
723 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
724 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
725 _omap2_init_reprogram_sdrc();
729 int __init omap_clk_init(void)
731 int ret = 0;
733 if (!omap_clk_soc_init)
734 return 0;
736 ret = of_prcm_init();
737 if (!ret)
738 ret = omap_clk_soc_init();
740 return ret;