arch/arm/mach-omap2/omap4-common.c

   1 /*
   2  * OMAP4 specific common source file.
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc.
   5  * Author:
   6  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   7  *
   8  *
   9  * This program is free software,you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/irqchip.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/memblock.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/export.h>
  24 #include <linux/irqchip/arm-gic.h>
  25 #include <linux/of_address.h>
  26 #include <linux/reboot.h>
  27
  28 #include <asm/hardware/cache-l2x0.h>
  29 #include <asm/mach/map.h>
  30 #include <asm/memblock.h>
  31 #include <asm/smp_twd.h>
  32
  33 #include "omap-wakeupgen.h"
  34 #include "soc.h"
  35 #include "iomap.h"
  36 #include "common.h"
  37 #include "mmc.h"
  38 #include "prminst44xx.h"
  39 #include "prcm_mpu44xx.h"
  40 #include "omap4-sar-layout.h"
  41 #include "omap-secure.h"
  42 #include "sram.h"
  43
  44 #ifdef CONFIG_CACHE_L2X0
  45 static void __iomem *l2cache_base;
  46 #endif
  47
  48 static void __iomem *sar_ram_base;
  49 static void __iomem *gic_dist_base_addr;
  50 static void __iomem *twd_base;
  51
  52 #define IRQ_LOCALTIMER          29
  53
  54 #ifdef CONFIG_OMAP4_ERRATA_I688
  55 /* Used to implement memory barrier on DRAM path */
  56 #define OMAP4_DRAM_BARRIER_VA                   0xfe600000
  57
  58 void __iomem *dram_sync, *sram_sync;
  59
  60 static phys_addr_t paddr;
  61 static u32 size;
  62
  63 void omap_bus_sync(void)
  64 {
  65         if (dram_sync && sram_sync) {
  66                 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
  67                 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
  68                 isb();
  69         }
  70 }
  71 EXPORT_SYMBOL(omap_bus_sync);
  72
  73 /* Steal one page physical memory for barrier implementation */
  74 int __init omap_barrier_reserve_memblock(void)
  75 {
  76
  77         size = ALIGN(PAGE_SIZE, SZ_1M);
  78         paddr = arm_memblock_steal(size, SZ_1M);
  79
  80         return 0;
  81 }
  82
  83 void __init omap_barriers_init(void)
  84 {
  85         struct map_desc dram_io_desc[1];
  86
  87         dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
  88         dram_io_desc[0].pfn = __phys_to_pfn(paddr);
  89         dram_io_desc[0].length = size;
  90         dram_io_desc[0].type = MT_MEMORY_RW_SO;
  91         iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
  92         dram_sync = (void __iomem *) dram_io_desc[0].virtual;
  93         sram_sync = (void __iomem *) OMAP4_SRAM_VA;
  94
  95         pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
  96                 (long long) paddr, dram_io_desc[0].virtual);
  97
  98 }
  99 #else
 100 void __init omap_barriers_init(void)
 101 {}
 102 #endif
 103
 104 void __init gic_init_irq(void)
 105 {
 106         void __iomem *omap_irq_base;
 107
 108         /* Static mapping, never released */
 109         gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
 110         BUG_ON(!gic_dist_base_addr);
 111
 112         twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
 113         BUG_ON(!twd_base);
 114
 115         /* Static mapping, never released */
 116         omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
 117         BUG_ON(!omap_irq_base);
 118
 119         omap_wakeupgen_init();
 120
 121         gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
 122 }
 123
 124 void gic_dist_disable(void)
 125 {
 126         if (gic_dist_base_addr)
 127                 __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
 128 }
 129
 130 void gic_dist_enable(void)
 131 {
 132         if (gic_dist_base_addr)
 133                 __raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
 134 }
 135
 136 bool gic_dist_disabled(void)
 137 {
 138         return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
 139 }
 140
 141 void gic_timer_retrigger(void)
 142 {
 143         u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
 144         u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
 145         u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
 146
 147         if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
 148                 /*
 149                  * The local timer interrupt got lost while the distributor was
 150                  * disabled.  Ack the pending interrupt, and retrigger it.
 151                  */
 152                 pr_warn("%s: lost localtimer interrupt\n", __func__);
 153                 __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
 154                 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
 155                         __raw_writel(1, twd_base + TWD_TIMER_COUNTER);
 156                         twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
 157                         __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
 158                 }
 159         }
 160 }
 161
 162 #ifdef CONFIG_CACHE_L2X0
 163
 164 void __iomem *omap4_get_l2cache_base(void)
 165 {
 166         return l2cache_base;
 167 }
 168
 169 static void omap4_l2x0_disable(void)
 170 {
 171         outer_flush_all();
 172         /* Disable PL310 L2 Cache controller */
 173         omap_smc1(0x102, 0x0);
 174 }
 175
 176 static void omap4_l2x0_set_debug(unsigned long val)
 177 {
 178         /* Program PL310 L2 Cache controller debug register */
 179         omap_smc1(0x100, val);
 180 }
 181
 182 static int __init omap_l2_cache_init(void)
 183 {
 184         u32 aux_ctrl = 0;
 185
 186         /*
 187          * To avoid code running on other OMAPs in
 188          * multi-omap builds
 189          */
 190         if (!cpu_is_omap44xx())
 191                 return -ENODEV;
 192
 193         /* Static mapping, never released */
 194         l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
 195         if (WARN_ON(!l2cache_base))
 196                 return -ENOMEM;
 197
 198         /*
 199          * 16-way associativity, parity disabled
 200          * Way size - 32KB (es1.0)
 201          * Way size - 64KB (es2.0 +)
 202          */
 203         aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
 204                         (0x1 << 25) |
 205                         (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
 206                         (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
 207
 208         if (omap_rev() == OMAP4430_REV_ES1_0) {
 209                 aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
 210         } else {
 211                 aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
 212                         (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
 213                         (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
 214                         (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
 215                         (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
 216         }
 217         if (omap_rev() != OMAP4430_REV_ES1_0)
 218                 omap_smc1(0x109, aux_ctrl);
 219
 220         /* Enable PL310 L2 Cache controller */
 221         omap_smc1(0x102, 0x1);
 222
 223         if (of_have_populated_dt())
 224                 l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
 225         else
 226                 l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
 227
 228         /*
 229          * Override default outer_cache.disable with a OMAP4
 230          * specific one
 231         */
 232         outer_cache.disable = omap4_l2x0_disable;
 233         outer_cache.set_debug = omap4_l2x0_set_debug;
 234
 235         return 0;
 236 }
 237 omap_early_initcall(omap_l2_cache_init);
 238 #endif
 239
 240 void __iomem *omap4_get_sar_ram_base(void)
 241 {
 242         return sar_ram_base;
 243 }
 244
 245 /*
 246  * SAR RAM used to save and restore the HW
 247  * context in low power modes
 248  */
 249 static int __init omap4_sar_ram_init(void)
 250 {
 251         unsigned long sar_base;
 252
 253         /*
 254          * To avoid code running on other OMAPs in
 255          * multi-omap builds
 256          */
 257         if (cpu_is_omap44xx())
 258                 sar_base = OMAP44XX_SAR_RAM_BASE;
 259         else if (soc_is_omap54xx())
 260                 sar_base = OMAP54XX_SAR_RAM_BASE;
 261         else
 262                 return -ENOMEM;
 263
 264         /* Static mapping, never released */
 265         sar_ram_base = ioremap(sar_base, SZ_16K);
 266         if (WARN_ON(!sar_ram_base))
 267                 return -ENOMEM;
 268
 269         return 0;
 270 }
 271 omap_early_initcall(omap4_sar_ram_init);
 272
 273 void __init omap_gic_of_init(void)
 274 {
 275         struct device_node *np;
 276
 277         /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
 278         if (!cpu_is_omap446x())
 279                 goto skip_errata_init;
 280
 281         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
 282         gic_dist_base_addr = of_iomap(np, 0);
 283         WARN_ON(!gic_dist_base_addr);
 284
 285         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
 286         twd_base = of_iomap(np, 0);
 287         WARN_ON(!twd_base);
 288
 289 skip_errata_init:
 290         omap_wakeupgen_init();
 291         irqchip_init();
 292 }