arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/platform_data/gpio-omap.h>
  13 #include <linux/omap-dma.h>
  14 #include <plat/dmtimer.h>
  15 #include <linux/platform_data/spi-omap2-mcspi.h>
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_common_data.h"
  19 #include "cm-regbits-24xx.h"
  20 #include "prm-regbits-24xx.h"
  21 #include "wd_timer.h"
  22
  23 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
  24         { .name = "dispc", .dma_req = 5 },
  25         { .dma_req = -1, },
  26 };
  27
  28 /*
  29  * 'dispc' class
  30  * display controller
  31  */
  32
  33 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  34         .rev_offs       = 0x0000,
  35         .sysc_offs      = 0x0010,
  36         .syss_offs      = 0x0014,
  37         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  38                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  39         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  40                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  41         .sysc_fields    = &omap_hwmod_sysc_type1,
  42 };
  43
  44 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  45         .name   = "dispc",
  46         .sysc   = &omap2_dispc_sysc,
  47 };
  48
  49 /* OMAP2xxx Timer Common */
  50 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  51         .rev_offs       = 0x0000,
  52         .sysc_offs      = 0x0010,
  53         .syss_offs      = 0x0014,
  54         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  55                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  56                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  57         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  58         .clockact       = CLOCKACT_TEST_ICLK,
  59         .sysc_fields    = &omap_hwmod_sysc_type1,
  60 };
  61
  62 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  63         .name   = "timer",
  64         .sysc   = &omap2xxx_timer_sysc,
  65 };
  66
  67 /*
  68  * 'wd_timer' class
  69  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  70  * overflow condition
  71  */
  72
  73 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  74         .rev_offs       = 0x0000,
  75         .sysc_offs      = 0x0010,
  76         .syss_offs      = 0x0014,
  77         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  78                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  79         .sysc_fields    = &omap_hwmod_sysc_type1,
  80 };
  81
  82 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  83         .name           = "wd_timer",
  84         .sysc           = &omap2xxx_wd_timer_sysc,
  85         .pre_shutdown   = &omap2_wd_timer_disable,
  86         .reset          = &omap2_wd_timer_reset,
  87 };
  88
  89 /*
  90  * 'gpio' class
  91  * general purpose io module
  92  */
  93 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
  94         .rev_offs       = 0x0000,
  95         .sysc_offs      = 0x0010,
  96         .syss_offs      = 0x0014,
  97         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  98                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  99                            SYSS_HAS_RESET_STATUS),
 100         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 101         .sysc_fields    = &omap_hwmod_sysc_type1,
 102 };
 103
 104 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
 105         .name = "gpio",
 106         .sysc = &omap2xxx_gpio_sysc,
 107         .rev = 0,
 108 };
 109
 110 /* system dma */
 111 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
 112         .rev_offs       = 0x0000,
 113         .sysc_offs      = 0x002c,
 114         .syss_offs      = 0x0028,
 115         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 116                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 117                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 118         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 119         .sysc_fields    = &omap_hwmod_sysc_type1,
 120 };
 121
 122 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
 123         .name   = "dma",
 124         .sysc   = &omap2xxx_dma_sysc,
 125 };
 126
 127 /*
 128  * 'mailbox' class
 129  * mailbox module allowing communication between the on-chip processors
 130  * using a queued mailbox-interrupt mechanism.
 131  */
 132
 133 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 134         .rev_offs       = 0x000,
 135         .sysc_offs      = 0x010,
 136         .syss_offs      = 0x014,
 137         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 138                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 139         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 140         .sysc_fields    = &omap_hwmod_sysc_type1,
 141 };
 142
 143 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 144         .name   = "mailbox",
 145         .sysc   = &omap2xxx_mailbox_sysc,
 146 };
 147
 148 /*
 149  * 'mcspi' class
 150  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 151  * bus
 152  */
 153
 154 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 155         .rev_offs       = 0x0000,
 156         .sysc_offs      = 0x0010,
 157         .syss_offs      = 0x0014,
 158         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 159                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 160                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 161         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 162         .sysc_fields    = &omap_hwmod_sysc_type1,
 163 };
 164
 165 struct omap_hwmod_class omap2xxx_mcspi_class = {
 166         .name   = "mcspi",
 167         .sysc   = &omap2xxx_mcspi_sysc,
 168         .rev    = OMAP2_MCSPI_REV,
 169 };
 170
 171 /*
 172  * 'gpmc' class
 173  * general purpose memory controller
 174  */
 175
 176 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
 177         .rev_offs       = 0x0000,
 178         .sysc_offs      = 0x0010,
 179         .syss_offs      = 0x0014,
 180         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 181                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 182         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 183         .sysc_fields    = &omap_hwmod_sysc_type1,
 184 };
 185
 186 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
 187         .name   = "gpmc",
 188         .sysc   = &omap2xxx_gpmc_sysc,
 189 };
 190
 191 /*
 192  * IP blocks
 193  */
 194
 195 /* L3 */
 196 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 197         .name           = "l3_main",
 198         .class          = &l3_hwmod_class,
 199         .flags          = HWMOD_NO_IDLEST,
 200 };
 201
 202 /* L4 CORE */
 203 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 204         .name           = "l4_core",
 205         .class          = &l4_hwmod_class,
 206         .flags          = HWMOD_NO_IDLEST,
 207 };
 208
 209 /* L4 WKUP */
 210 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 211         .name           = "l4_wkup",
 212         .class          = &l4_hwmod_class,
 213         .flags          = HWMOD_NO_IDLEST,
 214 };
 215
 216 /* MPU */
 217 struct omap_hwmod omap2xxx_mpu_hwmod = {
 218         .name           = "mpu",
 219         .class          = &mpu_hwmod_class,
 220         .main_clk       = "mpu_ck",
 221 };
 222
 223 /* IVA2 */
 224 struct omap_hwmod omap2xxx_iva_hwmod = {
 225         .name           = "iva",
 226         .class          = &iva_hwmod_class,
 227 };
 228
 229 /* always-on timers dev attribute */
 230 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 231         .timer_capability       = OMAP_TIMER_ALWON,
 232 };
 233
 234 /* pwm timers dev attribute */
 235 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 236         .timer_capability       = OMAP_TIMER_HAS_PWM,
 237 };
 238
 239 /* timers with DSP interrupt dev attribute */
 240 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 241         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 242 };
 243
 244 /* timer1 */
 245
 246 struct omap_hwmod omap2xxx_timer1_hwmod = {
 247         .name           = "timer1",
 248         .main_clk       = "gpt1_fck",
 249         .prcm           = {
 250                 .omap2 = {
 251                         .prcm_reg_id = 1,
 252                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 253                         .module_offs = WKUP_MOD,
 254                         .idlest_reg_id = 1,
 255                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 256                 },
 257         },
 258         .dev_attr       = &capability_alwon_dev_attr,
 259         .class          = &omap2xxx_timer_hwmod_class,
 260         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 261 };
 262
 263 /* timer2 */
 264
 265 struct omap_hwmod omap2xxx_timer2_hwmod = {
 266         .name           = "timer2",
 267         .main_clk       = "gpt2_fck",
 268         .prcm           = {
 269                 .omap2 = {
 270                         .prcm_reg_id = 1,
 271                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 272                         .module_offs = CORE_MOD,
 273                         .idlest_reg_id = 1,
 274                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 275                 },
 276         },
 277         .class          = &omap2xxx_timer_hwmod_class,
 278         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 279 };
 280
 281 /* timer3 */
 282
 283 struct omap_hwmod omap2xxx_timer3_hwmod = {
 284         .name           = "timer3",
 285         .main_clk       = "gpt3_fck",
 286         .prcm           = {
 287                 .omap2 = {
 288                         .prcm_reg_id = 1,
 289                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 290                         .module_offs = CORE_MOD,
 291                         .idlest_reg_id = 1,
 292                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 293                 },
 294         },
 295         .class          = &omap2xxx_timer_hwmod_class,
 296         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 297 };
 298
 299 /* timer4 */
 300
 301 struct omap_hwmod omap2xxx_timer4_hwmod = {
 302         .name           = "timer4",
 303         .main_clk       = "gpt4_fck",
 304         .prcm           = {
 305                 .omap2 = {
 306                         .prcm_reg_id = 1,
 307                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 308                         .module_offs = CORE_MOD,
 309                         .idlest_reg_id = 1,
 310                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 311                 },
 312         },
 313         .class          = &omap2xxx_timer_hwmod_class,
 314         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 315 };
 316
 317 /* timer5 */
 318
 319 struct omap_hwmod omap2xxx_timer5_hwmod = {
 320         .name           = "timer5",
 321         .main_clk       = "gpt5_fck",
 322         .prcm           = {
 323                 .omap2 = {
 324                         .prcm_reg_id = 1,
 325                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 326                         .module_offs = CORE_MOD,
 327                         .idlest_reg_id = 1,
 328                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 329                 },
 330         },
 331         .dev_attr       = &capability_dsp_dev_attr,
 332         .class          = &omap2xxx_timer_hwmod_class,
 333         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 334 };
 335
 336 /* timer6 */
 337
 338 struct omap_hwmod omap2xxx_timer6_hwmod = {
 339         .name           = "timer6",
 340         .main_clk       = "gpt6_fck",
 341         .prcm           = {
 342                 .omap2 = {
 343                         .prcm_reg_id = 1,
 344                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 345                         .module_offs = CORE_MOD,
 346                         .idlest_reg_id = 1,
 347                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 348                 },
 349         },
 350         .dev_attr       = &capability_dsp_dev_attr,
 351         .class          = &omap2xxx_timer_hwmod_class,
 352         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 353 };
 354
 355 /* timer7 */
 356
 357 struct omap_hwmod omap2xxx_timer7_hwmod = {
 358         .name           = "timer7",
 359         .main_clk       = "gpt7_fck",
 360         .prcm           = {
 361                 .omap2 = {
 362                         .prcm_reg_id = 1,
 363                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 364                         .module_offs = CORE_MOD,
 365                         .idlest_reg_id = 1,
 366                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 367                 },
 368         },
 369         .dev_attr       = &capability_dsp_dev_attr,
 370         .class          = &omap2xxx_timer_hwmod_class,
 371         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 372 };
 373
 374 /* timer8 */
 375
 376 struct omap_hwmod omap2xxx_timer8_hwmod = {
 377         .name           = "timer8",
 378         .main_clk       = "gpt8_fck",
 379         .prcm           = {
 380                 .omap2 = {
 381                         .prcm_reg_id = 1,
 382                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 383                         .module_offs = CORE_MOD,
 384                         .idlest_reg_id = 1,
 385                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 386                 },
 387         },
 388         .dev_attr       = &capability_dsp_dev_attr,
 389         .class          = &omap2xxx_timer_hwmod_class,
 390         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 391 };
 392
 393 /* timer9 */
 394
 395 struct omap_hwmod omap2xxx_timer9_hwmod = {
 396         .name           = "timer9",
 397         .main_clk       = "gpt9_fck",
 398         .prcm           = {
 399                 .omap2 = {
 400                         .prcm_reg_id = 1,
 401                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 402                         .module_offs = CORE_MOD,
 403                         .idlest_reg_id = 1,
 404                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 405                 },
 406         },
 407         .dev_attr       = &capability_pwm_dev_attr,
 408         .class          = &omap2xxx_timer_hwmod_class,
 409         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 410 };
 411
 412 /* timer10 */
 413
 414 struct omap_hwmod omap2xxx_timer10_hwmod = {
 415         .name           = "timer10",
 416         .main_clk       = "gpt10_fck",
 417         .prcm           = {
 418                 .omap2 = {
 419                         .prcm_reg_id = 1,
 420                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 421                         .module_offs = CORE_MOD,
 422                         .idlest_reg_id = 1,
 423                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 424                 },
 425         },
 426         .dev_attr       = &capability_pwm_dev_attr,
 427         .class          = &omap2xxx_timer_hwmod_class,
 428         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 429 };
 430
 431 /* timer11 */
 432
 433 struct omap_hwmod omap2xxx_timer11_hwmod = {
 434         .name           = "timer11",
 435         .main_clk       = "gpt11_fck",
 436         .prcm           = {
 437                 .omap2 = {
 438                         .prcm_reg_id = 1,
 439                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 440                         .module_offs = CORE_MOD,
 441                         .idlest_reg_id = 1,
 442                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 443                 },
 444         },
 445         .dev_attr       = &capability_pwm_dev_attr,
 446         .class          = &omap2xxx_timer_hwmod_class,
 447         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 448 };
 449
 450 /* timer12 */
 451
 452 struct omap_hwmod omap2xxx_timer12_hwmod = {
 453         .name           = "timer12",
 454         .main_clk       = "gpt12_fck",
 455         .prcm           = {
 456                 .omap2 = {
 457                         .prcm_reg_id = 1,
 458                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 459                         .module_offs = CORE_MOD,
 460                         .idlest_reg_id = 1,
 461                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 462                 },
 463         },
 464         .dev_attr       = &capability_pwm_dev_attr,
 465         .class          = &omap2xxx_timer_hwmod_class,
 466         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 467 };
 468
 469 /* wd_timer2 */
 470 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 471         .name           = "wd_timer2",
 472         .class          = &omap2xxx_wd_timer_hwmod_class,
 473         .main_clk       = "mpu_wdt_fck",
 474         .prcm           = {
 475                 .omap2 = {
 476                         .prcm_reg_id = 1,
 477                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 478                         .module_offs = WKUP_MOD,
 479                         .idlest_reg_id = 1,
 480                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 481                 },
 482         },
 483 };
 484
 485 /* UART1 */
 486
 487 struct omap_hwmod omap2xxx_uart1_hwmod = {
 488         .name           = "uart1",
 489         .main_clk       = "uart1_fck",
 490         .flags          = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 491         .prcm           = {
 492                 .omap2 = {
 493                         .module_offs = CORE_MOD,
 494                         .prcm_reg_id = 1,
 495                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 496                         .idlest_reg_id = 1,
 497                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 498                 },
 499         },
 500         .class          = &omap2_uart_class,
 501 };
 502
 503 /* UART2 */
 504
 505 struct omap_hwmod omap2xxx_uart2_hwmod = {
 506         .name           = "uart2",
 507         .main_clk       = "uart2_fck",
 508         .flags          = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 509         .prcm           = {
 510                 .omap2 = {
 511                         .module_offs = CORE_MOD,
 512                         .prcm_reg_id = 1,
 513                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 514                         .idlest_reg_id = 1,
 515                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 516                 },
 517         },
 518         .class          = &omap2_uart_class,
 519 };
 520
 521 /* UART3 */
 522
 523 struct omap_hwmod omap2xxx_uart3_hwmod = {
 524         .name           = "uart3",
 525         .main_clk       = "uart3_fck",
 526         .flags          = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 527         .prcm           = {
 528                 .omap2 = {
 529                         .module_offs = CORE_MOD,
 530                         .prcm_reg_id = 2,
 531                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 532                         .idlest_reg_id = 2,
 533                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 534                 },
 535         },
 536         .class          = &omap2_uart_class,
 537 };
 538
 539 /* dss */
 540
 541 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 542         /*
 543          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 544          * driver does not use these clocks.
 545          */
 546         { .role = "tv_clk", .clk = "dss_54m_fck" },
 547         { .role = "sys_clk", .clk = "dss2_fck" },
 548 };
 549
 550 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 551         .name           = "dss_core",
 552         .class          = &omap2_dss_hwmod_class,
 553         .main_clk       = "dss1_fck", /* instead of dss_fck */
 554         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 555         .prcm           = {
 556                 .omap2 = {
 557                         .prcm_reg_id = 1,
 558                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 559                         .module_offs = CORE_MOD,
 560                         .idlest_reg_id = 1,
 561                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 562                 },
 563         },
 564         .opt_clks       = dss_opt_clks,
 565         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 566         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 567 };
 568
 569 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 570         .name           = "dss_dispc",
 571         .class          = &omap2_dispc_hwmod_class,
 572         .mpu_irqs       = omap2_dispc_irqs,
 573         .main_clk       = "dss1_fck",
 574         .prcm           = {
 575                 .omap2 = {
 576                         .prcm_reg_id = 1,
 577                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 578                         .module_offs = CORE_MOD,
 579                         .idlest_reg_id = 1,
 580                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 581                 },
 582         },
 583         .flags          = HWMOD_NO_IDLEST,
 584         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 585 };
 586
 587 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 588         { .role = "ick", .clk = "dss_ick" },
 589 };
 590
 591 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 592         .name           = "dss_rfbi",
 593         .class          = &omap2_rfbi_hwmod_class,
 594         .main_clk       = "dss1_fck",
 595         .prcm           = {
 596                 .omap2 = {
 597                         .prcm_reg_id = 1,
 598                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 599                         .module_offs = CORE_MOD,
 600                 },
 601         },
 602         .opt_clks       = dss_rfbi_opt_clks,
 603         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 604         .flags          = HWMOD_NO_IDLEST,
 605 };
 606
 607 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 608         .name           = "dss_venc",
 609         .class          = &omap2_venc_hwmod_class,
 610         .main_clk       = "dss_54m_fck",
 611         .prcm           = {
 612                 .omap2 = {
 613                         .prcm_reg_id = 1,
 614                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 615                         .module_offs = CORE_MOD,
 616                 },
 617         },
 618         .flags          = HWMOD_NO_IDLEST,
 619 };
 620
 621 /* gpio dev_attr */
 622 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
 623         .bank_width = 32,
 624         .dbck_flag = false,
 625 };
 626
 627 /* gpio1 */
 628 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 629         .name           = "gpio1",
 630         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 631         .main_clk       = "gpios_fck",
 632         .prcm           = {
 633                 .omap2 = {
 634                         .prcm_reg_id = 1,
 635                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 636                         .module_offs = WKUP_MOD,
 637                         .idlest_reg_id = 1,
 638                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 639                 },
 640         },
 641         .class          = &omap2xxx_gpio_hwmod_class,
 642         .dev_attr       = &omap2xxx_gpio_dev_attr,
 643 };
 644
 645 /* gpio2 */
 646 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 647         .name           = "gpio2",
 648         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 649         .main_clk       = "gpios_fck",
 650         .prcm           = {
 651                 .omap2 = {
 652                         .prcm_reg_id = 1,
 653                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 654                         .module_offs = WKUP_MOD,
 655                         .idlest_reg_id = 1,
 656                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 657                 },
 658         },
 659         .class          = &omap2xxx_gpio_hwmod_class,
 660         .dev_attr       = &omap2xxx_gpio_dev_attr,
 661 };
 662
 663 /* gpio3 */
 664 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 665         .name           = "gpio3",
 666         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 667         .main_clk       = "gpios_fck",
 668         .prcm           = {
 669                 .omap2 = {
 670                         .prcm_reg_id = 1,
 671                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 672                         .module_offs = WKUP_MOD,
 673                         .idlest_reg_id = 1,
 674                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 675                 },
 676         },
 677         .class          = &omap2xxx_gpio_hwmod_class,
 678         .dev_attr       = &omap2xxx_gpio_dev_attr,
 679 };
 680
 681 /* gpio4 */
 682 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 683         .name           = "gpio4",
 684         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 685         .main_clk       = "gpios_fck",
 686         .prcm           = {
 687                 .omap2 = {
 688                         .prcm_reg_id = 1,
 689                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 690                         .module_offs = WKUP_MOD,
 691                         .idlest_reg_id = 1,
 692                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 693                 },
 694         },
 695         .class          = &omap2xxx_gpio_hwmod_class,
 696         .dev_attr       = &omap2xxx_gpio_dev_attr,
 697 };
 698
 699 /* mcspi1 */
 700 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 701         .num_chipselect = 4,
 702 };
 703
 704 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 705         .name           = "mcspi1",
 706         .main_clk       = "mcspi1_fck",
 707         .prcm           = {
 708                 .omap2 = {
 709                         .module_offs = CORE_MOD,
 710                         .prcm_reg_id = 1,
 711                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
 712                         .idlest_reg_id = 1,
 713                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 714                 },
 715         },
 716         .class          = &omap2xxx_mcspi_class,
 717         .dev_attr       = &omap_mcspi1_dev_attr,
 718 };
 719
 720 /* mcspi2 */
 721 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 722         .num_chipselect = 2,
 723 };
 724
 725 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 726         .name           = "mcspi2",
 727         .main_clk       = "mcspi2_fck",
 728         .prcm           = {
 729                 .omap2 = {
 730                         .module_offs = CORE_MOD,
 731                         .prcm_reg_id = 1,
 732                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
 733                         .idlest_reg_id = 1,
 734                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 735                 },
 736         },
 737         .class          = &omap2xxx_mcspi_class,
 738         .dev_attr       = &omap_mcspi2_dev_attr,
 739 };
 740
 741 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 742         .name   = "counter",
 743 };
 744
 745 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 746         .name           = "counter_32k",
 747         .main_clk       = "func_32k_ck",
 748         .prcm           = {
 749                 .omap2  = {
 750                         .module_offs = WKUP_MOD,
 751                         .prcm_reg_id = 1,
 752                         .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 753                         .idlest_reg_id = 1,
 754                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 755                 },
 756         },
 757         .class          = &omap2xxx_counter_hwmod_class,
 758 };
 759
 760 /* gpmc */
 761 struct omap_hwmod omap2xxx_gpmc_hwmod = {
 762         .name           = "gpmc",
 763         .class          = &omap2xxx_gpmc_hwmod_class,
 764         .main_clk       = "gpmc_fck",
 765         /*
 766          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
 767          * block.  It is not being added due to any known bugs with
 768          * resetting the GPMC IP block, but rather because any timings
 769          * set by the bootloader are not being correctly programmed by
 770          * the kernel from the board file or DT data.
 771          * HWMOD_INIT_NO_RESET should be removed ASAP.
 772          */
 773         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
 774                            HWMOD_NO_IDLEST),
 775         .prcm           = {
 776                 .omap2  = {
 777                         .prcm_reg_id = 3,
 778                         .module_bit = OMAP24XX_EN_GPMC_MASK,
 779                         .module_offs = CORE_MOD,
 780                 },
 781         },
 782 };
 783
 784 /* RNG */
 785
 786 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
 787         .rev_offs       = 0x3c,
 788         .sysc_offs      = 0x40,
 789         .syss_offs      = 0x44,
 790         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 791                            SYSS_HAS_RESET_STATUS),
 792         .sysc_fields    = &omap_hwmod_sysc_type1,
 793 };
 794
 795 static struct omap_hwmod_class omap2_rng_hwmod_class = {
 796         .name           = "rng",
 797         .sysc           = &omap2_rng_sysc,
 798 };
 799
 800 struct omap_hwmod omap2xxx_rng_hwmod = {
 801         .name           = "rng",
 802         .main_clk       = "l4_ck",
 803         .prcm           = {
 804                 .omap2 = {
 805                         .module_offs = CORE_MOD,
 806                         .prcm_reg_id = 4,
 807                         .module_bit = OMAP24XX_EN_RNG_SHIFT,
 808                         .idlest_reg_id = 4,
 809                         .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
 810                 },
 811         },
 812         /*
 813          * XXX The first read from the SYSSTATUS register of the RNG
 814          * after the SYSCONFIG SOFTRESET bit is set triggers an
 815          * imprecise external abort.  It's unclear why this happens.
 816          * Until this is analyzed, skip the IP block reset.
 817          */
 818         .flags          = HWMOD_INIT_NO_RESET,
 819         .class          = &omap2_rng_hwmod_class,
 820 };
 821
 822 /* SHAM */
 823
 824 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
 825         .rev_offs       = 0x5c,
 826         .sysc_offs      = 0x60,
 827         .syss_offs      = 0x64,
 828         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 829                            SYSS_HAS_RESET_STATUS),
 830         .sysc_fields    = &omap_hwmod_sysc_type1,
 831 };
 832
 833 static struct omap_hwmod_class omap2xxx_sham_class = {
 834         .name   = "sham",
 835         .sysc   = &omap2_sham_sysc,
 836 };
 837
 838 struct omap_hwmod omap2xxx_sham_hwmod = {
 839         .name           = "sham",
 840         .main_clk       = "l4_ck",
 841         .prcm           = {
 842                 .omap2 = {
 843                         .module_offs = CORE_MOD,
 844                         .prcm_reg_id = 4,
 845                         .module_bit = OMAP24XX_EN_SHA_SHIFT,
 846                         .idlest_reg_id = 4,
 847                         .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
 848                 },
 849         },
 850         .class          = &omap2xxx_sham_class,
 851 };
 852
 853 /* AES */
 854
 855 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
 856         .rev_offs       = 0x44,
 857         .sysc_offs      = 0x48,
 858         .syss_offs      = 0x4c,
 859         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 860                            SYSS_HAS_RESET_STATUS),
 861         .sysc_fields    = &omap_hwmod_sysc_type1,
 862 };
 863
 864 static struct omap_hwmod_class omap2xxx_aes_class = {
 865         .name   = "aes",
 866         .sysc   = &omap2_aes_sysc,
 867 };
 868
 869 struct omap_hwmod omap2xxx_aes_hwmod = {
 870         .name           = "aes",
 871         .main_clk       = "l4_ck",
 872         .prcm           = {
 873                 .omap2 = {
 874                         .module_offs = CORE_MOD,
 875                         .prcm_reg_id = 4,
 876                         .module_bit = OMAP24XX_EN_AES_SHIFT,
 877                         .idlest_reg_id = 4,
 878                         .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
 879                 },
 880         },
 881         .class          = &omap2xxx_aes_class,
 882 };