arch/arm/mach-omap2/prminst44xx.c

   1 /*
   2  * OMAP4 PRM instance functions
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Copyright (C) 2011 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/errno.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18
  19 #include "iomap.h"
  20 #include "common.h"
  21 #include "prcm-common.h"
  22 #include "prm44xx.h"
  23 #include "prm54xx.h"
  24 #include "prm7xx.h"
  25 #include "prminst44xx.h"
  26 #include "prm-regbits-44xx.h"
  27 #include "prcm44xx.h"
  28 #include "prcm_mpu44xx.h"
  29 #include "soc.h"
  30
  31 static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
  32
  33 /**
  34  * omap_prm_base_init - Populates the prm partitions
  35  *
  36  * Populates the base addresses of the _prm_bases
  37  * array used for read/write of prm module registers.
  38  */
  39 void omap_prm_base_init(void)
  40 {
  41         _prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
  42         _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
  43 }
  44
  45 /* Read a register in a PRM instance */
  46 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
  47 {
  48         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
  49                part == OMAP4430_INVALID_PRCM_PARTITION ||
  50                !_prm_bases[part]);
  51         return __raw_readl(_prm_bases[part] + inst + idx);
  52 }
  53
  54 /* Write into a register in a PRM instance */
  55 void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
  56 {
  57         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
  58                part == OMAP4430_INVALID_PRCM_PARTITION ||
  59                !_prm_bases[part]);
  60         __raw_writel(val, _prm_bases[part] + inst + idx);
  61 }
  62
  63 /* Read-modify-write a register in PRM. Caller must lock */
  64 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
  65                                     u16 idx)
  66 {
  67         u32 v;
  68
  69         v = omap4_prminst_read_inst_reg(part, inst, idx);
  70         v &= ~mask;
  71         v |= bits;
  72         omap4_prminst_write_inst_reg(v, part, inst, idx);
  73
  74         return v;
  75 }
  76
  77 /*
  78  * Address offset (in bytes) between the reset control and the reset
  79  * status registers: 4 bytes on OMAP4
  80  */
  81 #define OMAP4_RST_CTRL_ST_OFFSET                4
  82
  83 /**
  84  * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
  85  * submodules contained in the hwmod module
  86  * @rstctrl_reg: RM_RSTCTRL register address for this module
  87  * @shift: register bit shift corresponding to the reset line to check
  88  *
  89  * Returns 1 if the (sub)module hardreset line is currently asserted,
  90  * 0 if the (sub)module hardreset line is not currently asserted, or
  91  * -EINVAL upon parameter error.
  92  */
  93 int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
  94                                         u16 rstctrl_offs)
  95 {
  96         u32 v;
  97
  98         v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
  99         v &= 1 << shift;
 100         v >>= shift;
 101
 102         return v;
 103 }
 104
 105 /**
 106  * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
 107  * @rstctrl_reg: RM_RSTCTRL register address for this module
 108  * @shift: register bit shift corresponding to the reset line to assert
 109  *
 110  * Some IPs like dsp, ipu or iva contain processors that require an HW
 111  * reset line to be asserted / deasserted in order to fully enable the
 112  * IP.  These modules may have multiple hard-reset lines that reset
 113  * different 'submodules' inside the IP block.  This function will
 114  * place the submodule into reset.  Returns 0 upon success or -EINVAL
 115  * upon an argument error.
 116  */
 117 int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
 118                                    u16 rstctrl_offs)
 119 {
 120         u32 mask = 1 << shift;
 121
 122         omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
 123
 124         return 0;
 125 }
 126
 127 /**
 128  * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
 129  * wait
 130  * @rstctrl_reg: RM_RSTCTRL register address for this module
 131  * @shift: register bit shift corresponding to the reset line to deassert
 132  *
 133  * Some IPs like dsp, ipu or iva contain processors that require an HW
 134  * reset line to be asserted / deasserted in order to fully enable the
 135  * IP.  These modules may have multiple hard-reset lines that reset
 136  * different 'submodules' inside the IP block.  This function will
 137  * take the submodule out of reset and wait until the PRCM indicates
 138  * that the reset has completed before returning.  Returns 0 upon success or
 139  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 140  * of reset, or -EBUSY if the submodule did not exit reset promptly.
 141  */
 142 int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
 143                                      u16 rstctrl_offs)
 144 {
 145         int c;
 146         u32 mask = 1 << shift;
 147         u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
 148
 149         /* Check the current status to avoid de-asserting the line twice */
 150         if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
 151                                                 rstctrl_offs) == 0)
 152                 return -EEXIST;
 153
 154         /* Clear the reset status by writing 1 to the status bit */
 155         omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
 156                                         rstst_offs);
 157         /* de-assert the reset control line */
 158         omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
 159         /* wait the status to be set */
 160         omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
 161                                                               rstst_offs),
 162                           MAX_MODULE_HARDRESET_WAIT, c);
 163
 164         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 165 }
 166
 167
 168 void omap4_prminst_global_warm_sw_reset(void)
 169 {
 170         u32 v;
 171         s16 dev_inst;
 172
 173         if (cpu_is_omap44xx())
 174                 dev_inst = OMAP4430_PRM_DEVICE_INST;
 175         else if (soc_is_omap54xx())
 176                 dev_inst = OMAP54XX_PRM_DEVICE_INST;
 177         else if (soc_is_dra7xx())
 178                 dev_inst = DRA7XX_PRM_DEVICE_INST;
 179         else
 180                 return;
 181
 182         v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
 183                                         OMAP4_PRM_RSTCTRL_OFFSET);
 184         v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
 185         omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
 186                                  OMAP4430_PRM_DEVICE_INST,
 187                                  OMAP4_PRM_RSTCTRL_OFFSET);
 188
 189         /* OCP barrier */
 190         v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 191                                     OMAP4430_PRM_DEVICE_INST,
 192                                     OMAP4_PRM_RSTCTRL_OFFSET);
 193 }