2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/platform_device.h>
43 #include <linux/platform_data/dmtimer-omap.h>
44 #include <linux/sched_clock.h>
46 #include <asm/mach/time.h>
47 #include <asm/smp_twd.h>
49 #include "omap_hwmod.h"
50 #include "omap_device.h"
51 #include <plat/counter-32k.h>
52 #include <plat/dmtimer.h>
57 #include "powerdomain.h"
58 #include "omap-secure.h"
60 #define REALTIME_COUNTER_BASE 0x48243200
61 #define INCREMENTER_NUMERATOR_OFFSET 0x10
62 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
63 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
67 static struct omap_dm_timer clkev
;
68 static struct clock_event_device clockevent_gpt
;
70 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
71 static unsigned long arch_timer_freq
;
73 void set_cntfreq(void)
75 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX
, arch_timer_freq
);
79 static irqreturn_t
omap2_gp_timer_interrupt(int irq
, void *dev_id
)
81 struct clock_event_device
*evt
= &clockevent_gpt
;
83 __omap_dm_timer_write_status(&clkev
, OMAP_TIMER_INT_OVERFLOW
);
85 evt
->event_handler(evt
);
89 static struct irqaction omap2_gp_timer_irq
= {
91 .flags
= IRQF_TIMER
| IRQF_IRQPOLL
,
92 .handler
= omap2_gp_timer_interrupt
,
95 static int omap2_gp_timer_set_next_event(unsigned long cycles
,
96 struct clock_event_device
*evt
)
98 __omap_dm_timer_load_start(&clkev
, OMAP_TIMER_CTRL_ST
,
99 0xffffffff - cycles
, OMAP_TIMER_POSTED
);
104 static void omap2_gp_timer_set_mode(enum clock_event_mode mode
,
105 struct clock_event_device
*evt
)
109 __omap_dm_timer_stop(&clkev
, OMAP_TIMER_POSTED
, clkev
.rate
);
112 case CLOCK_EVT_MODE_PERIODIC
:
113 period
= clkev
.rate
/ HZ
;
115 /* Looks like we need to first set the load value separately */
116 __omap_dm_timer_write(&clkev
, OMAP_TIMER_LOAD_REG
,
117 0xffffffff - period
, OMAP_TIMER_POSTED
);
118 __omap_dm_timer_load_start(&clkev
,
119 OMAP_TIMER_CTRL_AR
| OMAP_TIMER_CTRL_ST
,
120 0xffffffff - period
, OMAP_TIMER_POSTED
);
122 case CLOCK_EVT_MODE_ONESHOT
:
124 case CLOCK_EVT_MODE_UNUSED
:
125 case CLOCK_EVT_MODE_SHUTDOWN
:
126 case CLOCK_EVT_MODE_RESUME
:
131 static struct clock_event_device clockevent_gpt
= {
132 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
134 .set_next_event
= omap2_gp_timer_set_next_event
,
135 .set_mode
= omap2_gp_timer_set_mode
,
138 static struct property device_disabled
= {
140 .length
= sizeof("disabled"),
144 static struct of_device_id omap_timer_match
[] __initdata
= {
145 { .compatible
= "ti,omap2420-timer", },
146 { .compatible
= "ti,omap3430-timer", },
147 { .compatible
= "ti,omap4430-timer", },
148 { .compatible
= "ti,omap5430-timer", },
149 { .compatible
= "ti,am335x-timer", },
150 { .compatible
= "ti,am335x-timer-1ms", },
155 * omap_get_timer_dt - get a timer using device-tree
156 * @match - device-tree match structure for matching a device type
157 * @property - optional timer property to match
159 * Helper function to get a timer during early boot using device-tree for use
160 * as kernel system timer. Optionally, the property argument can be used to
161 * select a timer with a specific property. Once a timer is found then mark
162 * the timer node in device-tree as disabled, to prevent the kernel from
163 * registering this timer as a platform device and so no one else can use it.
165 static struct device_node
* __init
omap_get_timer_dt(struct of_device_id
*match
,
166 const char *property
)
168 struct device_node
*np
;
170 for_each_matching_node(np
, match
) {
171 if (!of_device_is_available(np
))
174 if (property
&& !of_get_property(np
, property
, NULL
))
177 if (!property
&& (of_get_property(np
, "ti,timer-alwon", NULL
) ||
178 of_get_property(np
, "ti,timer-dsp", NULL
) ||
179 of_get_property(np
, "ti,timer-pwm", NULL
) ||
180 of_get_property(np
, "ti,timer-secure", NULL
)))
183 of_add_property(np
, &device_disabled
);
191 * omap_dmtimer_init - initialisation function when device tree is used
193 * For secure OMAP3 devices, timers with device type "timer-secure" cannot
194 * be used by the kernel as they are reserved. Therefore, to prevent the
195 * kernel registering these devices remove them dynamically from the device
198 static void __init
omap_dmtimer_init(void)
200 struct device_node
*np
;
202 if (!cpu_is_omap34xx())
205 /* If we are a secure device, remove any secure timer nodes */
206 if ((omap_type() != OMAP2_DEVICE_TYPE_GP
)) {
207 np
= omap_get_timer_dt(omap_timer_match
, "ti,timer-secure");
214 * omap_dm_timer_get_errata - get errata flags for a timer
216 * Get the timer errata flags that are specific to the OMAP device being used.
218 static u32 __init
omap_dm_timer_get_errata(void)
220 if (cpu_is_omap24xx())
223 return OMAP_TIMER_ERRATA_I103_I767
;
226 static int __init
omap_dm_timer_init_one(struct omap_dm_timer
*timer
,
227 const char *fck_source
,
228 const char *property
,
229 const char **timer_name
,
232 char name
[10]; /* 10 = sizeof("gptXX_Xck0") */
233 const char *oh_name
= NULL
;
234 struct device_node
*np
;
235 struct omap_hwmod
*oh
;
236 struct resource irq
, mem
;
240 if (of_have_populated_dt()) {
241 np
= omap_get_timer_dt(omap_timer_match
, property
);
245 of_property_read_string_index(np
, "ti,hwmods", 0, &oh_name
);
249 timer
->irq
= irq_of_parse_and_map(np
, 0);
253 timer
->io_base
= of_iomap(np
, 0);
257 if (omap_dm_timer_reserve_systimer(timer
->id
))
260 sprintf(name
, "timer%d", timer
->id
);
264 oh
= omap_hwmod_lookup(oh_name
);
268 *timer_name
= oh
->name
;
270 if (!of_have_populated_dt()) {
271 r
= omap_hwmod_get_resource_byname(oh
, IORESOURCE_IRQ
, NULL
,
275 timer
->irq
= irq
.start
;
277 r
= omap_hwmod_get_resource_byname(oh
, IORESOURCE_MEM
, NULL
,
282 /* Static mapping, never released */
283 timer
->io_base
= ioremap(mem
.start
, mem
.end
- mem
.start
);
289 /* After the dmtimer is using hwmod these clocks won't be needed */
290 timer
->fclk
= clk_get(NULL
, omap_hwmod_get_main_clk(oh
));
291 if (IS_ERR(timer
->fclk
))
292 return PTR_ERR(timer
->fclk
);
294 src
= clk_get(NULL
, fck_source
);
298 if (clk_get_parent(timer
->fclk
) != src
) {
299 r
= clk_set_parent(timer
->fclk
, src
);
301 pr_warn("%s: %s cannot set source\n", __func__
,
310 omap_hwmod_setup_one(oh_name
);
311 omap_hwmod_enable(oh
);
312 __omap_dm_timer_init_regs(timer
);
315 __omap_dm_timer_enable_posted(timer
);
317 /* Check that the intended posted configuration matches the actual */
318 if (posted
!= timer
->posted
)
321 timer
->rate
= clk_get_rate(timer
->fclk
);
327 static void __init
omap2_gp_clockevent_init(int gptimer_id
,
328 const char *fck_source
,
329 const char *property
)
333 clkev
.id
= gptimer_id
;
334 clkev
.errata
= omap_dm_timer_get_errata();
337 * For clock-event timers we never read the timer counter and
338 * so we are not impacted by errata i103 and i767. Therefore,
339 * we can safely ignore this errata for clock-event timers.
341 __omap_dm_timer_override_errata(&clkev
, OMAP_TIMER_ERRATA_I103_I767
);
343 res
= omap_dm_timer_init_one(&clkev
, fck_source
, property
,
344 &clockevent_gpt
.name
, OMAP_TIMER_POSTED
);
347 omap2_gp_timer_irq
.dev_id
= &clkev
;
348 setup_irq(clkev
.irq
, &omap2_gp_timer_irq
);
350 __omap_dm_timer_int_enable(&clkev
, OMAP_TIMER_INT_OVERFLOW
);
352 clockevent_gpt
.cpumask
= cpu_possible_mask
;
353 clockevent_gpt
.irq
= omap_dm_timer_get_irq(&clkev
);
354 clockevents_config_and_register(&clockevent_gpt
, clkev
.rate
,
355 3, /* Timer internal resynch latency */
358 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt
.name
,
362 /* Clocksource code */
363 static struct omap_dm_timer clksrc
;
364 static bool use_gptimer_clksrc
;
369 static cycle_t
clocksource_read_cycles(struct clocksource
*cs
)
371 return (cycle_t
)__omap_dm_timer_read_counter(&clksrc
,
372 OMAP_TIMER_NONPOSTED
);
375 static struct clocksource clocksource_gpt
= {
377 .read
= clocksource_read_cycles
,
378 .mask
= CLOCKSOURCE_MASK(32),
379 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
382 static u64 notrace
dmtimer_read_sched_clock(void)
385 return __omap_dm_timer_read_counter(&clksrc
,
386 OMAP_TIMER_NONPOSTED
);
391 static struct of_device_id omap_counter_match
[] __initdata
= {
392 { .compatible
= "ti,omap-counter32k", },
396 /* Setup free-running counter for clocksource */
397 static int __init __maybe_unused
omap2_sync32k_clocksource_init(void)
400 struct device_node
*np
= NULL
;
401 struct omap_hwmod
*oh
;
403 const char *oh_name
= "counter_32k";
406 * If device-tree is present, then search the DT blob
407 * to see if the 32kHz counter is supported.
409 if (of_have_populated_dt()) {
410 np
= omap_get_timer_dt(omap_counter_match
, NULL
);
414 of_property_read_string_index(np
, "ti,hwmods", 0, &oh_name
);
420 * First check hwmod data is available for sync32k counter
422 oh
= omap_hwmod_lookup(oh_name
);
423 if (!oh
|| oh
->slaves_cnt
== 0)
426 omap_hwmod_setup_one(oh_name
);
429 vbase
= of_iomap(np
, 0);
432 vbase
= omap_hwmod_get_mpu_rt_va(oh
);
436 pr_warn("%s: failed to get counter_32k resource\n", __func__
);
440 ret
= omap_hwmod_enable(oh
);
442 pr_warn("%s: failed to enable counter_32k module (%d)\n",
447 ret
= omap_init_clocksource_32k(vbase
);
449 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
457 static void __init
omap2_gptimer_clocksource_init(int gptimer_id
,
458 const char *fck_source
,
459 const char *property
)
463 clksrc
.id
= gptimer_id
;
464 clksrc
.errata
= omap_dm_timer_get_errata();
466 res
= omap_dm_timer_init_one(&clksrc
, fck_source
, property
,
467 &clocksource_gpt
.name
,
468 OMAP_TIMER_NONPOSTED
);
471 __omap_dm_timer_load_start(&clksrc
,
472 OMAP_TIMER_CTRL_ST
| OMAP_TIMER_CTRL_AR
, 0,
473 OMAP_TIMER_NONPOSTED
);
474 sched_clock_register(dmtimer_read_sched_clock
, 32, clksrc
.rate
);
476 if (clocksource_register_hz(&clocksource_gpt
, clksrc
.rate
))
477 pr_err("Could not register clocksource %s\n",
478 clocksource_gpt
.name
);
480 pr_info("OMAP clocksource: %s at %lu Hz\n",
481 clocksource_gpt
.name
, clksrc
.rate
);
484 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
486 * The realtime counter also called master counter, is a free-running
487 * counter, which is related to real time. It produces the count used
488 * by the CPU local timer peripherals in the MPU cluster. The timer counts
489 * at a rate of 6.144 MHz. Because the device operates on different clocks
490 * in different power modes, the master counter shifts operation between
491 * clocks, adjusting the increment per clock in hardware accordingly to
492 * maintain a constant count rate.
494 static void __init
realtime_counter_init(void)
497 static struct clk
*sys_clk
;
499 unsigned int reg
, num
, den
;
501 base
= ioremap(REALTIME_COUNTER_BASE
, SZ_32
);
503 pr_err("%s: ioremap failed\n", __func__
);
506 sys_clk
= clk_get(NULL
, "sys_clkin");
507 if (IS_ERR(sys_clk
)) {
508 pr_err("%s: failed to get system clock handle\n", __func__
);
513 rate
= clk_get_rate(sys_clk
);
514 /* Numerator/denumerator values refer TRM Realtime Counter section */
542 /* Program it for 38.4 MHz */
548 /* Program numerator and denumerator registers */
549 reg
= __raw_readl(base
+ INCREMENTER_NUMERATOR_OFFSET
) &
550 NUMERATOR_DENUMERATOR_MASK
;
552 __raw_writel(reg
, base
+ INCREMENTER_NUMERATOR_OFFSET
);
554 reg
= __raw_readl(base
+ INCREMENTER_DENUMERATOR_RELOAD_OFFSET
) &
555 NUMERATOR_DENUMERATOR_MASK
;
557 __raw_writel(reg
, base
+ INCREMENTER_DENUMERATOR_RELOAD_OFFSET
);
559 arch_timer_freq
= (rate
/ den
) * num
;
565 static inline void __init
realtime_counter_init(void)
569 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
570 clksrc_nr, clksrc_src, clksrc_prop) \
571 void __init omap##name##_gptimer_timer_init(void) \
574 omap_dmtimer_init(); \
575 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
576 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
580 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
581 clksrc_nr, clksrc_src, clksrc_prop) \
582 void __init omap##name##_sync32k_timer_init(void) \
585 omap_dmtimer_init(); \
586 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
587 /* Enable the use of clocksource="gp_timer" kernel parameter */ \
588 if (use_gptimer_clksrc) \
589 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
592 omap2_sync32k_clocksource_init(); \
595 #ifdef CONFIG_ARCH_OMAP2
596 OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
597 2, "timer_sys_ck", NULL
);
598 #endif /* CONFIG_ARCH_OMAP2 */
600 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
601 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
602 2, "timer_sys_ck", NULL
);
603 OMAP_SYS_32K_TIMER_INIT(3_secure
, 12, "secure_32k_fck", "ti,timer-secure",
604 2, "timer_sys_ck", NULL
);
605 #endif /* CONFIG_ARCH_OMAP3 */
607 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
608 OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL
,
609 1, "timer_sys_ck", "ti,timer-alwon");
612 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
613 defined(CONFIG_SOC_DRA7XX)
614 static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
615 2, "sys_clkin_ck", NULL
);
618 #ifdef CONFIG_ARCH_OMAP4
619 #ifdef CONFIG_HAVE_ARM_TWD
620 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer
, OMAP44XX_LOCAL_TWD_BASE
, 29);
621 void __init
omap4_local_timer_init(void)
623 omap4_sync32k_timer_init();
624 /* Local timers are not supprted on OMAP4430 ES1.0 */
625 if (omap_rev() != OMAP4430_REV_ES1_0
) {
628 if (of_have_populated_dt()) {
629 clocksource_of_init();
633 err
= twd_local_timer_register(&twd_local_timer
);
635 pr_err("twd_local_timer_register failed %d\n", err
);
639 void __init
omap4_local_timer_init(void)
641 omap4_sync32k_timer_init();
643 #endif /* CONFIG_HAVE_ARM_TWD */
644 #endif /* CONFIG_ARCH_OMAP4 */
646 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
647 void __init
omap5_realtime_timer_init(void)
649 omap4_sync32k_timer_init();
650 realtime_counter_init();
652 clocksource_of_init();
654 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
657 * omap_timer_init - build and register timer device with an
658 * associated timer hwmod
659 * @oh: timer hwmod pointer to be used to build timer device
660 * @user: parameter that can be passed from calling hwmod API
662 * Called by omap_hwmod_for_each_by_class to register each of the timer
663 * devices present in the system. The number of timer devices is known
664 * by parsing through the hwmod database for a given class name. At the
665 * end of function call memory is allocated for timer device and it is
666 * registered to the framework ready to be proved by the driver.
668 static int __init
omap_timer_init(struct omap_hwmod
*oh
, void *unused
)
672 char *name
= "omap_timer";
673 struct dmtimer_platform_data
*pdata
;
674 struct platform_device
*pdev
;
675 struct omap_timer_capability_dev_attr
*timer_dev_attr
;
677 pr_debug("%s: %s\n", __func__
, oh
->name
);
679 /* on secure device, do not register secure timer */
680 timer_dev_attr
= oh
->dev_attr
;
681 if (omap_type() != OMAP2_DEVICE_TYPE_GP
&& timer_dev_attr
)
682 if (timer_dev_attr
->timer_capability
== OMAP_TIMER_SECURE
)
685 pdata
= kzalloc(sizeof(*pdata
), GFP_KERNEL
);
687 pr_err("%s: No memory for [%s]\n", __func__
, oh
->name
);
692 * Extract the IDs from name field in hwmod database
693 * and use the same for constructing ids' for the
694 * timer devices. In a way, we are avoiding usage of
695 * static variable witin the function to do the same.
696 * CAUTION: We have to be careful and make sure the
697 * name in hwmod database does not change in which case
698 * we might either make corresponding change here or
699 * switch back static variable mechanism.
701 sscanf(oh
->name
, "timer%2d", &id
);
704 pdata
->timer_capability
= timer_dev_attr
->timer_capability
;
706 pdata
->timer_errata
= omap_dm_timer_get_errata();
707 pdata
->get_context_loss_count
= omap_pm_get_dev_context_loss_count
;
709 pdev
= omap_device_build(name
, id
, oh
, pdata
, sizeof(*pdata
));
712 pr_err("%s: Can't build omap_device for %s: %s.\n",
713 __func__
, name
, oh
->name
);
723 * omap2_dm_timer_init - top level regular device initialization
725 * Uses dedicated hwmod api to parse through hwmod database for
726 * given class name and then build and register the timer device.
728 static int __init
omap2_dm_timer_init(void)
732 /* If dtb is there, the devices will be created dynamically */
733 if (of_have_populated_dt())
736 ret
= omap_hwmod_for_each_by_class("timer", omap_timer_init
, NULL
);
738 pr_err("%s: device registration failed.\n", __func__
);
744 omap_arch_initcall(omap2_dm_timer_init
);
747 * omap2_override_clocksource - clocksource override with user configuration
749 * Allows user to override default clocksource, using kernel parameter
750 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
752 * Note that, here we are using same standard kernel parameter "clocksource=",
753 * and not introducing any OMAP specific interface.
755 static int __init
omap2_override_clocksource(char *str
)
760 * For OMAP architecture, we only have two options
761 * - sync_32k (default)
762 * - gp_timer (sys_clk based)
764 if (!strcmp(str
, "gp_timer"))
765 use_gptimer_clksrc
= true;
769 early_param("clocksource", omap2_override_clocksource
);