arch/arm/mach-s3c64xx/pm.c

   1 /* linux/arch/arm/plat-s3c64xx/pm.c
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C64XX CPU PM support.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/init.h>
  16 #include <linux/suspend.h>
  17 #include <linux/serial_core.h>
  18 #include <linux/io.h>
  19 #include <linux/gpio.h>
  20 #include <linux/pm_domain.h>
  21
  22 #include <mach/map.h>
  23 #include <mach/irqs.h>
  24
  25 #include <plat/devs.h>
  26 #include <plat/pm.h>
  27 #include <plat/wakeup-mask.h>
  28
  29 #include <mach/regs-gpio.h>
  30 #include <mach/regs-clock.h>
  31 #include <mach/gpio-samsung.h>
  32
  33 #include "regs-gpio-memport.h"
  34 #include "regs-modem.h"
  35 #include "regs-sys.h"
  36 #include "regs-syscon-power.h"
  37
  38 struct s3c64xx_pm_domain {
  39         char *const name;
  40         u32 ena;
  41         u32 pwr_stat;
  42         struct generic_pm_domain pd;
  43 };
  44
  45 static int s3c64xx_pd_off(struct generic_pm_domain *domain)
  46 {
  47         struct s3c64xx_pm_domain *pd;
  48         u32 val;
  49
  50         pd = container_of(domain, struct s3c64xx_pm_domain, pd);
  51
  52         val = __raw_readl(S3C64XX_NORMAL_CFG);
  53         val &= ~(pd->ena);
  54         __raw_writel(val, S3C64XX_NORMAL_CFG);
  55
  56         return 0;
  57 }
  58
  59 static int s3c64xx_pd_on(struct generic_pm_domain *domain)
  60 {
  61         struct s3c64xx_pm_domain *pd;
  62         u32 val;
  63         long retry = 1000000L;
  64
  65         pd = container_of(domain, struct s3c64xx_pm_domain, pd);
  66
  67         val = __raw_readl(S3C64XX_NORMAL_CFG);
  68         val |= pd->ena;
  69         __raw_writel(val, S3C64XX_NORMAL_CFG);
  70
  71         /* Not all domains provide power status readback */
  72         if (pd->pwr_stat) {
  73                 do {
  74                         cpu_relax();
  75                         if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
  76                                 break;
  77                 } while (retry--);
  78
  79                 if (!retry) {
  80                         pr_err("Failed to start domain %s\n", pd->name);
  81                         return -EBUSY;
  82                 }
  83         }
  84
  85         return 0;
  86 }
  87
  88 static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
  89         .name = "IROM",
  90         .ena = S3C64XX_NORMALCFG_IROM_ON,
  91         .pd = {
  92                 .power_off = s3c64xx_pd_off,
  93                 .power_on = s3c64xx_pd_on,
  94         },
  95 };
  96
  97 static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
  98         .name = "ETM",
  99         .ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
 100         .pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
 101         .pd = {
 102                 .power_off = s3c64xx_pd_off,
 103                 .power_on = s3c64xx_pd_on,
 104         },
 105 };
 106
 107 static struct s3c64xx_pm_domain s3c64xx_pm_s = {
 108         .name = "S",
 109         .ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
 110         .pwr_stat = S3C64XX_BLKPWRSTAT_S,
 111         .pd = {
 112                 .power_off = s3c64xx_pd_off,
 113                 .power_on = s3c64xx_pd_on,
 114         },
 115 };
 116
 117 static struct s3c64xx_pm_domain s3c64xx_pm_f = {
 118         .name = "F",
 119         .ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
 120         .pwr_stat = S3C64XX_BLKPWRSTAT_F,
 121         .pd = {
 122                 .power_off = s3c64xx_pd_off,
 123                 .power_on = s3c64xx_pd_on,
 124         },
 125 };
 126
 127 static struct s3c64xx_pm_domain s3c64xx_pm_p = {
 128         .name = "P",
 129         .ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
 130         .pwr_stat = S3C64XX_BLKPWRSTAT_P,
 131         .pd = {
 132                 .power_off = s3c64xx_pd_off,
 133                 .power_on = s3c64xx_pd_on,
 134         },
 135 };
 136
 137 static struct s3c64xx_pm_domain s3c64xx_pm_i = {
 138         .name = "I",
 139         .ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
 140         .pwr_stat = S3C64XX_BLKPWRSTAT_I,
 141         .pd = {
 142                 .power_off = s3c64xx_pd_off,
 143                 .power_on = s3c64xx_pd_on,
 144         },
 145 };
 146
 147 static struct s3c64xx_pm_domain s3c64xx_pm_g = {
 148         .name = "G",
 149         .ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
 150         .pd = {
 151                 .power_off = s3c64xx_pd_off,
 152                 .power_on = s3c64xx_pd_on,
 153         },
 154 };
 155
 156 static struct s3c64xx_pm_domain s3c64xx_pm_v = {
 157         .name = "V",
 158         .ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
 159         .pwr_stat = S3C64XX_BLKPWRSTAT_V,
 160         .pd = {
 161                 .power_off = s3c64xx_pd_off,
 162                 .power_on = s3c64xx_pd_on,
 163         },
 164 };
 165
 166 static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
 167         &s3c64xx_pm_irom,
 168 };
 169
 170 static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
 171         &s3c64xx_pm_etm,
 172         &s3c64xx_pm_g,
 173         &s3c64xx_pm_v,
 174         &s3c64xx_pm_i,
 175         &s3c64xx_pm_p,
 176         &s3c64xx_pm_s,
 177         &s3c64xx_pm_f,
 178 };
 179
 180 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
 181 void s3c_pm_debug_smdkled(u32 set, u32 clear)
 182 {
 183         unsigned long flags;
 184         int i;
 185
 186         local_irq_save(flags);
 187         for (i = 0; i < 4; i++) {
 188                 if (clear & (1 << i))
 189                         gpio_set_value(S3C64XX_GPN(12 + i), 0);
 190                 if (set & (1 << i))
 191                         gpio_set_value(S3C64XX_GPN(12 + i), 1);
 192         }
 193         local_irq_restore(flags);
 194 }
 195 #endif
 196
 197 static struct sleep_save core_save[] = {
 198         SAVE_ITEM(S3C64XX_MEM0DRVCON),
 199         SAVE_ITEM(S3C64XX_MEM1DRVCON),
 200 };
 201
 202 static struct sleep_save misc_save[] = {
 203         SAVE_ITEM(S3C64XX_AHB_CON0),
 204         SAVE_ITEM(S3C64XX_AHB_CON1),
 205         SAVE_ITEM(S3C64XX_AHB_CON2),
 206
 207         SAVE_ITEM(S3C64XX_SPCON),
 208
 209         SAVE_ITEM(S3C64XX_MEM0CONSTOP),
 210         SAVE_ITEM(S3C64XX_MEM1CONSTOP),
 211         SAVE_ITEM(S3C64XX_MEM0CONSLP0),
 212         SAVE_ITEM(S3C64XX_MEM0CONSLP1),
 213         SAVE_ITEM(S3C64XX_MEM1CONSLP),
 214
 215         SAVE_ITEM(S3C64XX_SDMA_SEL),
 216         SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
 217
 218         SAVE_ITEM(S3C64XX_NORMAL_CFG),
 219 };
 220
 221 void s3c_pm_configure_extint(void)
 222 {
 223         __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
 224 }
 225
 226 void s3c_pm_restore_core(void)
 227 {
 228         __raw_writel(0, S3C64XX_EINT_MASK);
 229
 230         s3c_pm_debug_smdkled(1 << 2, 0);
 231
 232         s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
 233         s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
 234 }
 235
 236 void s3c_pm_save_core(void)
 237 {
 238         s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
 239         s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
 240 }
 241
 242 /* since both s3c6400 and s3c6410 share the same sleep pm calls, we
 243  * put the per-cpu code in here until any new cpu comes along and changes
 244  * this.
 245  */
 246
 247 static int s3c64xx_cpu_suspend(unsigned long arg)
 248 {
 249         unsigned long tmp;
 250
 251         /* set our standby method to sleep */
 252
 253         tmp = __raw_readl(S3C64XX_PWR_CFG);
 254         tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
 255         tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
 256         __raw_writel(tmp, S3C64XX_PWR_CFG);
 257
 258         /* clear any old wakeup */
 259
 260         __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
 261                      S3C64XX_WAKEUP_STAT);
 262
 263         /* set the LED state to 0110 over sleep */
 264         s3c_pm_debug_smdkled(3 << 1, 0xf);
 265
 266         /* issue the standby signal into the pm unit. Note, we
 267          * issue a write-buffer drain just in case */
 268
 269         tmp = 0;
 270
 271         asm("b 1f\n\t"
 272             ".align 5\n\t"
 273             "1:\n\t"
 274             "mcr p15, 0, %0, c7, c10, 5\n\t"
 275             "mcr p15, 0, %0, c7, c10, 4\n\t"
 276             "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
 277
 278         /* we should never get past here */
 279
 280         pr_info("Failed to suspend the system\n");
 281         return 1; /* Aborting suspend */
 282 }
 283
 284 /* mapping of interrupts to parts of the wakeup mask */
 285 static struct samsung_wakeup_mask wake_irqs[] = {
 286         { .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
 287         { .irq = IRQ_RTC_TIC,   .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
 288         { .irq = IRQ_PENDN,     .bit = S3C64XX_PWRCFG_TS_DISABLE, },
 289         { .irq = IRQ_HSMMC0,    .bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
 290         { .irq = IRQ_HSMMC1,    .bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
 291         { .irq = IRQ_HSMMC2,    .bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
 292         { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE},
 293         { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
 294         { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE },
 295         { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
 296 };
 297
 298 static void s3c64xx_pm_prepare(void)
 299 {
 300         samsung_sync_wakemask(S3C64XX_PWR_CFG,
 301                               wake_irqs, ARRAY_SIZE(wake_irqs));
 302
 303         /* store address of resume. */
 304         __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
 305
 306         /* ensure previous wakeup state is cleared before sleeping */
 307         __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
 308 }
 309
 310 int __init s3c64xx_pm_init(void)
 311 {
 312         int i;
 313
 314         s3c_pm_init();
 315
 316         for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
 317                 pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
 318                               &pm_domain_always_on_gov, false);
 319
 320         for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
 321                 pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
 322
 323 #ifdef CONFIG_S3C_DEV_FB
 324         if (dev_get_platdata(&s3c_device_fb.dev))
 325                 pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
 326 #endif
 327
 328         return 0;
 329 }
 330
 331 static __init int s3c64xx_pm_initcall(void)
 332 {
 333         pm_cpu_prep = s3c64xx_pm_prepare;
 334         pm_cpu_sleep = s3c64xx_cpu_suspend;
 335         pm_uart_udivslot = 1;
 336
 337 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
 338         gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
 339         gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
 340         gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
 341         gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
 342         gpio_direction_output(S3C64XX_GPN(12), 0);
 343         gpio_direction_output(S3C64XX_GPN(13), 0);
 344         gpio_direction_output(S3C64XX_GPN(14), 0);
 345         gpio_direction_output(S3C64XX_GPN(15), 0);
 346 #endif
 347
 348         return 0;
 349 }
 350 arch_initcall(s3c64xx_pm_initcall);
 351
 352 int __init s3c64xx_pm_late_initcall(void)
 353 {
 354         pm_genpd_poweroff_unused();
 355
 356         return 0;
 357 }