arch/arm/mach-shmobile/clock-r7s72100.c

   1 /*
   2  * r7a72100 clock framework support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2012  Phil Edworthy
   6  * Copyright (C) 2011  Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #include <linux/init.h>
  18 #include <linux/kernel.h>
  19 #include <linux/io.h>
  20 #include <linux/sh_clk.h>
  21 #include <linux/clkdev.h>
  22 #include <mach/common.h>
  23 #include <mach/r7s72100.h>
  24
  25 /* registers */
  26 #define FRQCR           0xfcfe0010
  27 #define FRQCR2          0xfcfe0014
  28 #define STBCR3          0xfcfe0420
  29 #define STBCR4          0xfcfe0424
  30 #define STBCR9          0xfcfe0438
  31
  32 #define PLL_RATE 30
  33
  34 static struct clk_mapping cpg_mapping = {
  35         .phys   = 0xfcfe0000,
  36         .len    = 0x1000,
  37 };
  38
  39 /* Fixed 32 KHz root clock for RTC */
  40 static struct clk r_clk = {
  41         .rate           = 32768,
  42 };
  43
  44 /*
  45  * Default rate for the root input clock, reset this with clk_set_rate()
  46  * from the platform code.
  47  */
  48 static struct clk extal_clk = {
  49         .rate           = 13330000,
  50         .mapping        = &cpg_mapping,
  51 };
  52
  53 static unsigned long pll_recalc(struct clk *clk)
  54 {
  55         return clk->parent->rate * PLL_RATE;
  56 }
  57
  58 static struct sh_clk_ops pll_clk_ops = {
  59         .recalc         = pll_recalc,
  60 };
  61
  62 static struct clk pll_clk = {
  63         .ops            = &pll_clk_ops,
  64         .parent         = &extal_clk,
  65         .flags          = CLK_ENABLE_ON_INIT,
  66 };
  67
  68 static unsigned long bus_recalc(struct clk *clk)
  69 {
  70         return clk->parent->rate * 2 / 3;
  71 }
  72
  73 static struct sh_clk_ops bus_clk_ops = {
  74         .recalc         = bus_recalc,
  75 };
  76
  77 static struct clk bus_clk = {
  78         .ops            = &bus_clk_ops,
  79         .parent         = &pll_clk,
  80         .flags          = CLK_ENABLE_ON_INIT,
  81 };
  82
  83 static unsigned long peripheral0_recalc(struct clk *clk)
  84 {
  85         return clk->parent->rate / 12;
  86 }
  87
  88 static struct sh_clk_ops peripheral0_clk_ops = {
  89         .recalc         = peripheral0_recalc,
  90 };
  91
  92 static struct clk peripheral0_clk = {
  93         .ops            = &peripheral0_clk_ops,
  94         .parent         = &pll_clk,
  95         .flags          = CLK_ENABLE_ON_INIT,
  96 };
  97
  98 static unsigned long peripheral1_recalc(struct clk *clk)
  99 {
 100         return clk->parent->rate / 6;
 101 }
 102
 103 static struct sh_clk_ops peripheral1_clk_ops = {
 104         .recalc         = peripheral1_recalc,
 105 };
 106
 107 static struct clk peripheral1_clk = {
 108         .ops            = &peripheral1_clk_ops,
 109         .parent         = &pll_clk,
 110         .flags          = CLK_ENABLE_ON_INIT,
 111 };
 112
 113 struct clk *main_clks[] = {
 114         &r_clk,
 115         &extal_clk,
 116         &pll_clk,
 117         &bus_clk,
 118         &peripheral0_clk,
 119         &peripheral1_clk,
 120 };
 121
 122 static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
 123 static int multipliers[] = { 1, 2, 1, 1 };
 124
 125 static struct clk_div_mult_table div4_div_mult_table = {
 126         .divisors = div2,
 127         .nr_divisors = ARRAY_SIZE(div2),
 128         .multipliers = multipliers,
 129         .nr_multipliers = ARRAY_SIZE(multipliers),
 130 };
 131
 132 static struct clk_div4_table div4_table = {
 133         .div_mult_table = &div4_div_mult_table,
 134 };
 135
 136 enum { DIV4_I,
 137         DIV4_NR };
 138
 139 #define DIV4(_reg, _bit, _mask, _flags) \
 140         SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 141
 142 /* The mask field specifies the div2 entries that are valid */
 143 struct clk div4_clks[DIV4_NR] = {
 144         [DIV4_I]  = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
 145                                         | CLK_ENABLE_ON_INIT),
 146 };
 147
 148 enum {  MSTP97, MSTP96, MSTP95, MSTP94,
 149         MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
 150         MSTP33, MSTP_NR };
 151
 152 static struct clk mstp_clks[MSTP_NR] = {
 153         [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
 154         [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
 155         [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
 156         [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
 157         [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
 158         [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
 159         [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
 160         [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
 161         [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
 162         [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
 163         [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
 164         [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
 165         [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
 166 };
 167
 168 static struct clk_lookup lookups[] = {
 169         /* main clocks */
 170         CLKDEV_CON_ID("rclk", &r_clk),
 171         CLKDEV_CON_ID("extal", &extal_clk),
 172         CLKDEV_CON_ID("pll_clk", &pll_clk),
 173         CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
 174
 175         /* DIV4 clocks */
 176         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 177
 178         /* MSTP clocks */
 179         CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
 180
 181         /* ICK */
 182         CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
 183         CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
 184         CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
 185         CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
 186         CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
 187         CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
 188         CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
 189         CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
 190 };
 191
 192 void __init r7s72100_clock_init(void)
 193 {
 194         int k, ret = 0;
 195
 196         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 197                 ret = clk_register(main_clks[k]);
 198
 199         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 200
 201         if (!ret)
 202                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 203
 204         if (!ret)
 205                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 206
 207         if (!ret)
 208                 shmobile_clk_init();
 209         else
 210                 panic("failed to setup rza1 clocks\n");
 211 }