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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / arch / arm / mach-shmobile / setup-r8a7778.c
blob6d694526e4ca1b09be05a64cd163c4f83540e4df
1 /*
2 * r8a7778 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * Copyright (C) 2013 Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/irqchip/arm-gic.h>
25 #include <linux/of.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_data/dma-rcar-hpbdma.h>
28 #include <linux/platform_data/gpio-rcar.h>
29 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
30 #include <linux/platform_device.h>
31 #include <linux/irqchip.h>
32 #include <linux/serial_sci.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/usb/phy.h>
36 #include <linux/usb/hcd.h>
37 #include <linux/usb/ehci_pdriver.h>
38 #include <linux/usb/ohci_pdriver.h>
39 #include <linux/dma-mapping.h>
40 #include <mach/irqs.h>
41 #include <mach/r8a7778.h>
42 #include <mach/common.h>
43 #include <asm/mach/arch.h>
44 #include <asm/hardware/cache-l2x0.h>
45
46 /* SCIF */
47 #define R8A7778_SCIF(index, baseaddr, irq) \
48 static struct plat_sci_port scif##index##_platform_data = { \
49 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
50 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
51 .type = PORT_SCIF, \
52 }; \
53 \
54 static struct resource scif##index##_resources[] = { \
55 DEFINE_RES_MEM(baseaddr, 0x100), \
56 DEFINE_RES_IRQ(irq), \
57 }
58
59 R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
60 R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
61 R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
62 R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
63 R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
64 R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
65
66 #define r8a7778_register_scif(index) \
67 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
68 scif##index##_resources, \
69 ARRAY_SIZE(scif##index##_resources), \
70 &scif##index##_platform_data, \
71 sizeof(scif##index##_platform_data))
72
73 /* TMU */
74 static struct resource sh_tmu0_resources[] __initdata = {
75 DEFINE_RES_MEM(0xffd80008, 12),
76 DEFINE_RES_IRQ(gic_iid(0x40)),
77 };
78
79 static struct sh_timer_config sh_tmu0_platform_data __initdata = {
80 .name = "TMU00",
81 .channel_offset = 0x4,
82 .timer_bit = 0,
83 .clockevent_rating = 200,
84 };
85
86 static struct resource sh_tmu1_resources[] __initdata = {
87 DEFINE_RES_MEM(0xffd80014, 12),
88 DEFINE_RES_IRQ(gic_iid(0x41)),
89 };
90
91 static struct sh_timer_config sh_tmu1_platform_data __initdata = {
92 .name = "TMU01",
93 .channel_offset = 0x10,
94 .timer_bit = 1,
95 .clocksource_rating = 200,
96 };
97
98 #define r8a7778_register_tmu(idx) \
99 platform_device_register_resndata( \
100 &platform_bus, "sh_tmu", idx, \
101 sh_tmu##idx##_resources, \
102 ARRAY_SIZE(sh_tmu##idx##_resources), \
103 &sh_tmu##idx##_platform_data, \
104 sizeof(sh_tmu##idx##_platform_data))
105
106 int r8a7778_usb_phy_power(bool enable)
107 {
108 static struct usb_phy *phy = NULL;
109 int ret = 0;
110
111 if (!phy)
112 phy = usb_get_phy(USB_PHY_TYPE_USB2);
113
114 if (IS_ERR(phy)) {
115 pr_err("kernel doesn't have usb phy driver\n");
116 return PTR_ERR(phy);
117 }
118
119 if (enable)
120 ret = usb_phy_init(phy);
121 else
122 usb_phy_shutdown(phy);
123
124 return ret;
125 }
126
127 /* USB */
128 static int usb_power_on(struct platform_device *pdev)
129 {
130 int ret = r8a7778_usb_phy_power(true);
131
132 if (ret)
133 return ret;
134
135 pm_runtime_enable(&pdev->dev);
136 pm_runtime_get_sync(&pdev->dev);
137
138 return 0;
139 }
140
141 static void usb_power_off(struct platform_device *pdev)
142 {
143 if (r8a7778_usb_phy_power(false))
144 return;
145
146 pm_runtime_put_sync(&pdev->dev);
147 pm_runtime_disable(&pdev->dev);
148 }
149
150 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
151 {
152 /*
153 * Below are recommended values from the datasheet;
154 * see [USB :: Setting of EHCI Internal Buffer].
155 */
156 /* EHCI IP internal buffer setting */
157 iowrite32(0x00ff0040, hcd->regs + 0x0094);
158 /* EHCI IP internal buffer enable */
159 iowrite32(0x00000001, hcd->regs + 0x009C);
160
161 return 0;
162 }
163
164 static struct usb_ehci_pdata ehci_pdata __initdata = {
165 .power_on = usb_power_on,
166 .power_off = usb_power_off,
167 .power_suspend = usb_power_off,
168 .pre_setup = ehci_init_internal_buffer,
169 };
170
171 static struct resource ehci_resources[] __initdata = {
172 DEFINE_RES_MEM(0xffe70000, 0x400),
173 DEFINE_RES_IRQ(gic_iid(0x4c)),
174 };
175
176 static struct usb_ohci_pdata ohci_pdata __initdata = {
177 .power_on = usb_power_on,
178 .power_off = usb_power_off,
179 .power_suspend = usb_power_off,
180 };
181
182 static struct resource ohci_resources[] __initdata = {
183 DEFINE_RES_MEM(0xffe70400, 0x400),
184 DEFINE_RES_IRQ(gic_iid(0x4c)),
185 };
186
187 #define USB_PLATFORM_INFO(hci) \
188 static struct platform_device_info hci##_info __initdata = { \
189 .parent = &platform_bus, \
190 .name = #hci "-platform", \
191 .id = -1, \
192 .res = hci##_resources, \
193 .num_res = ARRAY_SIZE(hci##_resources), \
194 .data = &hci##_pdata, \
195 .size_data = sizeof(hci##_pdata), \
196 .dma_mask = DMA_BIT_MASK(32), \
197 }
198
199 USB_PLATFORM_INFO(ehci);
200 USB_PLATFORM_INFO(ohci);
201
202 /* PFC/GPIO */
203 static struct resource pfc_resources[] __initdata = {
204 DEFINE_RES_MEM(0xfffc0000, 0x118),
205 };
206
207 #define R8A7778_GPIO(idx) \
208 static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \
209 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \
210 DEFINE_RES_IRQ(gic_iid(0x87)), \
211 }; \
212 \
213 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
214 .gpio_base = 32 * (idx), \
215 .irq_base = GPIO_IRQ_BASE(idx), \
216 .number_of_pins = 32, \
217 .pctl_name = "pfc-r8a7778", \
218 }
219
220 R8A7778_GPIO(0);
221 R8A7778_GPIO(1);
222 R8A7778_GPIO(2);
223 R8A7778_GPIO(3);
224 R8A7778_GPIO(4);
225
226 #define r8a7778_register_gpio(idx) \
227 platform_device_register_resndata( \
228 &platform_bus, "gpio_rcar", idx, \
229 r8a7778_gpio##idx##_resources, \
230 ARRAY_SIZE(r8a7778_gpio##idx##_resources), \
231 &r8a7778_gpio##idx##_platform_data, \
232 sizeof(r8a7778_gpio##idx##_platform_data))
233
234 void __init r8a7778_pinmux_init(void)
235 {
236 platform_device_register_simple(
237 "pfc-r8a7778", -1,
238 pfc_resources,
239 ARRAY_SIZE(pfc_resources));
240
241 r8a7778_register_gpio(0);
242 r8a7778_register_gpio(1);
243 r8a7778_register_gpio(2);
244 r8a7778_register_gpio(3);
245 r8a7778_register_gpio(4);
246 };
247
248 /* I2C */
249 static struct resource i2c_resources[] __initdata = {
250 /* I2C0 */
251 DEFINE_RES_MEM(0xffc70000, 0x1000),
252 DEFINE_RES_IRQ(gic_iid(0x63)),
253 /* I2C1 */
254 DEFINE_RES_MEM(0xffc71000, 0x1000),
255 DEFINE_RES_IRQ(gic_iid(0x6e)),
256 /* I2C2 */
257 DEFINE_RES_MEM(0xffc72000, 0x1000),
258 DEFINE_RES_IRQ(gic_iid(0x6c)),
259 /* I2C3 */
260 DEFINE_RES_MEM(0xffc73000, 0x1000),
261 DEFINE_RES_IRQ(gic_iid(0x6d)),
262 };
263
264 static void __init r8a7778_register_i2c(int id)
265 {
266 BUG_ON(id < 0 || id > 3);
267
268 platform_device_register_simple(
269 "i2c-rcar", id,
270 i2c_resources + (2 * id), 2);
271 }
272
273 /* HSPI */
274 static struct resource hspi_resources[] __initdata = {
275 /* HSPI0 */
276 DEFINE_RES_MEM(0xfffc7000, 0x18),
277 DEFINE_RES_IRQ(gic_iid(0x5f)),
278 /* HSPI1 */
279 DEFINE_RES_MEM(0xfffc8000, 0x18),
280 DEFINE_RES_IRQ(gic_iid(0x74)),
281 /* HSPI2 */
282 DEFINE_RES_MEM(0xfffc6000, 0x18),
283 DEFINE_RES_IRQ(gic_iid(0x75)),
284 };
285
286 static void __init r8a7778_register_hspi(int id)
287 {
288 BUG_ON(id < 0 || id > 2);
289
290 platform_device_register_simple(
291 "sh-hspi", id,
292 hspi_resources + (2 * id), 2);
293 }
294
295 void __init r8a7778_add_dt_devices(void)
296 {
297 #ifdef CONFIG_CACHE_L2X0
298 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
299 if (base) {
300 /*
301 * Early BRESP enable, Shared attribute override enable, 64K*16way
302 * don't call iounmap(base)
303 */
304 l2x0_init(base, 0x40470000, 0x82000fff);
305 }
306 #endif
307
308 r8a7778_register_scif(0);
309 r8a7778_register_scif(1);
310 r8a7778_register_scif(2);
311 r8a7778_register_scif(3);
312 r8a7778_register_scif(4);
313 r8a7778_register_scif(5);
314 r8a7778_register_tmu(0);
315 r8a7778_register_tmu(1);
316 }
317
318 /* HPB-DMA */
319
320 /* Asynchronous mode register (ASYNCMDR) bits */
321 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */
322 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */
323 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
324 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */
325 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
326 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
327
328 #define HPBDMA_SSI(_id) \
329 { \
330 .id = HPBDMA_SLAVE_SSI## _id ##_TX, \
331 .addr = 0xffd91008 + (_id * 0x40), \
332 .dcr = HPB_DMAE_DCR_CT | \
333 HPB_DMAE_DCR_DIP | \
334 HPB_DMAE_DCR_SPDS_32BIT | \
335 HPB_DMAE_DCR_DMDL | \
336 HPB_DMAE_DCR_DPDS_32BIT, \
337 .port = _id + (_id << 8), \
338 .dma_ch = (28 + _id), \
339 }, { \
340 .id = HPBDMA_SLAVE_SSI## _id ##_RX, \
341 .addr = 0xffd9100c + (_id * 0x40), \
342 .dcr = HPB_DMAE_DCR_CT | \
343 HPB_DMAE_DCR_DIP | \
344 HPB_DMAE_DCR_SMDL | \
345 HPB_DMAE_DCR_SPDS_32BIT | \
346 HPB_DMAE_DCR_DPDS_32BIT, \
347 .port = _id + (_id << 8), \
348 .dma_ch = (28 + _id), \
349 }
350
351 #define HPBDMA_HPBIF(_id) \
352 { \
353 .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
354 .addr = 0xffda0000 + (_id * 0x1000), \
355 .dcr = HPB_DMAE_DCR_CT | \
356 HPB_DMAE_DCR_DIP | \
357 HPB_DMAE_DCR_SPDS_32BIT | \
358 HPB_DMAE_DCR_DMDL | \
359 HPB_DMAE_DCR_DPDS_32BIT, \
360 .port = 0x1111, \
361 .dma_ch = (28 + _id), \
362 }, { \
363 .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \
364 .addr = 0xffda0000 + (_id * 0x1000), \
365 .dcr = HPB_DMAE_DCR_CT | \
366 HPB_DMAE_DCR_DIP | \
367 HPB_DMAE_DCR_SMDL | \
368 HPB_DMAE_DCR_SPDS_32BIT | \
369 HPB_DMAE_DCR_DPDS_32BIT, \
370 .port = 0x1111, \
371 .dma_ch = (28 + _id), \
372 }
373
374 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
375 {
376 .id = HPBDMA_SLAVE_SDHI0_TX,
377 .addr = 0xffe4c000 + 0x30,
378 .dcr = HPB_DMAE_DCR_SPDS_16BIT |
379 HPB_DMAE_DCR_DMDL |
380 HPB_DMAE_DCR_DPDS_16BIT,
381 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
382 HPB_DMAE_ASYNCRSTR_ASRST22 |
383 HPB_DMAE_ASYNCRSTR_ASRST23,
384 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
385 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK,
386 .port = 0x0D0C,
387 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
388 .dma_ch = 21,
389 }, {
390 .id = HPBDMA_SLAVE_SDHI0_RX,
391 .addr = 0xffe4c000 + 0x30,
392 .dcr = HPB_DMAE_DCR_SMDL |
393 HPB_DMAE_DCR_SPDS_16BIT |
394 HPB_DMAE_DCR_DPDS_16BIT,
395 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
396 HPB_DMAE_ASYNCRSTR_ASRST22 |
397 HPB_DMAE_ASYNCRSTR_ASRST23,
398 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
399 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK,
400 .port = 0x0D0C,
401 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
402 .dma_ch = 22,
403 }, {
404 .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
405 .addr = 0xffe60018,
406 .dcr = HPB_DMAE_DCR_SPDS_32BIT |
407 HPB_DMAE_DCR_DMDL |
408 HPB_DMAE_DCR_DPDS_32BIT,
409 .port = 0x0000,
410 .dma_ch = 14,
411 }, {
412 .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
413 .addr = 0xffe6001c,
414 .dcr = HPB_DMAE_DCR_SMDL |
415 HPB_DMAE_DCR_SPDS_32BIT |
416 HPB_DMAE_DCR_DPDS_32BIT,
417 .port = 0x0101,
418 .dma_ch = 15,
419 },
420
421 HPBDMA_SSI(0),
422 HPBDMA_SSI(1),
423 HPBDMA_SSI(2),
424 HPBDMA_SSI(3),
425 HPBDMA_SSI(4),
426 HPBDMA_SSI(5),
427 HPBDMA_SSI(6),
428 HPBDMA_SSI(7),
429 HPBDMA_SSI(8),
430
431 HPBDMA_HPBIF(0),
432 HPBDMA_HPBIF(1),
433 HPBDMA_HPBIF(2),
434 HPBDMA_HPBIF(3),
435 HPBDMA_HPBIF(4),
436 HPBDMA_HPBIF(5),
437 HPBDMA_HPBIF(6),
438 HPBDMA_HPBIF(7),
439 HPBDMA_HPBIF(8),
440 };
441
442 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
443 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
444 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
445 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
446 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
447 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */
448 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */
449 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
450 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
451 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */
452 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */
453 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
454 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
455 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */
456 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */
457 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
458 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
459 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */
460 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */
461 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
462 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
463 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */
464 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */
465 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
466 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
467 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */
468 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */
469 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
470 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
471 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */
472 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */
473 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
474 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
475 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */
476 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */
477 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
478 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
479 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */
480 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */
481 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
482 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
483 };
484
485 static struct hpb_dmae_pdata dma_platform_data __initdata = {
486 .slaves = hpb_dmae_slaves,
487 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
488 .channels = hpb_dmae_channels,
489 .num_channels = ARRAY_SIZE(hpb_dmae_channels),
490 .ts_shift = {
491 [XMIT_SZ_8BIT] = 0,
492 [XMIT_SZ_16BIT] = 1,
493 [XMIT_SZ_32BIT] = 2,
494 },
495 .num_hw_channels = 39,
496 };
497
498 static struct resource hpb_dmae_resources[] __initdata = {
499 /* Channel registers */
500 DEFINE_RES_MEM(0xffc08000, 0x1000),
501 /* Common registers */
502 DEFINE_RES_MEM(0xffc09000, 0x170),
503 /* Asynchronous reset registers */
504 DEFINE_RES_MEM(0xffc00300, 4),
505 /* Asynchronous mode registers */
506 DEFINE_RES_MEM(0xffc00400, 4),
507 /* IRQ for DMA channels */
508 DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
509 };
510
511 static void __init r8a7778_register_hpb_dmae(void)
512 {
513 platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
514 hpb_dmae_resources,
515 ARRAY_SIZE(hpb_dmae_resources),
516 &dma_platform_data,
517 sizeof(dma_platform_data));
518 }
519
520 void __init r8a7778_add_standard_devices(void)
521 {
522 r8a7778_add_dt_devices();
523 r8a7778_register_i2c(0);
524 r8a7778_register_i2c(1);
525 r8a7778_register_i2c(2);
526 r8a7778_register_i2c(3);
527 r8a7778_register_hspi(0);
528 r8a7778_register_hspi(1);
529 r8a7778_register_hspi(2);
530
531 r8a7778_register_hpb_dmae();
532 }
533
534 void __init r8a7778_init_late(void)
535 {
536 platform_device_register_full(&ehci_info);
537 platform_device_register_full(&ohci_info);
538 }
539
540 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
541 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
542 .sense_bitfield_width = 2,
543 };
544
545 static struct resource irqpin_resources[] __initdata = {
546 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
547 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
548 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
549 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
550 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
551 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
552 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
553 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
554 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
555 };
556
557 void __init r8a7778_init_irq_extpin_dt(int irlm)
558 {
559 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
560 unsigned long tmp;
561
562 if (!icr0) {
563 pr_warn("r8a7778: unable to setup external irq pin mode\n");
564 return;
565 }
566
567 tmp = ioread32(icr0);
568 if (irlm)
569 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
570 else
571 tmp &= ~(1 << 23); /* IRL mode - not supported */
572 tmp |= (1 << 21); /* LVLMODE = 1 */
573 iowrite32(tmp, icr0);
574 iounmap(icr0);
575 }
576
577 void __init r8a7778_init_irq_extpin(int irlm)
578 {
579 r8a7778_init_irq_extpin_dt(irlm);
580 if (irlm)
581 platform_device_register_resndata(
582 &platform_bus, "renesas_intc_irqpin", -1,
583 irqpin_resources, ARRAY_SIZE(irqpin_resources),
584 &irqpin_platform_data, sizeof(irqpin_platform_data));
585 }
586
587 void __init r8a7778_init_delay(void)
588 {
589 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
590 }
591
592 #ifdef CONFIG_USE_OF
593 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */
594 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */
595
596 #define INT2NTSR0 0x00018 /* 0xfe700018 */
597 #define INT2NTSR1 0x0002c /* 0xfe70002c */
598 void __init r8a7778_init_irq_dt(void)
599 {
600 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
601
602 BUG_ON(!base);
603
604 irqchip_init();
605
606 /* route all interrupts to ARM */
607 __raw_writel(0x73ffffff, base + INT2NTSR0);
608 __raw_writel(0xffffffff, base + INT2NTSR1);
609
610 /* unmask all known interrupts in INTCS2 */
611 __raw_writel(0x08330773, base + INT2SMSKCR0);
612 __raw_writel(0x00311110, base + INT2SMSKCR1);
613
614 iounmap(base);
615 }
616
617 static const char *r8a7778_compat_dt[] __initdata = {
618 "renesas,r8a7778",
619 NULL,
620 };
621
622 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
623 .init_early = r8a7778_init_delay,
624 .init_irq = r8a7778_init_irq_dt,
625 .dt_compat = r8a7778_compat_dt,
626 .init_late = r8a7778_init_late,
627 MACHINE_END
628
629 #endif /* CONFIG_USE_OF */
Linux with added FPC-III support