arch/arm/mach-tegra/fuse.c

   1 /*
   2  * arch/arm/mach-tegra/fuse.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * Author:
   8  *      Colin Cross <ccross@android.com>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/io.h>
  23 #include <linux/export.h>
  24 #include <linux/random.h>
  25 #include <linux/clk.h>
  26 #include <linux/tegra-soc.h>
  27
  28 #include "fuse.h"
  29 #include "iomap.h"
  30 #include "apbio.h"
  31
  32 /* Tegra20 only */
  33 #define FUSE_UID_LOW            0x108
  34 #define FUSE_UID_HIGH           0x10c
  35
  36 /* Tegra30 and later */
  37 #define FUSE_VENDOR_CODE        0x200
  38 #define FUSE_FAB_CODE           0x204
  39 #define FUSE_LOT_CODE_0         0x208
  40 #define FUSE_LOT_CODE_1         0x20c
  41 #define FUSE_WAFER_ID           0x210
  42 #define FUSE_X_COORDINATE       0x214
  43 #define FUSE_Y_COORDINATE       0x218
  44
  45 #define FUSE_SKU_INFO           0x110
  46
  47 #define TEGRA20_FUSE_SPARE_BIT          0x200
  48 #define TEGRA30_FUSE_SPARE_BIT          0x244
  49
  50 int tegra_sku_id;
  51 int tegra_cpu_process_id;
  52 int tegra_core_process_id;
  53 int tegra_chip_id;
  54 int tegra_cpu_speedo_id;                /* only exist in Tegra30 and later */
  55 int tegra_soc_speedo_id;
  56 enum tegra_revision tegra_revision;
  57
  58 static struct clk *fuse_clk;
  59 static int tegra_fuse_spare_bit;
  60 static void (*tegra_init_speedo_data)(void);
  61
  62 /* The BCT to use at boot is specified by board straps that can be read
  63  * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
  64  */
  65 int tegra_bct_strapping;
  66
  67 #define STRAP_OPT 0x008
  68 #define GMI_AD0 (1 << 4)
  69 #define GMI_AD1 (1 << 5)
  70 #define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
  71 #define RAM_CODE_SHIFT 4
  72
  73 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
  74         [TEGRA_REVISION_UNKNOWN] = "unknown",
  75         [TEGRA_REVISION_A01]     = "A01",
  76         [TEGRA_REVISION_A02]     = "A02",
  77         [TEGRA_REVISION_A03]     = "A03",
  78         [TEGRA_REVISION_A03p]    = "A03 prime",
  79         [TEGRA_REVISION_A04]     = "A04",
  80 };
  81
  82 static void tegra_fuse_enable_clk(void)
  83 {
  84         if (IS_ERR(fuse_clk))
  85                 fuse_clk = clk_get_sys(NULL, "fuse");
  86         if (IS_ERR(fuse_clk))
  87                 return;
  88         clk_prepare_enable(fuse_clk);
  89 }
  90
  91 static void tegra_fuse_disable_clk(void)
  92 {
  93         if (IS_ERR(fuse_clk))
  94                 return;
  95         clk_disable_unprepare(fuse_clk);
  96 }
  97
  98 u32 tegra_fuse_readl(unsigned long offset)
  99 {
 100         return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
 101 }
 102
 103 bool tegra_spare_fuse(int bit)
 104 {
 105         bool ret;
 106
 107         tegra_fuse_enable_clk();
 108
 109         ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
 110
 111         tegra_fuse_disable_clk();
 112
 113         return ret;
 114 }
 115
 116 static enum tegra_revision tegra_get_revision(u32 id)
 117 {
 118         u32 minor_rev = (id >> 16) & 0xf;
 119
 120         switch (minor_rev) {
 121         case 1:
 122                 return TEGRA_REVISION_A01;
 123         case 2:
 124                 return TEGRA_REVISION_A02;
 125         case 3:
 126                 if (tegra_chip_id == TEGRA20 &&
 127                         (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
 128                         return TEGRA_REVISION_A03p;
 129                 else
 130                         return TEGRA_REVISION_A03;
 131         case 4:
 132                 return TEGRA_REVISION_A04;
 133         default:
 134                 return TEGRA_REVISION_UNKNOWN;
 135         }
 136 }
 137
 138 static void tegra_get_process_id(void)
 139 {
 140         u32 reg;
 141
 142         tegra_fuse_enable_clk();
 143
 144         reg = tegra_fuse_readl(tegra_fuse_spare_bit);
 145         tegra_cpu_process_id = (reg >> 6) & 3;
 146         reg = tegra_fuse_readl(tegra_fuse_spare_bit);
 147         tegra_core_process_id = (reg >> 12) & 3;
 148
 149         tegra_fuse_disable_clk();
 150 }
 151
 152 u32 tegra_read_chipid(void)
 153 {
 154         return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
 155 }
 156
 157 static void __init tegra20_fuse_init_randomness(void)
 158 {
 159         u32 randomness[2];
 160
 161         randomness[0] = tegra_fuse_readl(FUSE_UID_LOW);
 162         randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH);
 163
 164         add_device_randomness(randomness, sizeof(randomness));
 165 }
 166
 167 /* Applies to Tegra30 or later */
 168 static void __init tegra30_fuse_init_randomness(void)
 169 {
 170         u32 randomness[7];
 171
 172         randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE);
 173         randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE);
 174         randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0);
 175         randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1);
 176         randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID);
 177         randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE);
 178         randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE);
 179
 180         add_device_randomness(randomness, sizeof(randomness));
 181 }
 182
 183 void __init tegra_init_fuse(void)
 184 {
 185         u32 id;
 186         u32 randomness[5];
 187
 188         u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 189         reg |= 1 << 28;
 190         writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 191
 192         /*
 193          * Enable FUSE clock. This needs to be hardcoded because the clock
 194          * subsystem is not active during early boot.
 195          */
 196         reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
 197         reg |= 1 << 7;
 198         writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
 199         fuse_clk = ERR_PTR(-EINVAL);
 200
 201         reg = tegra_fuse_readl(FUSE_SKU_INFO);
 202         randomness[0] = reg;
 203         tegra_sku_id = reg & 0xFF;
 204
 205         reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
 206         randomness[1] = reg;
 207         tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
 208
 209         id = tegra_read_chipid();
 210         randomness[2] = id;
 211         tegra_chip_id = (id >> 8) & 0xff;
 212
 213         switch (tegra_chip_id) {
 214         case TEGRA20:
 215                 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
 216                 tegra_init_speedo_data = &tegra20_init_speedo_data;
 217                 break;
 218         case TEGRA30:
 219                 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
 220                 tegra_init_speedo_data = &tegra30_init_speedo_data;
 221                 break;
 222         case TEGRA114:
 223                 tegra_init_speedo_data = &tegra114_init_speedo_data;
 224                 break;
 225         default:
 226                 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
 227                 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
 228                 tegra_init_speedo_data = &tegra_get_process_id;
 229         }
 230
 231         tegra_revision = tegra_get_revision(id);
 232         tegra_init_speedo_data();
 233         randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id;
 234         randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id;
 235
 236         add_device_randomness(randomness, sizeof(randomness));
 237         switch (tegra_chip_id) {
 238         case TEGRA20:
 239                 tegra20_fuse_init_randomness();
 240                 break;
 241         case TEGRA30:
 242         case TEGRA114:
 243         default:
 244                 tegra30_fuse_init_randomness();
 245                 break;
 246         }
 247
 248         pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
 249                 tegra_revision_name[tegra_revision],
 250                 tegra_sku_id, tegra_cpu_process_id,
 251                 tegra_core_process_id);
 252 }