arch/c6x/include/asm/clock.h

   1 /*
   2  * TI C64X clock definitions
   3  *
   4  * Copyright (C) 2010, 2011 Texas Instruments.
   5  * Contributed by: Mark Salter <msalter@redhat.com>
   6  *
   7  * Copied heavily from arm/mach-davinci/clock.h, so:
   8  *
   9  * Copyright (C) 2006-2007 Texas Instruments.
  10  * Copyright (C) 2008-2009 Deep Root Systems, LLC
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef _ASM_C6X_CLOCK_H
  18 #define _ASM_C6X_CLOCK_H
  19
  20 #ifndef __ASSEMBLER__
  21
  22 #include <linux/list.h>
  23
  24 /* PLL/Reset register offsets */
  25 #define PLLCTL          0x100
  26 #define PLLM            0x110
  27 #define PLLPRE          0x114
  28 #define PLLDIV1         0x118
  29 #define PLLDIV2         0x11c
  30 #define PLLDIV3         0x120
  31 #define PLLPOST         0x128
  32 #define PLLCMD          0x138
  33 #define PLLSTAT         0x13c
  34 #define PLLALNCTL       0x140
  35 #define PLLDCHANGE      0x144
  36 #define PLLCKEN         0x148
  37 #define PLLCKSTAT       0x14c
  38 #define PLLSYSTAT       0x150
  39 #define PLLDIV4         0x160
  40 #define PLLDIV5         0x164
  41 #define PLLDIV6         0x168
  42 #define PLLDIV7         0x16c
  43 #define PLLDIV8         0x170
  44 #define PLLDIV9         0x174
  45 #define PLLDIV10        0x178
  46 #define PLLDIV11        0x17c
  47 #define PLLDIV12        0x180
  48 #define PLLDIV13        0x184
  49 #define PLLDIV14        0x188
  50 #define PLLDIV15        0x18c
  51 #define PLLDIV16        0x190
  52
  53 /* PLLM register bits */
  54 #define PLLM_PLLM_MASK  0xff
  55 #define PLLM_VAL(x)     ((x) - 1)
  56
  57 /* PREDIV register bits */
  58 #define PLLPREDIV_EN    BIT(15)
  59 #define PLLPREDIV_VAL(x) ((x) - 1)
  60
  61 /* PLLCTL register bits */
  62 #define PLLCTL_PLLEN    BIT(0)
  63 #define PLLCTL_PLLPWRDN BIT(1)
  64 #define PLLCTL_PLLRST   BIT(3)
  65 #define PLLCTL_PLLDIS   BIT(4)
  66 #define PLLCTL_PLLENSRC BIT(5)
  67 #define PLLCTL_CLKMODE  BIT(8)
  68
  69 /* PLLCMD register bits */
  70 #define PLLCMD_GOSTAT   BIT(0)
  71
  72 /* PLLSTAT register bits */
  73 #define PLLSTAT_GOSTAT  BIT(0)
  74
  75 /* PLLDIV register bits */
  76 #define PLLDIV_EN       BIT(15)
  77 #define PLLDIV_RATIO_MASK 0x1f
  78 #define PLLDIV_RATIO(x) ((x) - 1)
  79
  80 struct pll_data;
  81
  82 struct clk {
  83         struct list_head        node;
  84         struct module           *owner;
  85         const char              *name;
  86         unsigned long           rate;
  87         int                     usecount;
  88         u32                     flags;
  89         struct clk              *parent;
  90         struct list_head        children;       /* list of children */
  91         struct list_head        childnode;      /* parent's child list node */
  92         struct pll_data         *pll_data;
  93         u32                     div;
  94         unsigned long (*recalc) (struct clk *);
  95         int (*set_rate) (struct clk *clk, unsigned long rate);
  96         int (*round_rate) (struct clk *clk, unsigned long rate);
  97 };
  98
  99 /* Clock flags: SoC-specific flags start at BIT(16) */
 100 #define ALWAYS_ENABLED          BIT(1)
 101 #define CLK_PLL                 BIT(2) /* PLL-derived clock */
 102 #define PRE_PLL                 BIT(3) /* source is before PLL mult/div */
 103 #define FIXED_DIV_PLL           BIT(4) /* fixed divisor from PLL */
 104 #define FIXED_RATE_PLL          BIT(5) /* fixed ouput rate PLL */
 105
 106 #define MAX_PLL_SYSCLKS 16
 107
 108 struct pll_data {
 109         void __iomem *base;
 110         u32 num;
 111         u32 flags;
 112         u32 input_rate;
 113         u32 bypass_delay; /* in loops */
 114         u32 reset_delay;  /* in loops */
 115         u32 lock_delay;   /* in loops */
 116         struct clk sysclks[MAX_PLL_SYSCLKS + 1];
 117 };
 118
 119 /* pll_data flag bit */
 120 #define PLL_HAS_PRE     BIT(0)
 121 #define PLL_HAS_MUL     BIT(1)
 122 #define PLL_HAS_POST    BIT(2)
 123
 124 #define CLK(dev, con, ck)       \
 125         {                       \
 126                 .dev_id = dev,  \
 127                 .con_id = con,  \
 128                 .clk = ck,      \
 129         }                       \
 130
 131 extern void c6x_clks_init(struct clk_lookup *clocks);
 132 extern int clk_register(struct clk *clk);
 133 extern void clk_unregister(struct clk *clk);
 134 extern void c64x_setup_clocks(void);
 135
 136 extern struct pll_data c6x_soc_pll1;
 137
 138 extern struct clk clkin1;
 139 extern struct clk c6x_core_clk;
 140 extern struct clk c6x_i2c_clk;
 141 extern struct clk c6x_watchdog_clk;
 142 extern struct clk c6x_mcbsp1_clk;
 143 extern struct clk c6x_mcbsp2_clk;
 144 extern struct clk c6x_mdio_clk;
 145
 146 #endif
 147
 148 #endif /* _ASM_C6X_CLOCK_H */