1 #include <linux/init.h>
3 #include <asm/mips-boards/piix4.h>
5 /* PCI interrupt pins */
11 /* This table is filled in by interrogating the PIIX4 chip */
12 static char pci_irq
[5] = {
15 static char irq_tab
[][5] __initdata
= {
16 /* INTA INTB INTC INTD */
17 {0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */
18 {0, 0, 0, 0, 0 }, /* 1: Unused */
19 {0, 0, 0, 0, 0 }, /* 2: Unused */
20 {0, 0, 0, 0, 0 }, /* 3: Unused */
21 {0, 0, 0, 0, 0 }, /* 4: Unused */
22 {0, 0, 0, 0, 0 }, /* 5: Unused */
23 {0, 0, 0, 0, 0 }, /* 6: Unused */
24 {0, 0, 0, 0, 0 }, /* 7: Unused */
25 {0, 0, 0, 0, 0 }, /* 8: Unused */
26 {0, 0, 0, 0, 0 }, /* 9: Unused */
27 {0, 0, 0, 0, PCID
}, /* 10: PIIX4 USB */
28 {0, PCIB
, 0, 0, 0 }, /* 11: AMD 79C973 Ethernet */
29 {0, PCIC
, 0, 0, 0 }, /* 12: Crystal 4281 Sound */
30 {0, 0, 0, 0, 0 }, /* 13: Unused */
31 {0, 0, 0, 0, 0 }, /* 14: Unused */
32 {0, 0, 0, 0, 0 }, /* 15: Unused */
33 {0, 0, 0, 0, 0 }, /* 16: Unused */
34 {0, 0, 0, 0, 0 }, /* 17: Bonito/SOC-it PCI Bridge*/
35 {0, PCIA
, PCIB
, PCIC
, PCID
}, /* 18: PCI Slot 1 */
36 {0, PCIB
, PCIC
, PCID
, PCIA
}, /* 19: PCI Slot 2 */
37 {0, PCIC
, PCID
, PCIA
, PCIB
}, /* 20: PCI Slot 3 */
38 {0, PCID
, PCIA
, PCIB
, PCIC
} /* 21: PCI Slot 4 */
41 int __init
pcibios_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
44 virq
= irq_tab
[slot
][pin
];
48 /* Do platform specific device initialization at pci_enable_device() time */
49 int pcibios_plat_dev_init(struct pci_dev
*dev
)
54 static void malta_piix_func0_fixup(struct pci_dev
*pdev
)
56 unsigned char reg_val
;
58 /* PIIX PIRQC[A:D] irq mappings */
59 static int piixirqmap
[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX
] = {
67 /* Interrogate PIIX4 to get PCI IRQ mapping */
68 for (i
= 0; i
<= 3; i
++) {
69 pci_read_config_byte(pdev
, PIIX4_FUNC0_PIRQRC
+i
, ®_val
);
70 if (reg_val
& PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE
)
71 pci_irq
[PCIA
+i
] = 0; /* Disabled */
73 pci_irq
[PCIA
+i
] = piixirqmap
[reg_val
&
74 PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK
];
77 /* Done by YAMON 2.00 onwards */
78 if (PCI_SLOT(pdev
->devfn
) == 10) {
80 * Set top of main memory accessible by ISA or DMA
83 pci_read_config_byte(pdev
, PIIX4_FUNC0_TOM
, ®_val
);
84 pci_write_config_byte(pdev
, PIIX4_FUNC0_TOM
, reg_val
|
85 PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK
);
88 /* Mux SERIRQ to its pin */
89 pci_read_config_dword(pdev
, PIIX4_FUNC0_GENCFG
, ®_val32
);
90 pci_write_config_dword(pdev
, PIIX4_FUNC0_GENCFG
,
91 reg_val32
| PIIX4_FUNC0_GENCFG_SERIRQ
);
94 pci_read_config_byte(pdev
, PIIX4_FUNC0_SERIRQC
, ®_val
);
95 reg_val
|= PIIX4_FUNC0_SERIRQC_EN
| PIIX4_FUNC0_SERIRQC_CONT
;
96 pci_write_config_byte(pdev
, PIIX4_FUNC0_SERIRQC
, reg_val
);
99 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_0
,
100 malta_piix_func0_fixup
);
102 static void malta_piix_func1_fixup(struct pci_dev
*pdev
)
104 unsigned char reg_val
;
106 /* Done by YAMON 2.02 onwards */
107 if (PCI_SLOT(pdev
->devfn
) == 10) {
111 pci_read_config_byte(pdev
, PIIX4_FUNC1_IDETIM_PRIMARY_HI
,
113 pci_write_config_byte(pdev
, PIIX4_FUNC1_IDETIM_PRIMARY_HI
,
114 reg_val
|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN
);
115 pci_read_config_byte(pdev
, PIIX4_FUNC1_IDETIM_SECONDARY_HI
,
117 pci_write_config_byte(pdev
, PIIX4_FUNC1_IDETIM_SECONDARY_HI
,
118 reg_val
|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN
);
122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB
,
123 malta_piix_func1_fixup
);
125 /* Enable PCI 2.1 compatibility in PIIX4 */
126 static void quirk_dlcsetup(struct pci_dev
*dev
)
130 (void) pci_read_config_byte(dev
, PIIX4_FUNC0_DLC
, &odlc
);
131 /* Enable passive releases and delayed transaction */
132 ndlc
= odlc
| PIIX4_FUNC0_DLC_USBPR_EN
|
133 PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN
|
134 PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN
;
135 (void) pci_write_config_byte(dev
, PIIX4_FUNC0_DLC
, ndlc
);
138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_0
,