| blob | 651e4f55acdbf6f6187b1792315c780f127effde |
1 /*
2 * mpc8308_p1m Device Tree Source
3 *
4 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 compatible = "denx,mpc8308_p1m";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 };
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
31 PowerPC,8308@0 {
32 device_type = "cpu";
33 reg = <0x0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <16384>;
37 i-cache-size = <16384>;
38 timebase-frequency = <0>; // from bootloader
39 bus-frequency = <0>; // from bootloader
40 clock-frequency = <0>; // from bootloader
41 };
42 };
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x08000000>; // 128MB at 0
47 };
49 localbus@e0005000 {
50 #address-cells = <2>;
51 #size-cells = <1>;
52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 0x8>;
55 interrupt-parent = <&ipic>;
57 ranges = <0x0 0x0 0xfc000000 0x04000000
58 0x1 0x0 0xfbff0000 0x00008000
59 0x2 0x0 0xfbff8000 0x00008000>;
61 flash@0,0 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
65 reg = <0x0 0x0 0x4000000>;
66 bank-width = <2>;
67 device-width = <1>;
69 u-boot@0 {
70 reg = <0x0 0x60000>;
71 read-only;
72 };
73 env@60000 {
74 reg = <0x60000 0x20000>;
75 };
76 env1@80000 {
77 reg = <0x80000 0x20000>;
78 };
79 kernel@a0000 {
80 reg = <0xa0000 0x200000>;
81 };
82 dtb@2a0000 {
83 reg = <0x2a0000 0x20000>;
84 };
85 ramdisk@2c0000 {
86 reg = <0x2c0000 0x640000>;
87 };
88 user@700000 {
89 reg = <0x700000 0x3900000>;
90 };
91 };
93 can@1,0 {
94 compatible = "nxp,sja1000";
95 reg = <0x1 0x0 0x80>;
96 interrupts = <18 0x8>;
97 interrups-parent = <&ipic>;
98 };
100 cpld@2,0 {
101 compatible = "denx,mpc8308_p1m-cpld";
102 reg = <0x2 0x0 0x8>;
103 interrupts = <48 0x8>;
104 interrups-parent = <&ipic>;
105 };
106 };
108 immr@e0000000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 device_type = "soc";
112 compatible = "fsl,mpc8308-immr", "simple-bus";
113 ranges = <0 0xe0000000 0x00100000>;
114 reg = <0xe0000000 0x00000200>;
115 bus-frequency = <0>;
117 i2c@3000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 compatible = "fsl-i2c";
121 reg = <0x3000 0x100>;
122 interrupts = <14 0x8>;
123 interrupt-parent = <&ipic>;
124 dfsrr;
125 fram@50 {
126 compatible = "ramtron,24c64";
127 reg = <0x50>;
128 };
129 };
131 i2c@3100 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 compatible = "fsl-i2c";
135 reg = <0x3100 0x100>;
136 interrupts = <15 0x8>;
137 interrupt-parent = <&ipic>;
138 dfsrr;
139 pwm@28 {
140 compatible = "maxim,ds1050";
141 reg = <0x28>;
142 };
143 sensor@48 {
144 compatible = "maxim,max6625";
145 reg = <0x48>;
146 };
147 sensor@49 {
148 compatible = "maxim,max6625";
149 reg = <0x49>;
150 };
151 sensor@4b {
152 compatible = "maxim,max6625";
153 reg = <0x4b>;
154 };
155 };
157 usb@23000 {
158 compatible = "fsl-usb2-dr";
159 reg = <0x23000 0x1000>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupt-parent = <&ipic>;
163 interrupts = <38 0x8>;
164 dr_mode = "peripheral";
165 phy_type = "ulpi";
166 };
168 enet0: ethernet@24000 {
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0x24000 0x1000>;
173 cell-index = <0>;
174 device_type = "network";
175 model = "eTSEC";
176 compatible = "gianfar";
177 reg = <0x24000 0x1000>;
178 local-mac-address = [ 00 00 00 00 00 00 ];
179 interrupts = <32 0x8 33 0x8 34 0x8>;
180 interrupt-parent = <&ipic>;
181 phy-handle = < &phy1 >;
183 mdio@520 {
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "fsl,gianfar-mdio";
187 reg = <0x520 0x20>;
188 phy1: ethernet-phy@1 {
189 interrupt-parent = <&ipic>;
190 interrupts = <17 0x8>;
191 reg = <0x1>;
192 };
193 phy2: ethernet-phy@2 {
194 interrupt-parent = <&ipic>;
195 interrupts = <19 0x8>;
196 reg = <0x2>;
197 };
198 tbi0: tbi-phy@11 {
199 reg = <0x11>;
200 device_type = "tbi-phy";
201 };
202 };
203 };
205 enet1: ethernet@25000 {
206 #address-cells = <1>;
207 #size-cells = <1>;
208 cell-index = <1>;
209 device_type = "network";
210 model = "eTSEC";
211 compatible = "gianfar";
212 reg = <0x25000 0x1000>;
213 ranges = <0x0 0x25000 0x1000>;
214 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <35 0x8 36 0x8 37 0x8>;
216 interrupt-parent = <&ipic>;
217 phy-handle = < &phy2 >;
219 mdio@520 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 compatible = "fsl,gianfar-tbi";
223 reg = <0x520 0x20>;
224 tbi1: tbi-phy@11 {
225 reg = <0x11>;
226 device_type = "tbi-phy";
227 };
228 };
229 };
231 serial0: serial@4500 {
232 cell-index = <0>;
233 device_type = "serial";
234 compatible = "fsl,ns16550", "ns16550";
235 reg = <0x4500 0x100>;
236 clock-frequency = <133333333>;
237 interrupts = <9 0x8>;
238 interrupt-parent = <&ipic>;
239 };
241 serial1: serial@4600 {
242 cell-index = <1>;
243 device_type = "serial";
244 compatible = "fsl,ns16550", "ns16550";
245 reg = <0x4600 0x100>;
246 clock-frequency = <133333333>;
247 interrupts = <10 0x8>;
248 interrupt-parent = <&ipic>;
249 };
251 gpio@c00 {
252 #gpio-cells = <2>;
253 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
254 reg = <0xc00 0x18>;
255 interrupts = <74 0x8>;
256 interrupt-parent = <&ipic>;
257 gpio-controller;
258 };
260 timer@500 {
261 compatible = "fsl,mpc8308-gtm", "fsl,gtm";
262 reg = <0x500 0x100>;
263 interrupts = <90 8 78 8 84 8 72 8>;
264 interrupt-parent = <&ipic>;
265 clock-frequency = <133333333>;
266 };
268 /* IPIC
269 * interrupts cell = <intr #, sense>
270 * sense values match linux IORESOURCE_IRQ_* defines:
271 * sense == 8: Level, low assertion
272 * sense == 2: Edge, high-to-low change
273 */
274 ipic: interrupt-controller@700 {
275 compatible = "fsl,ipic";
276 interrupt-controller;
277 #address-cells = <0>;
278 #interrupt-cells = <2>;
279 reg = <0x700 0x100>;
280 device_type = "ipic";
281 };
283 ipic-msi@7c0 {
284 compatible = "fsl,ipic-msi";
285 reg = <0x7c0 0x40>;
286 msi-available-ranges = <0x0 0x100>;
287 interrupts = < 0x43 0x8
288 0x4 0x8
289 0x51 0x8
290 0x52 0x8
291 0x56 0x8
292 0x57 0x8
293 0x58 0x8
294 0x59 0x8 >;
295 interrupt-parent = < &ipic >;
296 };
298 dma@2c000 {
299 compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
300 reg = <0x2c000 0x1800>;
301 interrupts = <3 0x8
302 94 0x8>;
303 interrupt-parent = < &ipic >;
304 };
306 };
308 pci0: pcie@e0009000 {
309 #address-cells = <3>;
310 #size-cells = <2>;
311 #interrupt-cells = <1>;
312 device_type = "pci";
313 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
314 reg = <0xe0009000 0x00001000
315 0xb0000000 0x01000000>;
316 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
317 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
318 bus-range = <0 0>;
319 interrupt-map-mask = <0 0 0 0>;
320 interrupt-map = <0 0 0 0 &ipic 1 8>;
321 interrupts = <0x1 0x8>;
322 interrupt-parent = <&ipic>;
323 clock-frequency = <0>;
325 pcie@0 {
326 #address-cells = <3>;
327 #size-cells = <2>;
328 device_type = "pci";
329 reg = <0 0 0 0 0>;
330 ranges = <0x02000000 0 0xa0000000
331 0x02000000 0 0xa0000000
332 0 0x10000000
333 0x01000000 0 0x00000000
334 0x01000000 0 0x00000000
335 0 0x00800000>;
336 };
337 };
338 };