arch/powerpc/boot/dts/mpc8555cds.dts

   1 /*
   2  * MPC8555 CDS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 /include/ "fsl/e500v2_power_isa.dtsi"
  15
  16 / {
  17         model = "MPC8555CDS";
  18         compatible = "MPC8555CDS", "MPC85xxCDS";
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         aliases {
  23                 ethernet0 = &enet0;
  24                 ethernet1 = &enet1;
  25                 serial0 = &serial0;
  26                 serial1 = &serial1;
  27                 pci0 = &pci0;
  28                 pci1 = &pci1;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,8555@0 {
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38                         d-cache-line-size = <32>;       // 32 bytes
  39                         i-cache-line-size = <32>;       // 32 bytes
  40                         d-cache-size = <0x8000>;                // L1, 32K
  41                         i-cache-size = <0x8000>;                // L1, 32K
  42                         timebase-frequency = <0>;       //  33 MHz, from uboot
  43                         bus-frequency = <0>;    // 166 MHz
  44                         clock-frequency = <0>;  // 825 MHz, from uboot
  45                         next-level-cache = <&L2>;
  46                 };
  47         };
  48
  49         memory {
  50                 device_type = "memory";
  51                 reg = <0x0 0x8000000>;  // 128M at 0x0
  52         };
  53
  54         soc8555@e0000000 {
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 device_type = "soc";
  58                 compatible = "simple-bus";
  59                 ranges = <0x0 0xe0000000 0x100000>;
  60                 bus-frequency = <0>;
  61
  62                 ecm-law@0 {
  63                         compatible = "fsl,ecm-law";
  64                         reg = <0x0 0x1000>;
  65                         fsl,num-laws = <8>;
  66                 };
  67
  68                 ecm@1000 {
  69                         compatible = "fsl,mpc8555-ecm", "fsl,ecm";
  70                         reg = <0x1000 0x1000>;
  71                         interrupts = <17 2>;
  72                         interrupt-parent = <&mpic>;
  73                 };
  74
  75                 memory-controller@2000 {
  76                         compatible = "fsl,mpc8555-memory-controller";
  77                         reg = <0x2000 0x1000>;
  78                         interrupt-parent = <&mpic>;
  79                         interrupts = <18 2>;
  80                 };
  81
  82                 L2: l2-cache-controller@20000 {
  83                         compatible = "fsl,mpc8555-l2-cache-controller";
  84                         reg = <0x20000 0x1000>;
  85                         cache-line-size = <32>; // 32 bytes
  86                         cache-size = <0x40000>; // L2, 256K
  87                         interrupt-parent = <&mpic>;
  88                         interrupts = <16 2>;
  89                 };
  90
  91                 i2c@3000 {
  92                         #address-cells = <1>;
  93                         #size-cells = <0>;
  94                         cell-index = <0>;
  95                         compatible = "fsl-i2c";
  96                         reg = <0x3000 0x100>;
  97                         interrupts = <43 2>;
  98                         interrupt-parent = <&mpic>;
  99                         dfsrr;
 100                 };
 101
 102                 dma@21300 {
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
 106                         reg = <0x21300 0x4>;
 107                         ranges = <0x0 0x21100 0x200>;
 108                         cell-index = <0>;
 109                         dma-channel@0 {
 110                                 compatible = "fsl,mpc8555-dma-channel",
 111                                                 "fsl,eloplus-dma-channel";
 112                                 reg = <0x0 0x80>;
 113                                 cell-index = <0>;
 114                                 interrupt-parent = <&mpic>;
 115                                 interrupts = <20 2>;
 116                         };
 117                         dma-channel@80 {
 118                                 compatible = "fsl,mpc8555-dma-channel",
 119                                                 "fsl,eloplus-dma-channel";
 120                                 reg = <0x80 0x80>;
 121                                 cell-index = <1>;
 122                                 interrupt-parent = <&mpic>;
 123                                 interrupts = <21 2>;
 124                         };
 125                         dma-channel@100 {
 126                                 compatible = "fsl,mpc8555-dma-channel",
 127                                                 "fsl,eloplus-dma-channel";
 128                                 reg = <0x100 0x80>;
 129                                 cell-index = <2>;
 130                                 interrupt-parent = <&mpic>;
 131                                 interrupts = <22 2>;
 132                         };
 133                         dma-channel@180 {
 134                                 compatible = "fsl,mpc8555-dma-channel",
 135                                                 "fsl,eloplus-dma-channel";
 136                                 reg = <0x180 0x80>;
 137                                 cell-index = <3>;
 138                                 interrupt-parent = <&mpic>;
 139                                 interrupts = <23 2>;
 140                         };
 141                 };
 142
 143                 enet0: ethernet@24000 {
 144                         #address-cells = <1>;
 145                         #size-cells = <1>;
 146                         cell-index = <0>;
 147                         device_type = "network";
 148                         model = "TSEC";
 149                         compatible = "gianfar";
 150                         reg = <0x24000 0x1000>;
 151                         ranges = <0x0 0x24000 0x1000>;
 152                         local-mac-address = [ 00 00 00 00 00 00 ];
 153                         interrupts = <29 2 30 2 34 2>;
 154                         interrupt-parent = <&mpic>;
 155                         tbi-handle = <&tbi0>;
 156                         phy-handle = <&phy0>;
 157
 158                         mdio@520 {
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161                                 compatible = "fsl,gianfar-mdio";
 162                                 reg = <0x520 0x20>;
 163
 164                                 phy0: ethernet-phy@0 {
 165                                         interrupt-parent = <&mpic>;
 166                                         interrupts = <5 1>;
 167                                         reg = <0x0>;
 168                                 };
 169                                 phy1: ethernet-phy@1 {
 170                                         interrupt-parent = <&mpic>;
 171                                         interrupts = <5 1>;
 172                                         reg = <0x1>;
 173                                 };
 174                                 tbi0: tbi-phy@11 {
 175                                         reg = <0x11>;
 176                                         device_type = "tbi-phy";
 177                                 };
 178                         };
 179                 };
 180
 181                 enet1: ethernet@25000 {
 182                         #address-cells = <1>;
 183                         #size-cells = <1>;
 184                         cell-index = <1>;
 185                         device_type = "network";
 186                         model = "TSEC";
 187                         compatible = "gianfar";
 188                         reg = <0x25000 0x1000>;
 189                         ranges = <0x0 0x25000 0x1000>;
 190                         local-mac-address = [ 00 00 00 00 00 00 ];
 191                         interrupts = <35 2 36 2 40 2>;
 192                         interrupt-parent = <&mpic>;
 193                         tbi-handle = <&tbi1>;
 194                         phy-handle = <&phy1>;
 195
 196                         mdio@520 {
 197                                 #address-cells = <1>;
 198                                 #size-cells = <0>;
 199                                 compatible = "fsl,gianfar-tbi";
 200                                 reg = <0x520 0x20>;
 201
 202                                 tbi1: tbi-phy@11 {
 203                                         reg = <0x11>;
 204                                         device_type = "tbi-phy";
 205                                 };
 206                         };
 207                 };
 208
 209                 serial0: serial@4500 {
 210                         cell-index = <0>;
 211                         device_type = "serial";
 212                         compatible = "fsl,ns16550", "ns16550";
 213                         reg = <0x4500 0x100>;   // reg base, size
 214                         clock-frequency = <0>;  // should we fill in in uboot?
 215                         interrupts = <42 2>;
 216                         interrupt-parent = <&mpic>;
 217                 };
 218
 219                 serial1: serial@4600 {
 220                         cell-index = <1>;
 221                         device_type = "serial";
 222                         compatible = "fsl,ns16550", "ns16550";
 223                         reg = <0x4600 0x100>;   // reg base, size
 224                         clock-frequency = <0>;  // should we fill in in uboot?
 225                         interrupts = <42 2>;
 226                         interrupt-parent = <&mpic>;
 227                 };
 228
 229                 crypto@30000 {
 230                         compatible = "fsl,sec2.0";
 231                         reg = <0x30000 0x10000>;
 232                         interrupts = <45 2>;
 233                         interrupt-parent = <&mpic>;
 234                         fsl,num-channels = <4>;
 235                         fsl,channel-fifo-len = <24>;
 236                         fsl,exec-units-mask = <0x7e>;
 237                         fsl,descriptor-types-mask = <0x01010ebf>;
 238                 };
 239
 240                 mpic: pic@40000 {
 241                         interrupt-controller;
 242                         #address-cells = <0>;
 243                         #interrupt-cells = <2>;
 244                         reg = <0x40000 0x40000>;
 245                         compatible = "chrp,open-pic";
 246                         device_type = "open-pic";
 247                 };
 248
 249                 cpm@919c0 {
 250                         #address-cells = <1>;
 251                         #size-cells = <1>;
 252                         compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
 253                         reg = <0x919c0 0x30>;
 254                         ranges;
 255
 256                         muram@80000 {
 257                                 #address-cells = <1>;
 258                                 #size-cells = <1>;
 259                                 ranges = <0x0 0x80000 0x10000>;
 260
 261                                 data@0 {
 262                                         compatible = "fsl,cpm-muram-data";
 263                                         reg = <0x0 0x2000 0x9000 0x1000>;
 264                                 };
 265                         };
 266
 267                         brg@919f0 {
 268                                 compatible = "fsl,mpc8555-brg",
 269                                              "fsl,cpm2-brg",
 270                                              "fsl,cpm-brg";
 271                                 reg = <0x919f0 0x10 0x915f0 0x10>;
 272                         };
 273
 274                         cpmpic: pic@90c00 {
 275                                 interrupt-controller;
 276                                 #address-cells = <0>;
 277                                 #interrupt-cells = <2>;
 278                                 interrupts = <46 2>;
 279                                 interrupt-parent = <&mpic>;
 280                                 reg = <0x90c00 0x80>;
 281                                 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
 282                         };
 283                 };
 284         };
 285
 286         pci0: pci@e0008000 {
 287                 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
 288                 interrupt-map = <
 289
 290                         /* IDSEL 0x10 */
 291                         0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
 292                         0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
 293                         0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
 294                         0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
 295
 296                         /* IDSEL 0x11 */
 297                         0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
 298                         0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
 299                         0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
 300                         0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
 301
 302                         /* IDSEL 0x12 (Slot 1) */
 303                         0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
 304                         0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
 305                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
 306                         0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
 307
 308                         /* IDSEL 0x13 (Slot 2) */
 309                         0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
 310                         0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
 311                         0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
 312                         0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
 313
 314                         /* IDSEL 0x14 (Slot 3) */
 315                         0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
 316                         0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
 317                         0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
 318                         0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
 319
 320                         /* IDSEL 0x15 (Slot 4) */
 321                         0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
 322                         0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
 323                         0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
 324                         0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
 325
 326                         /* Bus 1 (Tundra Bridge) */
 327                         /* IDSEL 0x12 (ISA bridge) */
 328                         0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
 329                         0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
 330                         0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
 331                         0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 332                 interrupt-parent = <&mpic>;
 333                 interrupts = <24 2>;
 334                 bus-range = <0 0>;
 335                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 336                           0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
 337                 clock-frequency = <66666666>;
 338                 #interrupt-cells = <1>;
 339                 #size-cells = <2>;
 340                 #address-cells = <3>;
 341                 reg = <0xe0008000 0x1000>;
 342                 compatible = "fsl,mpc8540-pci";
 343                 device_type = "pci";
 344
 345                 i8259@19000 {
 346                         interrupt-controller;
 347                         device_type = "interrupt-controller";
 348                         reg = <0x19000 0x0 0x0 0x0 0x1>;
 349                         #address-cells = <0>;
 350                         #interrupt-cells = <2>;
 351                         compatible = "chrp,iic";
 352                         interrupts = <1>;
 353                         interrupt-parent = <&pci0>;
 354                 };
 355         };
 356
 357         pci1: pci@e0009000 {
 358                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 359                 interrupt-map = <
 360
 361                         /* IDSEL 0x15 */
 362                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
 363                         0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
 364                         0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
 365                         0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
 366                 interrupt-parent = <&mpic>;
 367                 interrupts = <25 2>;
 368                 bus-range = <0 0>;
 369                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 370                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
 371                 clock-frequency = <66666666>;
 372                 #interrupt-cells = <1>;
 373                 #size-cells = <2>;
 374                 #address-cells = <3>;
 375                 reg = <0xe0009000 0x1000>;
 376                 compatible = "fsl,mpc8540-pci";
 377                 device_type = "pci";
 378         };
 379 };