2 * MPC8568E MDS Device Tree Source
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 /include/ "fsl/mpc8568si-pre.dtsi"
15 model = "MPC8568EMDS";
16 compatible = "MPC8568EMDS", "MPC85xxMDS";
25 device_type = "memory";
26 reg = <0x0 0x0 0x0 0x0>;
29 lbc: localbus@e0005000 {
30 reg = <0x0 0xe0005000 0x0 0x1000>;
31 ranges = <0x0 0x0 0xfe000000 0x02000000
32 0x1 0x0 0xf8000000 0x00008000
33 0x2 0x0 0xf0000000 0x04000000
34 0x4 0x0 0xf8008000 0x00008000
35 0x5 0x0 0xf8010000 0x00008000>;
40 compatible = "cfi-flash";
41 reg = <0x0 0x0 0x02000000>;
49 compatible = "fsl,mpc8568mds-bcsr";
51 ranges = <0 1 0 0x8000>;
53 bcsr5: gpio-controller@11 {
55 compatible = "fsl,mpc8568mds-bcsr-gpio";
62 compatible = "fsl,mpc8568mds-pib";
67 compatible = "fsl,mpc8568mds-pib";
72 soc: soc8568@e0000000 {
73 ranges = <0x0 0x0 0xe0000000 0x100000>;
78 compatible = "dallas,ds1374";
80 interrupts = <3 1 0 0>;
85 enet0: ethernet@24000 {
91 phy0: ethernet-phy@7 {
92 interrupts = <1 1 0 0>;
95 phy1: ethernet-phy@1 {
96 interrupts = <2 1 0 0>;
99 phy2: ethernet-phy@2 {
100 interrupts = <1 1 0 0>;
103 phy3: ethernet-phy@3 {
104 interrupts = <2 1 0 0>;
109 device_type = "tbi-phy";
113 enet1: ethernet@25000 {
114 tbi-handle = <&tbi1>;
115 phy-handle = <&phy3>;
116 sleep = <&pmc 0x00000040>;
122 device_type = "tbi-phy";
131 /* port pin dir open_drain assignment has_irq */
132 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
133 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
134 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
135 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
136 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
137 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
138 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
139 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
140 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
141 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
142 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
143 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
144 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
145 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
146 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
147 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
148 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
149 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
150 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
151 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
152 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
153 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
154 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
159 /* port pin dir open_drain assignment has_irq */
160 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
161 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
162 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
163 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
164 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
165 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
166 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
167 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
168 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
169 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
170 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
171 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
172 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
173 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
174 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
175 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
176 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
177 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
178 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
179 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
180 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
181 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
182 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
183 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
184 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
190 ranges = <0x0 0x0 0xe0080000 0x40000>;
191 reg = <0x0 0xe0080000 0x0 0x480>;
202 device_type = "network";
203 compatible = "ucc_geth";
204 local-mac-address = [ 00 00 00 00 00 00 ];
205 rx-clock-name = "none";
206 tx-clock-name = "clk16";
207 pio-handle = <&pio1>;
208 phy-handle = <&phy0>;
209 phy-connection-type = "rgmii-id";
213 device_type = "network";
214 compatible = "ucc_geth";
215 local-mac-address = [ 00 00 00 00 00 00 ];
216 rx-clock-name = "none";
217 tx-clock-name = "clk16";
218 pio-handle = <&pio2>;
219 phy-handle = <&phy1>;
220 phy-connection-type = "rgmii-id";
224 #address-cells = <1>;
227 compatible = "fsl,ucc-mdio";
229 /* These are the same PHYs as on
230 * gianfar's MDIO bus */
231 qe_phy0: ethernet-phy@07 {
232 interrupt-parent = <&mpic>;
233 interrupts = <1 1 0 0>;
236 qe_phy1: ethernet-phy@01 {
237 interrupt-parent = <&mpic>;
238 interrupts = <2 1 0 0>;
241 qe_phy2: ethernet-phy@02 {
242 interrupt-parent = <&mpic>;
243 interrupts = <1 1 0 0>;
246 qe_phy3: ethernet-phy@03 {
247 interrupt-parent = <&mpic>;
248 interrupts = <2 1 0 0>;
255 reg = <0x0 0xe0008000 0x0 0x1000>;
256 ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
257 0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
258 clock-frequency = <66666666>;
259 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
261 /* IDSEL 0x12 AD18 */
262 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
263 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
264 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
265 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
267 /* IDSEL 0x13 AD19 */
268 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
269 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
270 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
271 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
275 pci1: pcie@e000a000 {
276 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
277 0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
278 reg = <0x0 0xe000a000 0x0 0x1000>;
280 ranges = <0x2000000 0x0 0xa0000000
281 0x2000000 0x0 0xa0000000
290 rio: rapidio@e00c00000 {
291 reg = <0x0 0xe00c0000 0x0 0x20000>;
293 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
298 compatible = "gpio-leds";
301 gpios = <&bcsr5 1 0>;
305 gpios = <&bcsr5 2 0>;
309 gpios = <&bcsr5 3 0>;
314 /include/ "fsl/mpc8568si-post.dtsi"