arch/powerpc/include/asm/dma.h

   1 #ifndef _ASM_POWERPC_DMA_H
   2 #define _ASM_POWERPC_DMA_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * Defines for using and allocating dma channels.
   7  * Written by Hennus Bergman, 1992.
   8  * High DMA channel support & info by Hannu Savolainen
   9  * and John Boyd, Nov. 1992.
  10  * Changes for ppc sound by Christoph Nadig
  11  */
  12
  13 /*
  14  * Note: Adapted for PowerPC by Gary Thomas
  15  * Modified by Cort Dougan <cort@cs.nmt.edu>
  16  *
  17  * None of this really applies for Power Macintoshes.  There is
  18  * basically just enough here to get kernel/dma.c to compile.
  19  */
  20
  21 #include <asm/io.h>
  22 #include <linux/spinlock.h>
  23
  24 #ifndef MAX_DMA_CHANNELS
  25 #define MAX_DMA_CHANNELS        8
  26 #endif
  27
  28 /* The maximum address that we can perform a DMA transfer to on this platform */
  29 /* Doesn't really apply... */
  30 #define MAX_DMA_ADDRESS         (~0UL)
  31
  32 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  33 #define dma_outb        outb_p
  34 #else
  35 #define dma_outb        outb
  36 #endif
  37
  38 #define dma_inb         inb
  39
  40 /*
  41  * NOTES about DMA transfers:
  42  *
  43  *  controller 1: channels 0-3, byte operations, ports 00-1F
  44  *  controller 2: channels 4-7, word operations, ports C0-DF
  45  *
  46  *  - ALL registers are 8 bits only, regardless of transfer size
  47  *  - channel 4 is not used - cascades 1 into 2.
  48  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  49  *  - channels 5-7 are word - addresses/counts are for physical words
  50  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  51  *  - transfer count loaded to registers is 1 less than actual count
  52  *  - controller 2 offsets are all even (2x offsets for controller 1)
  53  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  54  *  - page registers for 0-3 use bit 0, represent 64K pages
  55  *
  56  * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
  57  * Note that addresses loaded into registers must be _physical_ addresses,
  58  * not logical addresses (which may differ if paging is active).
  59  *
  60  *  Address mapping for channels 0-3:
  61  *
  62  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  63  *    |  ...  |   |  ... |   |  ... |
  64  *    |  ...  |   |  ... |   |  ... |
  65  *    |  ...  |   |  ... |   |  ... |
  66  *   P7  ...  P0  A7 ... A0  A7 ... A0
  67  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  68  *
  69  *  Address mapping for channels 5-7:
  70  *
  71  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  72  *    |  ...  |   \   \   ... \  \  \  ... \  \
  73  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  74  *    |  ...  |     \   \   ... \  \  \  ... \
  75  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  76  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  77  *
  78  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  79  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  80  * the hardware level, so odd-byte transfers aren't possible).
  81  *
  82  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  83  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  84  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  85  *
  86  */
  87
  88 /* 8237 DMA controllers */
  89 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
  90 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
  91
  92 /* DMA controller registers */
  93 #define DMA1_CMD_REG            0x08    /* command register (w) */
  94 #define DMA1_STAT_REG           0x08    /* status register (r) */
  95 #define DMA1_REQ_REG            0x09    /* request register (w) */
  96 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
  97 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
  98 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
  99 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
 100 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
 101 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
 102 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 103
 104 #define DMA2_CMD_REG            0xD0    /* command register (w) */
 105 #define DMA2_STAT_REG           0xD0    /* status register (r) */
 106 #define DMA2_REQ_REG            0xD2    /* request register (w) */
 107 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 108 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
 109 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 110 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 111 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 112 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 113 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 114
 115 #define DMA_ADDR_0              0x00    /* DMA address registers */
 116 #define DMA_ADDR_1              0x02
 117 #define DMA_ADDR_2              0x04
 118 #define DMA_ADDR_3              0x06
 119 #define DMA_ADDR_4              0xC0
 120 #define DMA_ADDR_5              0xC4
 121 #define DMA_ADDR_6              0xC8
 122 #define DMA_ADDR_7              0xCC
 123
 124 #define DMA_CNT_0               0x01    /* DMA count registers */
 125 #define DMA_CNT_1               0x03
 126 #define DMA_CNT_2               0x05
 127 #define DMA_CNT_3               0x07
 128 #define DMA_CNT_4               0xC2
 129 #define DMA_CNT_5               0xC6
 130 #define DMA_CNT_6               0xCA
 131 #define DMA_CNT_7               0xCE
 132
 133 #define DMA_LO_PAGE_0           0x87    /* DMA page registers */
 134 #define DMA_LO_PAGE_1           0x83
 135 #define DMA_LO_PAGE_2           0x81
 136 #define DMA_LO_PAGE_3           0x82
 137 #define DMA_LO_PAGE_5           0x8B
 138 #define DMA_LO_PAGE_6           0x89
 139 #define DMA_LO_PAGE_7           0x8A
 140
 141 #define DMA_HI_PAGE_0           0x487   /* DMA page registers */
 142 #define DMA_HI_PAGE_1           0x483
 143 #define DMA_HI_PAGE_2           0x481
 144 #define DMA_HI_PAGE_3           0x482
 145 #define DMA_HI_PAGE_5           0x48B
 146 #define DMA_HI_PAGE_6           0x489
 147 #define DMA_HI_PAGE_7           0x48A
 148
 149 #define DMA1_EXT_REG            0x40B
 150 #define DMA2_EXT_REG            0x4D6
 151
 152 #ifndef __powerpc64__
 153     /* in arch/ppc/kernel/setup.c -- Cort */
 154     extern unsigned int DMA_MODE_WRITE;
 155     extern unsigned int DMA_MODE_READ;
 156     extern unsigned long ISA_DMA_THRESHOLD;
 157 #else
 158     #define DMA_MODE_READ       0x44    /* I/O to memory, no autoinit, increment, single mode */
 159     #define DMA_MODE_WRITE      0x48    /* memory to I/O, no autoinit, increment, single mode */
 160 #endif
 161
 162 #define DMA_MODE_CASCADE        0xC0    /* pass thru DREQ->HRQ, DACK<-HLDA only */
 163
 164 #define DMA_AUTOINIT            0x10
 165
 166 extern spinlock_t dma_spin_lock;
 167
 168 static __inline__ unsigned long claim_dma_lock(void)
 169 {
 170         unsigned long flags;
 171         spin_lock_irqsave(&dma_spin_lock, flags);
 172         return flags;
 173 }
 174
 175 static __inline__ void release_dma_lock(unsigned long flags)
 176 {
 177         spin_unlock_irqrestore(&dma_spin_lock, flags);
 178 }
 179
 180 /* enable/disable a specific DMA channel */
 181 static __inline__ void enable_dma(unsigned int dmanr)
 182 {
 183         unsigned char ucDmaCmd = 0x00;
 184
 185         if (dmanr != 4) {
 186                 dma_outb(0, DMA2_MASK_REG);     /* This may not be enabled */
 187                 dma_outb(ucDmaCmd, DMA2_CMD_REG);       /* Enable group */
 188         }
 189         if (dmanr <= 3) {
 190                 dma_outb(dmanr, DMA1_MASK_REG);
 191                 dma_outb(ucDmaCmd, DMA1_CMD_REG);       /* Enable group */
 192         } else {
 193                 dma_outb(dmanr & 3, DMA2_MASK_REG);
 194         }
 195 }
 196
 197 static __inline__ void disable_dma(unsigned int dmanr)
 198 {
 199         if (dmanr <= 3)
 200                 dma_outb(dmanr | 4, DMA1_MASK_REG);
 201         else
 202                 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
 203 }
 204
 205 /* Clear the 'DMA Pointer Flip Flop'.
 206  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 207  * Use this once to initialize the FF to a known state.
 208  * After that, keep track of it. :-)
 209  * --- In order to do that, the DMA routines below should ---
 210  * --- only be used while interrupts are disabled! ---
 211  */
 212 static __inline__ void clear_dma_ff(unsigned int dmanr)
 213 {
 214         if (dmanr <= 3)
 215                 dma_outb(0, DMA1_CLEAR_FF_REG);
 216         else
 217                 dma_outb(0, DMA2_CLEAR_FF_REG);
 218 }
 219
 220 /* set mode (above) for a specific DMA channel */
 221 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 222 {
 223         if (dmanr <= 3)
 224                 dma_outb(mode | dmanr, DMA1_MODE_REG);
 225         else
 226                 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
 227 }
 228
 229 /* Set only the page register bits of the transfer address.
 230  * This is used for successive transfers when we know the contents of
 231  * the lower 16 bits of the DMA current address register, but a 64k boundary
 232  * may have been crossed.
 233  */
 234 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
 235 {
 236         switch (dmanr) {
 237         case 0:
 238                 dma_outb(pagenr, DMA_LO_PAGE_0);
 239                 dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
 240                 break;
 241         case 1:
 242                 dma_outb(pagenr, DMA_LO_PAGE_1);
 243                 dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
 244                 break;
 245         case 2:
 246                 dma_outb(pagenr, DMA_LO_PAGE_2);
 247                 dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
 248                 break;
 249         case 3:
 250                 dma_outb(pagenr, DMA_LO_PAGE_3);
 251                 dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
 252                 break;
 253         case 5:
 254                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
 255                 dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
 256                 break;
 257         case 6:
 258                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
 259                 dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
 260                 break;
 261         case 7:
 262                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
 263                 dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
 264                 break;
 265         }
 266 }
 267
 268 /* Set transfer address & page bits for specific DMA channel.
 269  * Assumes dma flipflop is clear.
 270  */
 271 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
 272 {
 273         if (dmanr <= 3) {
 274                 dma_outb(phys & 0xff,
 275                          ((dmanr & 3) << 1) + IO_DMA1_BASE);
 276                 dma_outb((phys >> 8) & 0xff,
 277                          ((dmanr & 3) << 1) + IO_DMA1_BASE);
 278         } else {
 279                 dma_outb((phys >> 1) & 0xff,
 280                          ((dmanr & 3) << 2) + IO_DMA2_BASE);
 281                 dma_outb((phys >> 9) & 0xff,
 282                          ((dmanr & 3) << 2) + IO_DMA2_BASE);
 283         }
 284         set_dma_page(dmanr, phys >> 16);
 285 }
 286
 287
 288 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 289  * a specific DMA channel.
 290  * You must ensure the parameters are valid.
 291  * NOTE: from a manual: "the number of transfers is one more
 292  * than the initial word count"! This is taken into account.
 293  * Assumes dma flip-flop is clear.
 294  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 295  */
 296 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 297 {
 298         count--;
 299         if (dmanr <= 3) {
 300                 dma_outb(count & 0xff,
 301                          ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
 302                 dma_outb((count >> 8) & 0xff,
 303                          ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
 304         } else {
 305                 dma_outb((count >> 1) & 0xff,
 306                          ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
 307                 dma_outb((count >> 9) & 0xff,
 308                          ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
 309         }
 310 }
 311
 312
 313 /* Get DMA residue count. After a DMA transfer, this
 314  * should return zero. Reading this while a DMA transfer is
 315  * still in progress will return unpredictable results.
 316  * If called before the channel has been used, it may return 1.
 317  * Otherwise, it returns the number of _bytes_ left to transfer.
 318  *
 319  * Assumes DMA flip-flop is clear.
 320  */
 321 static __inline__ int get_dma_residue(unsigned int dmanr)
 322 {
 323         unsigned int io_port = (dmanr <= 3)
 324             ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
 325             : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
 326
 327         /* using short to get 16-bit wrap around */
 328         unsigned short count;
 329
 330         count = 1 + dma_inb(io_port);
 331         count += dma_inb(io_port) << 8;
 332
 333         return (dmanr <= 3) ? count : (count << 1);
 334 }
 335
 336 /* These are in kernel/dma.c: */
 337
 338 /* reserve a DMA channel */
 339 extern int request_dma(unsigned int dmanr, const char *device_id);
 340 /* release it again */
 341 extern void free_dma(unsigned int dmanr);
 342
 343 #ifdef CONFIG_PCI
 344 extern int isa_dma_bridge_buggy;
 345 #else
 346 #define isa_dma_bridge_buggy    (0)
 347 #endif
 348
 349 #endif /* __KERNEL__ */
 350 #endif  /* _ASM_POWERPC_DMA_H */