| blob | 879f09620f8341e27dbfd1ed6be47fe242eab812 |
1 /*
2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * and Paul Mackerras.
7 *
8 * kexec bits:
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
11 * PPC44x port. Copyright (C) 2011, IBM Corporation
12 * Author: Suzuki Poulose <suzuki@in.ibm.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 *
19 */
21 #include <linux/sys.h>
22 #include <asm/unistd.h>
23 #include <asm/errno.h>
24 #include <asm/reg.h>
25 #include <asm/page.h>
26 #include <asm/cache.h>
27 #include <asm/cputable.h>
28 #include <asm/mmu.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/thread_info.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/processor.h>
33 #include <asm/kexec.h>
34 #include <asm/bug.h>
35 #include <asm/ptrace.h>
37 .text
39 /*
40 * We store the saved ksp_limit in the unused part
41 * of the STACK_FRAME_OVERHEAD
42 */
43 _GLOBAL(call_do_softirq)
44 mflr r0
45 stw r0,4(r1)
46 lwz r10,THREAD+KSP_LIMIT(r2)
47 addi r11,r3,THREAD_INFO_GAP
48 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
49 mr r1,r3
50 stw r10,8(r1)
51 stw r11,THREAD+KSP_LIMIT(r2)
52 bl __do_softirq
53 lwz r10,8(r1)
54 lwz r1,0(r1)
55 lwz r0,4(r1)
56 stw r10,THREAD+KSP_LIMIT(r2)
57 mtlr r0
58 blr
60 _GLOBAL(call_do_irq)
61 mflr r0
62 stw r0,4(r1)
63 lwz r10,THREAD+KSP_LIMIT(r2)
64 addi r11,r3,THREAD_INFO_GAP
65 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
66 mr r1,r4
67 stw r10,8(r1)
68 stw r11,THREAD+KSP_LIMIT(r2)
69 bl __do_irq
70 lwz r10,8(r1)
71 lwz r1,0(r1)
72 lwz r0,4(r1)
73 stw r10,THREAD+KSP_LIMIT(r2)
74 mtlr r0
75 blr
77 /*
78 * This returns the high 64 bits of the product of two 64-bit numbers.
79 */
80 _GLOBAL(mulhdu)
81 cmpwi r6,0
82 cmpwi cr1,r3,0
83 mr r10,r4
84 mulhwu r4,r4,r5
85 beq 1f
86 mulhwu r0,r10,r6
87 mullw r7,r10,r5
88 addc r7,r0,r7
89 addze r4,r4
90 1: beqlr cr1 /* all done if high part of A is 0 */
91 mr r10,r3
92 mullw r9,r3,r5
93 mulhwu r3,r3,r5
94 beq 2f
95 mullw r0,r10,r6
96 mulhwu r8,r10,r6
97 addc r7,r0,r7
98 adde r4,r4,r8
99 addze r3,r3
100 2: addc r4,r4,r9
101 addze r3,r3
102 blr
104 /*
105 * sub_reloc_offset(x) returns x - reloc_offset().
106 */
107 _GLOBAL(sub_reloc_offset)
108 mflr r0
109 bl 1f
110 1: mflr r5
111 lis r4,1b@ha
112 addi r4,r4,1b@l
113 subf r5,r4,r5
114 subf r3,r5,r3
115 mtlr r0
116 blr
118 /*
119 * reloc_got2 runs through the .got2 section adding an offset
120 * to each entry.
121 */
122 _GLOBAL(reloc_got2)
123 mflr r11
124 lis r7,__got2_start@ha
125 addi r7,r7,__got2_start@l
126 lis r8,__got2_end@ha
127 addi r8,r8,__got2_end@l
128 subf r8,r7,r8
129 srwi. r8,r8,2
130 beqlr
131 mtctr r8
132 bl 1f
133 1: mflr r0
134 lis r4,1b@ha
135 addi r4,r4,1b@l
136 subf r0,r4,r0
137 add r7,r0,r7
138 2: lwz r0,0(r7)
139 add r0,r0,r3
140 stw r0,0(r7)
141 addi r7,r7,4
142 bdnz 2b
143 mtlr r11
144 blr
146 /*
147 * call_setup_cpu - call the setup_cpu function for this cpu
148 * r3 = data offset, r24 = cpu number
149 *
150 * Setup function is called with:
151 * r3 = data offset
152 * r4 = ptr to CPU spec (relocated)
153 */
154 _GLOBAL(call_setup_cpu)
155 addis r4,r3,cur_cpu_spec@ha
156 addi r4,r4,cur_cpu_spec@l
157 lwz r4,0(r4)
158 add r4,r4,r3
159 lwz r5,CPU_SPEC_SETUP(r4)
160 cmpwi 0,r5,0
161 add r5,r5,r3
162 beqlr
163 mtctr r5
164 bctr
166 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
168 /* This gets called by via-pmu.c to switch the PLL selection
169 * on 750fx CPU. This function should really be moved to some
170 * other place (as most of the cpufreq code in via-pmu
171 */
172 _GLOBAL(low_choose_750fx_pll)
173 /* Clear MSR:EE */
174 mfmsr r7
175 rlwinm r0,r7,0,17,15
176 mtmsr r0
178 /* If switching to PLL1, disable HID0:BTIC */
179 cmplwi cr0,r3,0
180 beq 1f
181 mfspr r5,SPRN_HID0
182 rlwinm r5,r5,0,27,25
183 sync
184 mtspr SPRN_HID0,r5
185 isync
186 sync
188 1:
189 /* Calc new HID1 value */
190 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
191 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
192 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
193 or r4,r4,r5
194 mtspr SPRN_HID1,r4
196 /* Store new HID1 image */
197 CURRENT_THREAD_INFO(r6, r1)
198 lwz r6,TI_CPU(r6)
199 slwi r6,r6,2
200 addis r6,r6,nap_save_hid1@ha
201 stw r4,nap_save_hid1@l(r6)
203 /* If switching to PLL0, enable HID0:BTIC */
204 cmplwi cr0,r3,0
205 bne 1f
206 mfspr r5,SPRN_HID0
207 ori r5,r5,HID0_BTIC
208 sync
209 mtspr SPRN_HID0,r5
210 isync
211 sync
213 1:
214 /* Return */
215 mtmsr r7
216 blr
218 _GLOBAL(low_choose_7447a_dfs)
219 /* Clear MSR:EE */
220 mfmsr r7
221 rlwinm r0,r7,0,17,15
222 mtmsr r0
224 /* Calc new HID1 value */
225 mfspr r4,SPRN_HID1
226 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
227 sync
228 mtspr SPRN_HID1,r4
229 sync
230 isync
232 /* Return */
233 mtmsr r7
234 blr
236 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
238 /*
239 * complement mask on the msr then "or" some values on.
240 * _nmask_and_or_msr(nmask, value_to_or)
241 */
242 _GLOBAL(_nmask_and_or_msr)
243 mfmsr r0 /* Get current msr */
244 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
245 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
246 SYNC /* Some chip revs have problems here... */
247 mtmsr r0 /* Update machine state */
248 isync
249 blr /* Done */
251 #ifdef CONFIG_40x
253 /*
254 * Do an IO access in real mode
255 */
256 _GLOBAL(real_readb)
257 mfmsr r7
258 ori r0,r7,MSR_DR
259 xori r0,r0,MSR_DR
260 sync
261 mtmsr r0
262 sync
263 isync
264 lbz r3,0(r3)
265 sync
266 mtmsr r7
267 sync
268 isync
269 blr
271 /*
272 * Do an IO access in real mode
273 */
274 _GLOBAL(real_writeb)
275 mfmsr r7
276 ori r0,r7,MSR_DR
277 xori r0,r0,MSR_DR
278 sync
279 mtmsr r0
280 sync
281 isync
282 stb r3,0(r4)
283 sync
284 mtmsr r7
285 sync
286 isync
287 blr
289 #endif /* CONFIG_40x */
292 /*
293 * Flush instruction cache.
294 * This is a no-op on the 601.
295 */
296 _GLOBAL(flush_instruction_cache)
297 #if defined(CONFIG_8xx)
298 isync
299 lis r5, IDC_INVALL@h
300 mtspr SPRN_IC_CST, r5
301 #elif defined(CONFIG_4xx)
302 #ifdef CONFIG_403GCX
303 li r3, 512
304 mtctr r3
305 lis r4, KERNELBASE@h
306 1: iccci 0, r4
307 addi r4, r4, 16
308 bdnz 1b
309 #else
310 lis r3, KERNELBASE@h
311 iccci 0,r3
312 #endif
313 #elif CONFIG_FSL_BOOKE
314 BEGIN_FTR_SECTION
315 mfspr r3,SPRN_L1CSR0
316 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
317 /* msync; isync recommended here */
318 mtspr SPRN_L1CSR0,r3
319 isync
320 blr
321 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
322 mfspr r3,SPRN_L1CSR1
323 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
324 mtspr SPRN_L1CSR1,r3
325 #else
326 mfspr r3,SPRN_PVR
327 rlwinm r3,r3,16,16,31
328 cmpwi 0,r3,1
329 beqlr /* for 601, do nothing */
330 /* 603/604 processor - use invalidate-all bit in HID0 */
331 mfspr r3,SPRN_HID0
332 ori r3,r3,HID0_ICFI
333 mtspr SPRN_HID0,r3
334 #endif /* CONFIG_8xx/4xx */
335 isync
336 blr
338 /*
339 * Write any modified data cache blocks out to memory
340 * and invalidate the corresponding instruction cache blocks.
341 * This is a no-op on the 601.
342 *
343 * flush_icache_range(unsigned long start, unsigned long stop)
344 */
345 _KPROBE(flush_icache_range)
346 BEGIN_FTR_SECTION
347 PURGE_PREFETCHED_INS
348 blr /* for 601, do nothing */
349 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
350 li r5,L1_CACHE_BYTES-1
351 andc r3,r3,r5
352 subf r4,r3,r4
353 add r4,r4,r5
354 srwi. r4,r4,L1_CACHE_SHIFT
355 beqlr
356 mtctr r4
357 mr r6,r3
358 1: dcbst 0,r3
359 addi r3,r3,L1_CACHE_BYTES
360 bdnz 1b
361 sync /* wait for dcbst's to get to ram */
362 #ifndef CONFIG_44x
363 mtctr r4
364 2: icbi 0,r6
365 addi r6,r6,L1_CACHE_BYTES
366 bdnz 2b
367 #else
368 /* Flash invalidate on 44x because we are passed kmapped addresses and
369 this doesn't work for userspace pages due to the virtually tagged
370 icache. Sigh. */
371 iccci 0, r0
372 #endif
373 sync /* additional sync needed on g4 */
374 isync
375 blr
376 /*
377 * Write any modified data cache blocks out to memory.
378 * Does not invalidate the corresponding cache lines (especially for
379 * any corresponding instruction cache).
380 *
381 * clean_dcache_range(unsigned long start, unsigned long stop)
382 */
383 _GLOBAL(clean_dcache_range)
384 li r5,L1_CACHE_BYTES-1
385 andc r3,r3,r5
386 subf r4,r3,r4
387 add r4,r4,r5
388 srwi. r4,r4,L1_CACHE_SHIFT
389 beqlr
390 mtctr r4
392 1: dcbst 0,r3
393 addi r3,r3,L1_CACHE_BYTES
394 bdnz 1b
395 sync /* wait for dcbst's to get to ram */
396 blr
398 /*
399 * Write any modified data cache blocks out to memory and invalidate them.
400 * Does not invalidate the corresponding instruction cache blocks.
401 *
402 * flush_dcache_range(unsigned long start, unsigned long stop)
403 */
404 _GLOBAL(flush_dcache_range)
405 li r5,L1_CACHE_BYTES-1
406 andc r3,r3,r5
407 subf r4,r3,r4
408 add r4,r4,r5
409 srwi. r4,r4,L1_CACHE_SHIFT
410 beqlr
411 mtctr r4
413 1: dcbf 0,r3
414 addi r3,r3,L1_CACHE_BYTES
415 bdnz 1b
416 sync /* wait for dcbst's to get to ram */
417 blr
419 /*
420 * Like above, but invalidate the D-cache. This is used by the 8xx
421 * to invalidate the cache so the PPC core doesn't get stale data
422 * from the CPM (no cache snooping here :-).
423 *
424 * invalidate_dcache_range(unsigned long start, unsigned long stop)
425 */
426 _GLOBAL(invalidate_dcache_range)
427 li r5,L1_CACHE_BYTES-1
428 andc r3,r3,r5
429 subf r4,r3,r4
430 add r4,r4,r5
431 srwi. r4,r4,L1_CACHE_SHIFT
432 beqlr
433 mtctr r4
435 1: dcbi 0,r3
436 addi r3,r3,L1_CACHE_BYTES
437 bdnz 1b
438 sync /* wait for dcbi's to get to ram */
439 blr
441 /*
442 * Flush a particular page from the data cache to RAM.
443 * Note: this is necessary because the instruction cache does *not*
444 * snoop from the data cache.
445 * This is a no-op on the 601 which has a unified cache.
446 *
447 * void __flush_dcache_icache(void *page)
448 */
449 _GLOBAL(__flush_dcache_icache)
450 BEGIN_FTR_SECTION
451 PURGE_PREFETCHED_INS
452 blr
453 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
454 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
455 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
456 mtctr r4
457 mr r6,r3
458 0: dcbst 0,r3 /* Write line to ram */
459 addi r3,r3,L1_CACHE_BYTES
460 bdnz 0b
461 sync
462 #ifdef CONFIG_44x
463 /* We don't flush the icache on 44x. Those have a virtual icache
464 * and we don't have access to the virtual address here (it's
465 * not the page vaddr but where it's mapped in user space). The
466 * flushing of the icache on these is handled elsewhere, when
467 * a change in the address space occurs, before returning to
468 * user space
469 */
470 BEGIN_MMU_FTR_SECTION
471 blr
472 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
473 #endif /* CONFIG_44x */
474 mtctr r4
475 1: icbi 0,r6
476 addi r6,r6,L1_CACHE_BYTES
477 bdnz 1b
478 sync
479 isync
480 blr
482 #ifndef CONFIG_BOOKE
483 /*
484 * Flush a particular page from the data cache to RAM, identified
485 * by its physical address. We turn off the MMU so we can just use
486 * the physical address (this may be a highmem page without a kernel
487 * mapping).
488 *
489 * void __flush_dcache_icache_phys(unsigned long physaddr)
490 */
491 _GLOBAL(__flush_dcache_icache_phys)
492 BEGIN_FTR_SECTION
493 PURGE_PREFETCHED_INS
494 blr /* for 601, do nothing */
495 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
496 mfmsr r10
497 rlwinm r0,r10,0,28,26 /* clear DR */
498 mtmsr r0
499 isync
500 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
501 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
502 mtctr r4
503 mr r6,r3
504 0: dcbst 0,r3 /* Write line to ram */
505 addi r3,r3,L1_CACHE_BYTES
506 bdnz 0b
507 sync
508 mtctr r4
509 1: icbi 0,r6
510 addi r6,r6,L1_CACHE_BYTES
511 bdnz 1b
512 sync
513 mtmsr r10 /* restore DR */
514 isync
515 blr
516 #endif /* CONFIG_BOOKE */
518 /*
519 * Clear pages using the dcbz instruction, which doesn't cause any
520 * memory traffic (except to write out any cache lines which get
521 * displaced). This only works on cacheable memory.
522 *
523 * void clear_pages(void *page, int order) ;
524 */
525 _GLOBAL(clear_pages)
526 li r0,PAGE_SIZE/L1_CACHE_BYTES
527 slw r0,r0,r4
528 mtctr r0
529 1: dcbz 0,r3
530 addi r3,r3,L1_CACHE_BYTES
531 bdnz 1b
532 blr
534 /*
535 * Copy a whole page. We use the dcbz instruction on the destination
536 * to reduce memory traffic (it eliminates the unnecessary reads of
537 * the destination into cache). This requires that the destination
538 * is cacheable.
539 */
540 #define COPY_16_BYTES \
541 lwz r6,4(r4); \
542 lwz r7,8(r4); \
543 lwz r8,12(r4); \
544 lwzu r9,16(r4); \
545 stw r6,4(r3); \
546 stw r7,8(r3); \
547 stw r8,12(r3); \
548 stwu r9,16(r3)
550 _GLOBAL(copy_page)
551 addi r3,r3,-4
552 addi r4,r4,-4
554 li r5,4
556 #if MAX_COPY_PREFETCH > 1
557 li r0,MAX_COPY_PREFETCH
558 li r11,4
559 mtctr r0
560 11: dcbt r11,r4
561 addi r11,r11,L1_CACHE_BYTES
562 bdnz 11b
563 #else /* MAX_COPY_PREFETCH == 1 */
564 dcbt r5,r4
565 li r11,L1_CACHE_BYTES+4
566 #endif /* MAX_COPY_PREFETCH */
567 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
568 crclr 4*cr0+eq
569 2:
570 mtctr r0
571 1:
572 dcbt r11,r4
573 dcbz r5,r3
574 COPY_16_BYTES
575 #if L1_CACHE_BYTES >= 32
576 COPY_16_BYTES
577 #if L1_CACHE_BYTES >= 64
578 COPY_16_BYTES
579 COPY_16_BYTES
580 #if L1_CACHE_BYTES >= 128
581 COPY_16_BYTES
582 COPY_16_BYTES
583 COPY_16_BYTES
584 COPY_16_BYTES
585 #endif
586 #endif
587 #endif
588 bdnz 1b
589 beqlr
590 crnot 4*cr0+eq,4*cr0+eq
591 li r0,MAX_COPY_PREFETCH
592 li r11,4
593 b 2b
595 /*
596 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
597 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
598 */
599 _GLOBAL(atomic_clear_mask)
600 10: lwarx r5,0,r4
601 andc r5,r5,r3
602 PPC405_ERR77(0,r4)
603 stwcx. r5,0,r4
604 bne- 10b
605 blr
606 _GLOBAL(atomic_set_mask)
607 10: lwarx r5,0,r4
608 or r5,r5,r3
609 PPC405_ERR77(0,r4)
610 stwcx. r5,0,r4
611 bne- 10b
612 blr
614 /*
615 * Extended precision shifts.
616 *
617 * Updated to be valid for shift counts from 0 to 63 inclusive.
618 * -- Gabriel
619 *
620 * R3/R4 has 64 bit value
621 * R5 has shift count
622 * result in R3/R4
623 *
624 * ashrdi3: arithmetic right shift (sign propagation)
625 * lshrdi3: logical right shift
626 * ashldi3: left shift
627 */
628 _GLOBAL(__ashrdi3)
629 subfic r6,r5,32
630 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
631 addi r7,r5,32 # could be xori, or addi with -32
632 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
633 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
634 sraw r7,r3,r7 # t2 = MSW >> (count-32)
635 or r4,r4,r6 # LSW |= t1
636 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
637 sraw r3,r3,r5 # MSW = MSW >> count
638 or r4,r4,r7 # LSW |= t2
639 blr
641 _GLOBAL(__ashldi3)
642 subfic r6,r5,32
643 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
644 addi r7,r5,32 # could be xori, or addi with -32
645 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
646 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
647 or r3,r3,r6 # MSW |= t1
648 slw r4,r4,r5 # LSW = LSW << count
649 or r3,r3,r7 # MSW |= t2
650 blr
652 _GLOBAL(__lshrdi3)
653 subfic r6,r5,32
654 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
655 addi r7,r5,32 # could be xori, or addi with -32
656 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
657 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
658 or r4,r4,r6 # LSW |= t1
659 srw r3,r3,r5 # MSW = MSW >> count
660 or r4,r4,r7 # LSW |= t2
661 blr
663 /*
664 * 64-bit comparison: __cmpdi2(s64 a, s64 b)
665 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
666 */
667 _GLOBAL(__cmpdi2)
668 cmpw r3,r5
669 li r3,1
670 bne 1f
671 cmplw r4,r6
672 beqlr
673 1: li r3,0
674 bltlr
675 li r3,2
676 blr
677 /*
678 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
679 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
680 */
681 _GLOBAL(__ucmpdi2)
682 cmplw r3,r5
683 li r3,1
684 bne 1f
685 cmplw r4,r6
686 beqlr
687 1: li r3,0
688 bltlr
689 li r3,2
690 blr
692 _GLOBAL(__bswapdi2)
693 rotlwi r9,r4,8
694 rotlwi r10,r3,8
695 rlwimi r9,r4,24,0,7
696 rlwimi r10,r3,24,0,7
697 rlwimi r9,r4,24,16,23
698 rlwimi r10,r3,24,16,23
699 mr r3,r9
700 mr r4,r10
701 blr
703 _GLOBAL(abs)
704 srawi r4,r3,31
705 xor r3,r3,r4
706 sub r3,r3,r4
707 blr
709 #ifdef CONFIG_SMP
710 _GLOBAL(start_secondary_resume)
711 /* Reset stack */
712 CURRENT_THREAD_INFO(r1, r1)
713 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
714 li r3,0
715 stw r3,0(r1) /* Zero the stack frame pointer */
716 bl start_secondary
717 b .
718 #endif /* CONFIG_SMP */
720 /*
721 * This routine is just here to keep GCC happy - sigh...
722 */
723 _GLOBAL(__main)
724 blr
726 #ifdef CONFIG_KEXEC
727 /*
728 * Must be relocatable PIC code callable as a C function.
729 */
730 .globl relocate_new_kernel
731 relocate_new_kernel:
732 /* r3 = page_list */
733 /* r4 = reboot_code_buffer */
734 /* r5 = start_address */
736 #ifdef CONFIG_FSL_BOOKE
738 mr r29, r3
739 mr r30, r4
740 mr r31, r5
742 #define ENTRY_MAPPING_KEXEC_SETUP
743 #include "fsl_booke_entry_mapping.S"
744 #undef ENTRY_MAPPING_KEXEC_SETUP
746 mr r3, r29
747 mr r4, r30
748 mr r5, r31
750 li r0, 0
751 #elif defined(CONFIG_44x)
753 /* Save our parameters */
754 mr r29, r3
755 mr r30, r4
756 mr r31, r5
758 #ifdef CONFIG_PPC_47x
759 /* Check for 47x cores */
760 mfspr r3,SPRN_PVR
761 srwi r3,r3,16
762 cmplwi cr0,r3,PVR_476@h
763 beq setup_map_47x
764 cmplwi cr0,r3,PVR_476_ISS@h
765 beq setup_map_47x
766 #endif /* CONFIG_PPC_47x */
768 /*
769 * Code for setting up 1:1 mapping for PPC440x for KEXEC
770 *
771 * We cannot switch off the MMU on PPC44x.
772 * So we:
773 * 1) Invalidate all the mappings except the one we are running from.
774 * 2) Create a tmp mapping for our code in the other address space(TS) and
775 * jump to it. Invalidate the entry we started in.
776 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
777 * 4) Jump to the 1:1 mapping in original TS.
778 * 5) Invalidate the tmp mapping.
779 *
780 * - Based on the kexec support code for FSL BookE
781 *
782 */
784 /*
785 * Load the PID with kernel PID (0).
786 * Also load our MSR_IS and TID to MMUCR for TLB search.
787 */
788 li r3, 0
789 mtspr SPRN_PID, r3
790 mfmsr r4
791 andi. r4,r4,MSR_IS@l
792 beq wmmucr
793 oris r3,r3,PPC44x_MMUCR_STS@h
794 wmmucr:
795 mtspr SPRN_MMUCR,r3
796 sync
798 /*
799 * Invalidate all the TLB entries except the current entry
800 * where we are running from
801 */
802 bl 0f /* Find our address */
803 0: mflr r5 /* Make it accessible */
804 tlbsx r23,0,r5 /* Find entry we are in */
805 li r4,0 /* Start at TLB entry 0 */
806 li r3,0 /* Set PAGEID inval value */
807 1: cmpw r23,r4 /* Is this our entry? */
808 beq skip /* If so, skip the inval */
809 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
810 skip:
811 addi r4,r4,1 /* Increment */
812 cmpwi r4,64 /* Are we done? */
813 bne 1b /* If not, repeat */
814 isync
816 /* Create a temp mapping and jump to it */
817 andi. r6, r23, 1 /* Find the index to use */
818 addi r24, r6, 1 /* r24 will contain 1 or 2 */
820 mfmsr r9 /* get the MSR */
821 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
822 xori r7, r5, 1 /* Use the other address space */
824 /* Read the current mapping entries */
825 tlbre r3, r23, PPC44x_TLB_PAGEID
826 tlbre r4, r23, PPC44x_TLB_XLAT
827 tlbre r5, r23, PPC44x_TLB_ATTRIB
829 /* Save our current XLAT entry */
830 mr r25, r4
832 /* Extract the TLB PageSize */
833 li r10, 1 /* r10 will hold PageSize */
834 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
836 /* XXX: As of now we use 256M, 4K pages */
837 cmpwi r11, PPC44x_TLB_256M
838 bne tlb_4k
839 rotlwi r10, r10, 28 /* r10 = 256M */
840 b write_out
841 tlb_4k:
842 cmpwi r11, PPC44x_TLB_4K
843 bne default
844 rotlwi r10, r10, 12 /* r10 = 4K */
845 b write_out
846 default:
847 rotlwi r10, r10, 10 /* r10 = 1K */
849 write_out:
850 /*
851 * Write out the tmp 1:1 mapping for this code in other address space
852 * Fixup EPN = RPN , TS=other address space
853 */
854 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
856 /* Write out the tmp mapping entries */
857 tlbwe r3, r24, PPC44x_TLB_PAGEID
858 tlbwe r4, r24, PPC44x_TLB_XLAT
859 tlbwe r5, r24, PPC44x_TLB_ATTRIB
861 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
862 not r10, r11 /* Mask for PageNum */
864 /* Switch to other address space in MSR */
865 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
867 bl 1f
868 1: mflr r8
869 addi r8, r8, (2f-1b) /* Find the target offset */
871 /* Jump to the tmp mapping */
872 mtspr SPRN_SRR0, r8
873 mtspr SPRN_SRR1, r9
874 rfi
876 2:
877 /* Invalidate the entry we were executing from */
878 li r3, 0
879 tlbwe r3, r23, PPC44x_TLB_PAGEID
881 /* attribute fields. rwx for SUPERVISOR mode */
882 li r5, 0
883 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
885 /* Create 1:1 mapping in 256M pages */
886 xori r7, r7, 1 /* Revert back to Original TS */
888 li r8, 0 /* PageNumber */
889 li r6, 3 /* TLB Index, start at 3 */
891 next_tlb:
892 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
893 mr r4, r3 /* RPN = EPN */
894 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
895 insrwi r3, r7, 1, 23 /* Set TS from r7 */
897 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
898 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
899 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
901 addi r8, r8, 1 /* Increment PN */
902 addi r6, r6, 1 /* Increment TLB Index */
903 cmpwi r8, 8 /* Are we done ? */
904 bne next_tlb
905 isync
907 /* Jump to the new mapping 1:1 */
908 li r9,0
909 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
911 bl 1f
912 1: mflr r8
913 and r8, r8, r11 /* Get our offset within page */
914 addi r8, r8, (2f-1b)
916 and r5, r25, r10 /* Get our target PageNum */
917 or r8, r8, r5 /* Target jump address */
919 mtspr SPRN_SRR0, r8
920 mtspr SPRN_SRR1, r9
921 rfi
922 2:
923 /* Invalidate the tmp entry we used */
924 li r3, 0
925 tlbwe r3, r24, PPC44x_TLB_PAGEID
926 sync
927 b ppc44x_map_done
929 #ifdef CONFIG_PPC_47x
931 /* 1:1 mapping for 47x */
933 setup_map_47x:
935 /*
936 * Load the kernel pid (0) to PID and also to MMUCR[TID].
937 * Also set the MSR IS->MMUCR STS
938 */
939 li r3, 0
940 mtspr SPRN_PID, r3 /* Set PID */
941 mfmsr r4 /* Get MSR */
942 andi. r4, r4, MSR_IS@l /* TS=1? */
943 beq 1f /* If not, leave STS=0 */
944 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
945 1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
946 sync
948 /* Find the entry we are running from */
949 bl 2f
950 2: mflr r23
951 tlbsx r23, 0, r23
952 tlbre r24, r23, 0 /* TLB Word 0 */
953 tlbre r25, r23, 1 /* TLB Word 1 */
954 tlbre r26, r23, 2 /* TLB Word 2 */
957 /*
958 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
959 * of 4k page size in all 4 ways (0-3 in r3).
960 * This would invalidate the entire UTLB including the one we are
961 * running from. However the shadow TLB entries would help us
962 * to continue the execution, until we flush them (rfi/isync).
963 */
964 addis r3, 0, 0x8000 /* specify the way */
965 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
966 addi r5, 0, 0
967 b clear_utlb_entry
969 /* Align the loop to speed things up. from head_44x.S */
970 .align 6
972 clear_utlb_entry:
974 tlbwe r4, r3, 0
975 tlbwe r5, r3, 1
976 tlbwe r5, r3, 2
977 addis r3, r3, 0x2000 /* Increment the way */
978 cmpwi r3, 0
979 bne clear_utlb_entry
980 addis r3, 0, 0x8000
981 addis r4, r4, 0x100 /* Increment the EPN */
982 cmpwi r4, 0
983 bne clear_utlb_entry
985 /* Create the entries in the other address space */
986 mfmsr r5
987 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
988 xori r7, r7, 1 /* r7 = !TS */
990 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
992 /*
993 * write out the TLB entries for the tmp mapping
994 * Use way '0' so that we could easily invalidate it later.
995 */
996 lis r3, 0x8000 /* Way '0' */
998 tlbwe r24, r3, 0
999 tlbwe r25, r3, 1
1000 tlbwe r26, r3, 2
1002 /* Update the msr to the new TS */
1003 insrwi r5, r7, 1, 26
1005 bl 1f
1006 1: mflr r6
1007 addi r6, r6, (2f-1b)
1009 mtspr SPRN_SRR0, r6
1010 mtspr SPRN_SRR1, r5
1011 rfi
1013 /*
1014 * Now we are in the tmp address space.
1015 * Create a 1:1 mapping for 0-2GiB in the original TS.
1016 */
1017 2:
1018 li r3, 0
1019 li r4, 0 /* TLB Word 0 */
1020 li r5, 0 /* TLB Word 1 */
1021 li r6, 0
1022 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
1024 li r8, 0 /* PageIndex */
1026 xori r7, r7, 1 /* revert back to original TS */
1028 write_utlb:
1029 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
1030 /* ERPN = 0 as we don't use memory above 2G */
1032 mr r4, r5 /* EPN = RPN */
1033 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
1034 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
1036 tlbwe r4, r3, 0 /* Write out the entries */
1037 tlbwe r5, r3, 1
1038 tlbwe r6, r3, 2
1039 addi r8, r8, 1
1040 cmpwi r8, 8 /* Have we completed ? */
1041 bne write_utlb
1043 /* make sure we complete the TLB write up */
1044 isync
1046 /*
1047 * Prepare to jump to the 1:1 mapping.
1048 * 1) Extract page size of the tmp mapping
1049 * DSIZ = TLB_Word0[22:27]
1050 * 2) Calculate the physical address of the address
1051 * to jump to.
1052 */
1053 rlwinm r10, r24, 0, 22, 27
1055 cmpwi r10, PPC47x_TLB0_4K
1056 bne 0f
1057 li r10, 0x1000 /* r10 = 4k */
1058 bl 1f
1060 0:
1061 /* Defaults to 256M */
1062 lis r10, 0x1000
1064 bl 1f
1065 1: mflr r4
1066 addi r4, r4, (2f-1b) /* virtual address of 2f */
1068 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
1069 not r10, r11 /* Pagemask = ~(offsetmask) */
1071 and r5, r25, r10 /* Physical page */
1072 and r6, r4, r11 /* offset within the current page */
1074 or r5, r5, r6 /* Physical address for 2f */
1076 /* Switch the TS in MSR to the original one */
1077 mfmsr r8
1078 insrwi r8, r7, 1, 26
1080 mtspr SPRN_SRR1, r8
1081 mtspr SPRN_SRR0, r5
1082 rfi
1084 2:
1085 /* Invalidate the tmp mapping */
1086 lis r3, 0x8000 /* Way '0' */
1088 clrrwi r24, r24, 12 /* Clear the valid bit */
1089 tlbwe r24, r3, 0
1090 tlbwe r25, r3, 1
1091 tlbwe r26, r3, 2
1093 /* Make sure we complete the TLB write and flush the shadow TLB */
1094 isync
1096 #endif
1098 ppc44x_map_done:
1101 /* Restore the parameters */
1102 mr r3, r29
1103 mr r4, r30
1104 mr r5, r31
1106 li r0, 0
1107 #else
1108 li r0, 0
1110 /*
1111 * Set Machine Status Register to a known status,
1112 * switch the MMU off and jump to 1: in a single step.
1113 */
1115 mr r8, r0
1116 ori r8, r8, MSR_RI|MSR_ME
1117 mtspr SPRN_SRR1, r8
1118 addi r8, r4, 1f - relocate_new_kernel
1119 mtspr SPRN_SRR0, r8
1120 sync
1121 rfi
1123 1:
1124 #endif
1125 /* from this point address translation is turned off */
1126 /* and interrupts are disabled */
1128 /* set a new stack at the bottom of our page... */
1129 /* (not really needed now) */
1130 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
1131 stw r0, 0(r1)
1133 /* Do the copies */
1134 li r6, 0 /* checksum */
1135 mr r0, r3
1136 b 1f
1138 0: /* top, read another word for the indirection page */
1139 lwzu r0, 4(r3)
1141 1:
1142 /* is it a destination page? (r8) */
1143 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
1144 beq 2f
1146 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
1147 b 0b
1149 2: /* is it an indirection page? (r3) */
1150 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
1151 beq 2f
1153 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1154 subi r3, r3, 4
1155 b 0b
1157 2: /* are we done? */
1158 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
1159 beq 2f
1160 b 3f
1162 2: /* is it a source page? (r9) */
1163 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
1164 beq 0b
1166 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1168 li r7, PAGE_SIZE / 4
1169 mtctr r7
1170 subi r9, r9, 4
1171 subi r8, r8, 4
1172 9:
1173 lwzu r0, 4(r9) /* do the copy */
1174 xor r6, r6, r0
1175 stwu r0, 4(r8)
1176 dcbst 0, r8
1177 sync
1178 icbi 0, r8
1179 bdnz 9b
1181 addi r9, r9, 4
1182 addi r8, r8, 4
1183 b 0b
1185 3:
1187 /* To be certain of avoiding problems with self-modifying code
1188 * execute a serializing instruction here.
1189 */
1190 isync
1191 sync
1193 mfspr r3, SPRN_PIR /* current core we are running on */
1194 mr r4, r5 /* load physical address of chunk called */
1196 /* jump to the entry point, usually the setup routine */
1197 mtlr r5
1198 blrl
1200 1: b 1b
1202 relocate_new_kernel_end:
1204 .globl relocate_new_kernel_size
1205 relocate_new_kernel_size:
1206 .long relocate_new_kernel_end - relocate_new_kernel
1207 #endif