2 * Copyright 2007, Michael Ellerman, IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/msi.h>
16 #include <linux/export.h>
17 #include <linux/of_platform.h>
18 #include <linux/debugfs.h>
19 #include <linux/slab.h>
22 #include <asm/machdep.h>
27 * MSIC registers, specified as offsets from dcr_base
29 #define MSIC_CTRL_REG 0x0
31 /* Base Address registers specify FIFO location in BE memory */
32 #define MSIC_BASE_ADDR_HI_REG 0x3
33 #define MSIC_BASE_ADDR_LO_REG 0x4
35 /* Hold the read/write offsets into the FIFO */
36 #define MSIC_READ_OFFSET_REG 0x5
37 #define MSIC_WRITE_OFFSET_REG 0x6
40 /* MSIC control register flags */
41 #define MSIC_CTRL_ENABLE 0x0001
42 #define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
43 #define MSIC_CTRL_IRQ_ENABLE 0x0008
44 #define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
47 * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
48 * Currently we're using a 64KB FIFO size.
50 #define MSIC_FIFO_SIZE_SHIFT 16
51 #define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
54 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
55 * 8-9 of the MSIC control reg.
57 #define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
60 * We need to mask the read/write offsets to make sure they stay within
61 * the bounds of the FIFO. Also they should always be 16-byte aligned.
63 #define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
65 /* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
66 #define MSIC_FIFO_ENTRY_SIZE 0x10
70 struct irq_domain
*irq_domain
;
81 void axon_msi_debug_setup(struct device_node
*dn
, struct axon_msic
*msic
);
83 static inline void axon_msi_debug_setup(struct device_node
*dn
,
84 struct axon_msic
*msic
) { }
88 static void msic_dcr_write(struct axon_msic
*msic
, unsigned int dcr_n
, u32 val
)
90 pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val
, dcr_n
);
92 dcr_write(msic
->dcr_host
, dcr_n
, val
);
95 static void axon_msi_cascade(unsigned int irq
, struct irq_desc
*desc
)
97 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
98 struct axon_msic
*msic
= irq_get_handler_data(irq
);
99 u32 write_offset
, msi
;
103 write_offset
= dcr_read(msic
->dcr_host
, MSIC_WRITE_OFFSET_REG
);
104 pr_devel("axon_msi: original write_offset 0x%x\n", write_offset
);
106 /* write_offset doesn't wrap properly, so we have to mask it */
107 write_offset
&= MSIC_FIFO_SIZE_MASK
;
109 while (msic
->read_offset
!= write_offset
&& retry
< 100) {
110 idx
= msic
->read_offset
/ sizeof(__le32
);
111 msi
= le32_to_cpu(msic
->fifo_virt
[idx
]);
114 pr_devel("axon_msi: woff %x roff %x msi %x\n",
115 write_offset
, msic
->read_offset
, msi
);
117 if (msi
< nr_irqs
&& irq_get_chip_data(msi
) == msic
) {
118 generic_handle_irq(msi
);
119 msic
->fifo_virt
[idx
] = cpu_to_le32(0xffffffff);
122 * Reading the MSIC_WRITE_OFFSET_REG does not
123 * reliably flush the outstanding DMA to the
124 * FIFO buffer. Here we were reading stale
125 * data, so we need to retry.
129 pr_devel("axon_msi: invalid irq 0x%x!\n", msi
);
134 pr_devel("axon_msi: late irq 0x%x, retry %d\n",
139 msic
->read_offset
+= MSIC_FIFO_ENTRY_SIZE
;
140 msic
->read_offset
&= MSIC_FIFO_SIZE_MASK
;
144 printk(KERN_WARNING
"axon_msi: irq timed out\n");
146 msic
->read_offset
+= MSIC_FIFO_ENTRY_SIZE
;
147 msic
->read_offset
&= MSIC_FIFO_SIZE_MASK
;
150 chip
->irq_eoi(&desc
->irq_data
);
153 static struct axon_msic
*find_msi_translator(struct pci_dev
*dev
)
155 struct irq_domain
*irq_domain
;
156 struct device_node
*dn
, *tmp
;
158 struct axon_msic
*msic
= NULL
;
160 dn
= of_node_get(pci_device_to_OF_node(dev
));
162 dev_dbg(&dev
->dev
, "axon_msi: no pci_dn found\n");
166 for (; dn
; dn
= of_get_next_parent(dn
)) {
167 ph
= of_get_property(dn
, "msi-translator", NULL
);
174 "axon_msi: no msi-translator property found\n");
179 dn
= of_find_node_by_phandle(*ph
);
183 "axon_msi: msi-translator doesn't point to a node\n");
187 irq_domain
= irq_find_host(dn
);
189 dev_dbg(&dev
->dev
, "axon_msi: no irq_domain found for node %s\n",
194 msic
= irq_domain
->host_data
;
202 static int axon_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
204 if (!find_msi_translator(dev
))
210 static int setup_msi_msg_address(struct pci_dev
*dev
, struct msi_msg
*msg
)
212 struct device_node
*dn
;
213 struct msi_desc
*entry
;
217 dn
= of_node_get(pci_device_to_OF_node(dev
));
219 dev_dbg(&dev
->dev
, "axon_msi: no pci_dn found\n");
223 entry
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
225 for (; dn
; dn
= of_get_next_parent(dn
)) {
226 if (entry
->msi_attrib
.is_64
) {
227 prop
= of_get_property(dn
, "msi-address-64", &len
);
232 prop
= of_get_property(dn
, "msi-address-32", &len
);
239 "axon_msi: no msi-address-(32|64) properties found\n");
245 msg
->address_hi
= prop
[0];
246 msg
->address_lo
= prop
[1];
250 msg
->address_lo
= prop
[0];
254 "axon_msi: malformed msi-address-(32|64) property\n");
264 static int axon_msi_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
266 unsigned int virq
, rc
;
267 struct msi_desc
*entry
;
269 struct axon_msic
*msic
;
271 msic
= find_msi_translator(dev
);
275 rc
= setup_msi_msg_address(dev
, &msg
);
279 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
280 virq
= irq_create_direct_mapping(msic
->irq_domain
);
281 if (virq
== NO_IRQ
) {
283 "axon_msi: virq allocation failed!\n");
286 dev_dbg(&dev
->dev
, "axon_msi: allocated virq 0x%x\n", virq
);
288 irq_set_msi_desc(virq
, entry
);
290 write_msi_msg(virq
, &msg
);
296 static void axon_msi_teardown_msi_irqs(struct pci_dev
*dev
)
298 struct msi_desc
*entry
;
300 dev_dbg(&dev
->dev
, "axon_msi: tearing down msi irqs\n");
302 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
303 if (entry
->irq
== NO_IRQ
)
306 irq_set_msi_desc(entry
->irq
, NULL
);
307 irq_dispose_mapping(entry
->irq
);
311 static struct irq_chip msic_irq_chip
= {
312 .irq_mask
= mask_msi_irq
,
313 .irq_unmask
= unmask_msi_irq
,
314 .irq_shutdown
= mask_msi_irq
,
318 static int msic_host_map(struct irq_domain
*h
, unsigned int virq
,
321 irq_set_chip_data(virq
, h
->host_data
);
322 irq_set_chip_and_handler(virq
, &msic_irq_chip
, handle_simple_irq
);
327 static const struct irq_domain_ops msic_host_ops
= {
328 .map
= msic_host_map
,
331 static void axon_msi_shutdown(struct platform_device
*device
)
333 struct axon_msic
*msic
= dev_get_drvdata(&device
->dev
);
336 pr_devel("axon_msi: disabling %s\n",
337 msic
->irq_domain
->of_node
->full_name
);
338 tmp
= dcr_read(msic
->dcr_host
, MSIC_CTRL_REG
);
339 tmp
&= ~MSIC_CTRL_ENABLE
& ~MSIC_CTRL_IRQ_ENABLE
;
340 msic_dcr_write(msic
, MSIC_CTRL_REG
, tmp
);
343 static int axon_msi_probe(struct platform_device
*device
)
345 struct device_node
*dn
= device
->dev
.of_node
;
346 struct axon_msic
*msic
;
348 int dcr_base
, dcr_len
;
350 pr_devel("axon_msi: setting up dn %s\n", dn
->full_name
);
352 msic
= kzalloc(sizeof(struct axon_msic
), GFP_KERNEL
);
354 printk(KERN_ERR
"axon_msi: couldn't allocate msic for %s\n",
359 dcr_base
= dcr_resource_start(dn
, 0);
360 dcr_len
= dcr_resource_len(dn
, 0);
362 if (dcr_base
== 0 || dcr_len
== 0) {
364 "axon_msi: couldn't parse dcr properties on %s\n",
369 msic
->dcr_host
= dcr_map(dn
, dcr_base
, dcr_len
);
370 if (!DCR_MAP_OK(msic
->dcr_host
)) {
371 printk(KERN_ERR
"axon_msi: dcr_map failed for %s\n",
376 msic
->fifo_virt
= dma_alloc_coherent(&device
->dev
, MSIC_FIFO_SIZE_BYTES
,
377 &msic
->fifo_phys
, GFP_KERNEL
);
378 if (!msic
->fifo_virt
) {
379 printk(KERN_ERR
"axon_msi: couldn't allocate fifo for %s\n",
384 virq
= irq_of_parse_and_map(dn
, 0);
385 if (virq
== NO_IRQ
) {
386 printk(KERN_ERR
"axon_msi: irq parse and map failed for %s\n",
390 memset(msic
->fifo_virt
, 0xff, MSIC_FIFO_SIZE_BYTES
);
392 /* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */
393 msic
->irq_domain
= irq_domain_add_nomap(dn
, 65536, &msic_host_ops
, msic
);
394 if (!msic
->irq_domain
) {
395 printk(KERN_ERR
"axon_msi: couldn't allocate irq_domain for %s\n",
400 irq_set_handler_data(virq
, msic
);
401 irq_set_chained_handler(virq
, axon_msi_cascade
);
402 pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq
);
404 /* Enable the MSIC hardware */
405 msic_dcr_write(msic
, MSIC_BASE_ADDR_HI_REG
, msic
->fifo_phys
>> 32);
406 msic_dcr_write(msic
, MSIC_BASE_ADDR_LO_REG
,
407 msic
->fifo_phys
& 0xFFFFFFFF);
408 msic_dcr_write(msic
, MSIC_CTRL_REG
,
409 MSIC_CTRL_IRQ_ENABLE
| MSIC_CTRL_ENABLE
|
410 MSIC_CTRL_FIFO_SIZE
);
412 msic
->read_offset
= dcr_read(msic
->dcr_host
, MSIC_WRITE_OFFSET_REG
)
413 & MSIC_FIFO_SIZE_MASK
;
415 dev_set_drvdata(&device
->dev
, msic
);
417 ppc_md
.setup_msi_irqs
= axon_msi_setup_msi_irqs
;
418 ppc_md
.teardown_msi_irqs
= axon_msi_teardown_msi_irqs
;
419 ppc_md
.msi_check_device
= axon_msi_check_device
;
421 axon_msi_debug_setup(dn
, msic
);
423 printk(KERN_DEBUG
"axon_msi: setup MSIC on %s\n", dn
->full_name
);
428 dma_free_coherent(&device
->dev
, MSIC_FIFO_SIZE_BYTES
, msic
->fifo_virt
,
437 static const struct of_device_id axon_msi_device_id
[] = {
439 .compatible
= "ibm,axon-msic"
444 static struct platform_driver axon_msi_driver
= {
445 .probe
= axon_msi_probe
,
446 .shutdown
= axon_msi_shutdown
,
449 .owner
= THIS_MODULE
,
450 .of_match_table
= axon_msi_device_id
,
454 static int __init
axon_msi_init(void)
456 return platform_driver_register(&axon_msi_driver
);
458 subsys_initcall(axon_msi_init
);
462 static int msic_set(void *data
, u64 val
)
464 struct axon_msic
*msic
= data
;
465 out_le32(msic
->trigger
, val
);
469 static int msic_get(void *data
, u64
*val
)
475 DEFINE_SIMPLE_ATTRIBUTE(fops_msic
, msic_get
, msic_set
, "%llu\n");
477 void axon_msi_debug_setup(struct device_node
*dn
, struct axon_msic
*msic
)
482 addr
= of_translate_address(dn
, of_get_property(dn
, "reg", NULL
));
483 if (addr
== OF_BAD_ADDR
) {
484 pr_devel("axon_msi: couldn't translate reg property\n");
488 msic
->trigger
= ioremap(addr
, 0x4);
489 if (!msic
->trigger
) {
490 pr_devel("axon_msi: ioremap failed\n");
494 snprintf(name
, sizeof(name
), "msic_%d", of_node_to_nid(dn
));
496 if (!debugfs_create_file(name
, 0600, powerpc_debugfs_root
,
498 pr_devel("axon_msi: debugfs_create_file failed!\n");