2 * Support for PCI on Celleb platform.
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
6 * This code is based on arch/powerpc/kernel/rtas_pci.c:
7 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
27 #include <linux/kernel.h>
28 #include <linux/threads.h>
29 #include <linux/pci.h>
30 #include <linux/string.h>
31 #include <linux/init.h>
32 #include <linux/bootmem.h>
33 #include <linux/pci_regs.h>
35 #include <linux/of_device.h>
36 #include <linux/slab.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/ppc-pci.h>
44 #include "celleb_pci.h"
46 #define MAX_PCI_DEVICES 32
47 #define MAX_PCI_FUNCTIONS 8
48 #define MAX_PCI_BASE_ADDRS 3 /* use 64 bit address */
50 /* definition for fake pci configuration area for GbE, .... ,and etc. */
52 struct celleb_pci_resource
{
53 struct resource r
[MAX_PCI_BASE_ADDRS
];
56 struct celleb_pci_private
{
57 unsigned char *fake_config
[MAX_PCI_DEVICES
][MAX_PCI_FUNCTIONS
];
58 struct celleb_pci_resource
*res
[MAX_PCI_DEVICES
][MAX_PCI_FUNCTIONS
];
61 static inline u8
celleb_fake_config_readb(void *addr
)
67 static inline u16
celleb_fake_config_readw(void *addr
)
70 return le16_to_cpu(*p
);
73 static inline u32
celleb_fake_config_readl(void *addr
)
76 return le32_to_cpu(*p
);
79 static inline void celleb_fake_config_writeb(u32 val
, void *addr
)
85 static inline void celleb_fake_config_writew(u32 val
, void *addr
)
89 val16
= cpu_to_le16(val
);
93 static inline void celleb_fake_config_writel(u32 val
, void *addr
)
97 val32
= cpu_to_le32(val
);
101 static unsigned char *get_fake_config_start(struct pci_controller
*hose
,
104 struct celleb_pci_private
*private = hose
->private_data
;
109 return private->fake_config
[devno
][fn
];
112 static struct celleb_pci_resource
*get_resource_start(
113 struct pci_controller
*hose
,
116 struct celleb_pci_private
*private = hose
->private_data
;
121 return private->res
[devno
][fn
];
125 static void celleb_config_read_fake(unsigned char *config
, int where
,
128 char *p
= config
+ where
;
132 *val
= celleb_fake_config_readb(p
);
135 *val
= celleb_fake_config_readw(p
);
138 *val
= celleb_fake_config_readl(p
);
143 static void celleb_config_write_fake(unsigned char *config
, int where
,
146 char *p
= config
+ where
;
150 celleb_fake_config_writeb(val
, p
);
153 celleb_fake_config_writew(val
, p
);
156 celleb_fake_config_writel(val
, p
);
161 static int celleb_fake_pci_read_config(struct pci_bus
*bus
,
162 unsigned int devfn
, int where
, int size
, u32
*val
)
165 struct pci_controller
*hose
= pci_bus_to_host(bus
);
166 unsigned int devno
= devfn
>> 3;
167 unsigned int fn
= devfn
& 0x7;
169 /* allignment check */
170 BUG_ON(where
% size
);
172 pr_debug(" fake read: bus=0x%x, ", bus
->number
);
173 config
= get_fake_config_start(hose
, devno
, fn
);
175 pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno
, where
, size
);
177 pr_debug("failed\n");
178 return PCIBIOS_DEVICE_NOT_FOUND
;
181 celleb_config_read_fake(config
, where
, size
, val
);
182 pr_debug("val=0x%x\n", *val
);
184 return PCIBIOS_SUCCESSFUL
;
188 static int celleb_fake_pci_write_config(struct pci_bus
*bus
,
189 unsigned int devfn
, int where
, int size
, u32 val
)
192 struct pci_controller
*hose
= pci_bus_to_host(bus
);
193 struct celleb_pci_resource
*res
;
194 unsigned int devno
= devfn
>> 3;
195 unsigned int fn
= devfn
& 0x7;
197 /* allignment check */
198 BUG_ON(where
% size
);
200 config
= get_fake_config_start(hose
, devno
, fn
);
203 return PCIBIOS_DEVICE_NOT_FOUND
;
206 int i
= (where
- PCI_BASE_ADDRESS_0
) >> 3;
209 case PCI_BASE_ADDRESS_0
:
210 case PCI_BASE_ADDRESS_2
:
212 return PCIBIOS_DEVICE_NOT_FOUND
;
213 res
= get_resource_start(hose
, devno
, fn
);
215 return PCIBIOS_DEVICE_NOT_FOUND
;
216 celleb_config_write_fake(config
, where
, size
,
217 (res
->r
[i
].end
- res
->r
[i
].start
));
218 return PCIBIOS_SUCCESSFUL
;
219 case PCI_BASE_ADDRESS_1
:
220 case PCI_BASE_ADDRESS_3
:
221 case PCI_BASE_ADDRESS_4
:
222 case PCI_BASE_ADDRESS_5
:
229 celleb_config_write_fake(config
, where
, size
, val
);
230 pr_debug(" fake write: where=%x, size=%d, val=%x\n",
233 return PCIBIOS_SUCCESSFUL
;
236 static struct pci_ops celleb_fake_pci_ops
= {
237 .read
= celleb_fake_pci_read_config
,
238 .write
= celleb_fake_pci_write_config
,
241 static inline void celleb_setup_pci_base_addrs(struct pci_controller
*hose
,
242 unsigned int devno
, unsigned int fn
,
243 unsigned int num_base_addr
)
246 unsigned char *config
;
247 struct celleb_pci_resource
*res
;
249 config
= get_fake_config_start(hose
, devno
, fn
);
250 res
= get_resource_start(hose
, devno
, fn
);
255 switch (num_base_addr
) {
257 val
= (res
->r
[2].start
& 0xfffffff0)
258 | PCI_BASE_ADDRESS_MEM_TYPE_64
;
259 celleb_config_write_fake(config
, PCI_BASE_ADDRESS_4
, 4, val
);
260 val
= res
->r
[2].start
>> 32;
261 celleb_config_write_fake(config
, PCI_BASE_ADDRESS_5
, 4, val
);
264 val
= (res
->r
[1].start
& 0xfffffff0)
265 | PCI_BASE_ADDRESS_MEM_TYPE_64
;
266 celleb_config_write_fake(config
, PCI_BASE_ADDRESS_2
, 4, val
);
267 val
= res
->r
[1].start
>> 32;
268 celleb_config_write_fake(config
, PCI_BASE_ADDRESS_3
, 4, val
);
271 val
= (res
->r
[0].start
& 0xfffffff0)
272 | PCI_BASE_ADDRESS_MEM_TYPE_64
;
273 celleb_config_write_fake(config
, PCI_BASE_ADDRESS_0
, 4, val
);
274 val
= res
->r
[0].start
>> 32;
275 celleb_config_write_fake(config
, PCI_BASE_ADDRESS_1
, 4, val
);
279 val
= PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
;
280 celleb_config_write_fake(config
, PCI_COMMAND
, 2, val
);
283 static int __init
celleb_setup_fake_pci_device(struct device_node
*node
,
284 struct pci_controller
*hose
)
287 int num_base_addr
= 0;
289 const u32
*wi0
, *wi1
, *wi2
, *wi3
, *wi4
;
290 unsigned int devno
, fn
;
291 struct celleb_pci_private
*private = hose
->private_data
;
292 unsigned char **config
= NULL
;
293 struct celleb_pci_resource
**res
= NULL
;
295 const unsigned long *li
;
298 if (private == NULL
) {
299 printk(KERN_ERR
"PCI: "
300 "memory space for pci controller is not assigned\n");
304 name
= of_get_property(node
, "model", &rlen
);
306 printk(KERN_ERR
"PCI: model property not found.\n");
310 wi4
= of_get_property(node
, "reg", &rlen
);
314 devno
= ((wi4
[0] >> 8) & 0xff) >> 3;
315 fn
= (wi4
[0] >> 8) & 0x7;
317 pr_debug("PCI: celleb_setup_fake_pci() %s devno=%x fn=%x\n", name
,
321 config
= &private->fake_config
[devno
][fn
];
322 *config
= zalloc_maybe_bootmem(size
, GFP_KERNEL
);
323 if (*config
== NULL
) {
324 printk(KERN_ERR
"PCI: "
325 "not enough memory for fake configuration space\n");
328 pr_debug("PCI: fake config area assigned 0x%016lx\n",
329 (unsigned long)*config
);
331 size
= sizeof(struct celleb_pci_resource
);
332 res
= &private->res
[devno
][fn
];
333 *res
= zalloc_maybe_bootmem(size
, GFP_KERNEL
);
336 "PCI: not enough memory for resource data space\n");
339 pr_debug("PCI: res assigned 0x%016lx\n", (unsigned long)*res
);
341 wi0
= of_get_property(node
, "device-id", NULL
);
342 wi1
= of_get_property(node
, "vendor-id", NULL
);
343 wi2
= of_get_property(node
, "class-code", NULL
);
344 wi3
= of_get_property(node
, "revision-id", NULL
);
345 if (!wi0
|| !wi1
|| !wi2
|| !wi3
) {
346 printk(KERN_ERR
"PCI: Missing device tree properties.\n");
350 celleb_config_write_fake(*config
, PCI_DEVICE_ID
, 2, wi0
[0] & 0xffff);
351 celleb_config_write_fake(*config
, PCI_VENDOR_ID
, 2, wi1
[0] & 0xffff);
352 pr_debug("class-code = 0x%08x\n", wi2
[0]);
354 celleb_config_write_fake(*config
, PCI_CLASS_PROG
, 1, wi2
[0] & 0xff);
355 celleb_config_write_fake(*config
, PCI_CLASS_DEVICE
, 2,
356 (wi2
[0] >> 8) & 0xffff);
357 celleb_config_write_fake(*config
, PCI_REVISION_ID
, 1, wi3
[0]);
359 while (num_base_addr
< MAX_PCI_BASE_ADDRS
) {
360 result
= of_address_to_resource(node
,
361 num_base_addr
, &(*res
)->r
[num_base_addr
]);
367 celleb_setup_pci_base_addrs(hose
, devno
, fn
, num_base_addr
);
369 li
= of_get_property(node
, "interrupts", &rlen
);
371 printk(KERN_ERR
"PCI: interrupts not found.\n");
375 celleb_config_write_fake(*config
, PCI_INTERRUPT_PIN
, 1, 1);
376 celleb_config_write_fake(*config
, PCI_INTERRUPT_LINE
, 1, val
);
379 pr_debug("PCI: %s irq=%ld\n", name
, li
[0]);
380 for (i
= 0; i
< 6; i
++) {
381 celleb_config_read_fake(*config
,
382 PCI_BASE_ADDRESS_0
+ 0x4 * i
, 4,
384 pr_debug("PCI: %s fn=%d base_address_%d=0x%x\n",
389 celleb_config_write_fake(*config
, PCI_HEADER_TYPE
, 1,
390 PCI_HEADER_TYPE_NORMAL
);
396 if (config
&& *config
)
402 if (config
&& *config
) {
404 free_bootmem(__pa(*config
), size
);
407 size
= sizeof(struct celleb_pci_resource
);
408 free_bootmem(__pa(*res
), size
);
415 static int __init
phb_set_bus_ranges(struct device_node
*dev
,
416 struct pci_controller
*phb
)
418 const int *bus_range
;
421 bus_range
= of_get_property(dev
, "bus-range", &len
);
422 if (bus_range
== NULL
|| len
< 2 * sizeof(int))
425 phb
->first_busno
= bus_range
[0];
426 phb
->last_busno
= bus_range
[1];
431 static void __init
celleb_alloc_private_mem(struct pci_controller
*hose
)
434 zalloc_maybe_bootmem(sizeof(struct celleb_pci_private
),
438 static int __init
celleb_setup_fake_pci(struct device_node
*dev
,
439 struct pci_controller
*phb
)
441 struct device_node
*node
;
443 phb
->ops
= &celleb_fake_pci_ops
;
444 celleb_alloc_private_mem(phb
);
446 for (node
= of_get_next_child(dev
, NULL
);
447 node
!= NULL
; node
= of_get_next_child(dev
, node
))
448 celleb_setup_fake_pci_device(node
, phb
);
453 static struct celleb_phb_spec celleb_fake_pci_spec __initdata
= {
454 .setup
= celleb_setup_fake_pci
,
457 static struct of_device_id celleb_phb_match
[] __initdata
= {
459 .name
= "pci-pseudo",
460 .data
= &celleb_fake_pci_spec
,
463 .data
= &celleb_epci_spec
,
466 .data
= &celleb_pciex_spec
,
471 int __init
celleb_setup_phb(struct pci_controller
*phb
)
473 struct device_node
*dev
= phb
->dn
;
474 const struct of_device_id
*match
;
475 const struct celleb_phb_spec
*phb_spec
;
478 match
= of_match_node(celleb_phb_match
, dev
);
482 phb_set_bus_ranges(dev
, phb
);
485 phb_spec
= match
->data
;
486 rc
= (*phb_spec
->setup
)(dev
, phb
);
491 iowa_register_bus(phb
, phb_spec
->ops
,
493 phb_spec
->iowa_data
);
497 int celleb_pci_probe_mode(struct pci_bus
*bus
)
499 return PCI_PROBE_DEVTREE
;