arch/tile/include/arch/trio_pcie_rc.h

   1 /*
   2  * Copyright 2012 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 /* Machine-generated file; do not edit. */
  16
  17 #ifndef __ARCH_TRIO_PCIE_RC_H__
  18 #define __ARCH_TRIO_PCIE_RC_H__
  19
  20 #include <arch/abi.h>
  21 #include <arch/trio_pcie_rc_def.h>
  22
  23 #ifndef __ASSEMBLER__
  24
  25 /* Device Capabilities Register. */
  26
  27 __extension__
  28 typedef union
  29 {
  30   struct
  31   {
  32 #ifndef __BIG_ENDIAN__
  33     /*
  34      * Max_Payload_Size Supported, writablethrough the MAC_STANDARD interface
  35      */
  36     uint_reg_t mps_sup                    : 3;
  37     /*
  38      * This field is writable through the MAC_STANDARD interface.  However,
  39      * Phantom Function is not  supported. Therefore, the application must
  40      * not write any value other than 0x0 to this  field.
  41      */
  42     uint_reg_t phantom_function_supported : 2;
  43     /* This bit is writable through the MAC_STANDARD interface. */
  44     uint_reg_t ext_tag_field_supported    : 1;
  45     /* Reserved. */
  46     uint_reg_t __reserved_0               : 3;
  47     /* Endpoint L1 Acceptable Latency Must be 0x0 for non-Endpoint devices. */
  48     uint_reg_t l1_lat                     : 3;
  49     /*
  50      * Undefined since PCI Express 1.1 (Was Attention Button Present for PCI
  51      * Express 1.0a)
  52      */
  53     uint_reg_t r1                         : 1;
  54     /*
  55      * Undefined since PCI Express 1.1 (Was Attention Indicator Present for
  56      * PCI  Express 1.0a)
  57      */
  58     uint_reg_t r2                         : 1;
  59     /*
  60      * Undefined since PCI Express 1.1 (Was Power Indicator Present for PCI
  61      * Express 1.0a)
  62      */
  63     uint_reg_t r3                         : 1;
  64     /*
  65      * Role-Based Error Reporting, writable through the MAC_STANDARD
  66      * interface.  Required to be set for device compliant to 1.1  spec and
  67      * later.
  68      */
  69     uint_reg_t rer                        : 1;
  70     /* Reserved. */
  71     uint_reg_t __reserved_1               : 2;
  72     /* Captured Slot Power Limit Value Upstream port only. */
  73     uint_reg_t slot_pwr_lim               : 8;
  74     /* Captured Slot Power Limit Scale Upstream port only. */
  75     uint_reg_t slot_pwr_scale             : 2;
  76     /* Reserved. */
  77     uint_reg_t __reserved_2               : 4;
  78     /* Endpoint L0s Acceptable LatencyMust be 0x0 for non-Endpoint devices. */
  79     uint_reg_t l0s_lat                    : 1;
  80     /* Reserved. */
  81     uint_reg_t __reserved_3               : 31;
  82 #else   /* __BIG_ENDIAN__ */
  83     uint_reg_t __reserved_3               : 31;
  84     uint_reg_t l0s_lat                    : 1;
  85     uint_reg_t __reserved_2               : 4;
  86     uint_reg_t slot_pwr_scale             : 2;
  87     uint_reg_t slot_pwr_lim               : 8;
  88     uint_reg_t __reserved_1               : 2;
  89     uint_reg_t rer                        : 1;
  90     uint_reg_t r3                         : 1;
  91     uint_reg_t r2                         : 1;
  92     uint_reg_t r1                         : 1;
  93     uint_reg_t l1_lat                     : 3;
  94     uint_reg_t __reserved_0               : 3;
  95     uint_reg_t ext_tag_field_supported    : 1;
  96     uint_reg_t phantom_function_supported : 2;
  97     uint_reg_t mps_sup                    : 3;
  98 #endif
  99   };
 100
 101   uint_reg_t word;
 102 } TRIO_PCIE_RC_DEVICE_CAP_t;
 103
 104 /* Device Control Register. */
 105
 106 __extension__
 107 typedef union
 108 {
 109   struct
 110   {
 111 #ifndef __BIG_ENDIAN__
 112     /* Correctable Error Reporting Enable */
 113     uint_reg_t cor_err_ena      : 1;
 114     /* Non-Fatal Error Reporting Enable */
 115     uint_reg_t nf_err_ena       : 1;
 116     /* Fatal Error Reporting Enable */
 117     uint_reg_t fatal_err_ena    : 1;
 118     /* Unsupported Request Reporting Enable */
 119     uint_reg_t ur_ena           : 1;
 120     /* Relaxed orderring enable */
 121     uint_reg_t ro_ena           : 1;
 122     /* Max Payload Size */
 123     uint_reg_t max_payload_size : 3;
 124     /* Extended Tag Field Enable */
 125     uint_reg_t ext_tag          : 1;
 126     /* Phantom Function Enable */
 127     uint_reg_t ph_fn_ena        : 1;
 128     /* AUX Power PM Enable */
 129     uint_reg_t aux_pm_ena       : 1;
 130     /* Enable NoSnoop */
 131     uint_reg_t no_snoop         : 1;
 132     /* Max read request size */
 133     uint_reg_t max_read_req_sz  : 3;
 134     /* Reserved. */
 135     uint_reg_t __reserved       : 49;
 136 #else   /* __BIG_ENDIAN__ */
 137     uint_reg_t __reserved       : 49;
 138     uint_reg_t max_read_req_sz  : 3;
 139     uint_reg_t no_snoop         : 1;
 140     uint_reg_t aux_pm_ena       : 1;
 141     uint_reg_t ph_fn_ena        : 1;
 142     uint_reg_t ext_tag          : 1;
 143     uint_reg_t max_payload_size : 3;
 144     uint_reg_t ro_ena           : 1;
 145     uint_reg_t ur_ena           : 1;
 146     uint_reg_t fatal_err_ena    : 1;
 147     uint_reg_t nf_err_ena       : 1;
 148     uint_reg_t cor_err_ena      : 1;
 149 #endif
 150   };
 151
 152   uint_reg_t word;
 153 } TRIO_PCIE_RC_DEVICE_CONTROL_t;
 154 #endif /* !defined(__ASSEMBLER__) */
 155
 156 #endif /* !defined(__ARCH_TRIO_PCIE_RC_H__) */