drivers/dma/ioat/registers.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef _IOAT_REGISTERS_H_
  22 #define _IOAT_REGISTERS_H_
  23
  24 #define IOAT_PCI_DMACTRL_OFFSET                 0x48
  25 #define IOAT_PCI_DMACTRL_DMA_EN                 0x00000001
  26 #define IOAT_PCI_DMACTRL_MSI_EN                 0x00000002
  27
  28 #define IOAT_PCI_DEVICE_ID_OFFSET               0x02
  29 #define IOAT_PCI_DMAUNCERRSTS_OFFSET            0x148
  30 #define IOAT_PCI_CHANERR_INT_OFFSET             0x180
  31 #define IOAT_PCI_CHANERRMASK_INT_OFFSET         0x184
  32
  33 /* MMIO Device Registers */
  34 #define IOAT_CHANCNT_OFFSET                     0x00    /*  8-bit */
  35
  36 #define IOAT_XFERCAP_OFFSET                     0x01    /*  8-bit */
  37 #define IOAT_XFERCAP_4KB                        12
  38 #define IOAT_XFERCAP_8KB                        13
  39 #define IOAT_XFERCAP_16KB                       14
  40 #define IOAT_XFERCAP_32KB                       15
  41 #define IOAT_XFERCAP_32GB                       0
  42
  43 #define IOAT_GENCTRL_OFFSET                     0x02    /*  8-bit */
  44 #define IOAT_GENCTRL_DEBUG_EN                   0x01
  45
  46 #define IOAT_INTRCTRL_OFFSET                    0x03    /*  8-bit */
  47 #define IOAT_INTRCTRL_MASTER_INT_EN             0x01    /* Master Interrupt Enable */
  48 #define IOAT_INTRCTRL_INT_STATUS                0x02    /* ATTNSTATUS -or- Channel Int */
  49 #define IOAT_INTRCTRL_INT                       0x04    /* INT_STATUS -and- MASTER_INT_EN */
  50 #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL       0x08    /* Enable all MSI-X vectors */
  51
  52 #define IOAT_ATTNSTATUS_OFFSET                  0x04    /* Each bit is a channel */
  53
  54 #define IOAT_VER_OFFSET                         0x08    /*  8-bit */
  55 #define IOAT_VER_MAJOR_MASK                     0xF0
  56 #define IOAT_VER_MINOR_MASK                     0x0F
  57 #define GET_IOAT_VER_MAJOR(x)                   (((x) & IOAT_VER_MAJOR_MASK) >> 4)
  58 #define GET_IOAT_VER_MINOR(x)                   ((x) & IOAT_VER_MINOR_MASK)
  59
  60 #define IOAT_PERPORTOFFSET_OFFSET               0x0A    /* 16-bit */
  61
  62 #define IOAT_INTRDELAY_OFFSET                   0x0C    /* 16-bit */
  63 #define IOAT_INTRDELAY_MASK                     0x3FFF  /* Interrupt Delay Time */
  64 #define IOAT_INTRDELAY_COALESE_SUPPORT          0x8000  /* Interrupt Coalescing Supported */
  65
  66 #define IOAT_DEVICE_STATUS_OFFSET               0x0E    /* 16-bit */
  67 #define IOAT_DEVICE_STATUS_DEGRADED_MODE        0x0001
  68 #define IOAT_DEVICE_MMIO_RESTRICTED             0x0002
  69 #define IOAT_DEVICE_MEMORY_BYPASS               0x0004
  70 #define IOAT_DEVICE_ADDRESS_REMAPPING           0x0008
  71
  72 #define IOAT_DMA_CAP_OFFSET                     0x10    /* 32-bit */
  73 #define IOAT_CAP_PAGE_BREAK                     0x00000001
  74 #define IOAT_CAP_CRC                            0x00000002
  75 #define IOAT_CAP_SKIP_MARKER                    0x00000004
  76 #define IOAT_CAP_DCA                            0x00000010
  77 #define IOAT_CAP_CRC_MOVE                       0x00000020
  78 #define IOAT_CAP_FILL_BLOCK                     0x00000040
  79 #define IOAT_CAP_APIC                           0x00000080
  80 #define IOAT_CAP_XOR                            0x00000100
  81 #define IOAT_CAP_PQ                             0x00000200
  82 #define IOAT_CAP_DWBES                          0x00002000
  83 #define IOAT_CAP_RAID16SS                       0x00020000
  84
  85 #define IOAT_CHANNEL_MMIO_SIZE                  0x80    /* Each Channel MMIO space is this size */
  86
  87 /* DMA Channel Registers */
  88 #define IOAT_CHANCTRL_OFFSET                    0x00    /* 16-bit Channel Control Register */
  89 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK     0xF000
  90 #define IOAT3_CHANCTRL_COMPL_DCA_EN             0x0200
  91 #define IOAT_CHANCTRL_CHANNEL_IN_USE            0x0100
  92 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL     0x0020
  93 #define IOAT_CHANCTRL_ERR_INT_EN                0x0010
  94 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN          0x0008
  95 #define IOAT_CHANCTRL_ERR_COMPLETION_EN         0x0004
  96 #define IOAT_CHANCTRL_INT_REARM                 0x0001
  97 #define IOAT_CHANCTRL_RUN                       (IOAT_CHANCTRL_INT_REARM |\
  98                                                  IOAT_CHANCTRL_ERR_INT_EN |\
  99                                                  IOAT_CHANCTRL_ERR_COMPLETION_EN |\
 100                                                  IOAT_CHANCTRL_ANY_ERR_ABORT_EN)
 101
 102 #define IOAT_DMA_COMP_OFFSET                    0x02    /* 16-bit DMA channel compatibility */
 103 #define IOAT_DMA_COMP_V1                        0x0001  /* Compatibility with DMA version 1 */
 104 #define IOAT_DMA_COMP_V2                        0x0002  /* Compatibility with DMA version 2 */
 105
 106
 107 #define IOAT1_CHANSTS_OFFSET            0x04    /* 64-bit Channel Status Register */
 108 #define IOAT2_CHANSTS_OFFSET            0x08    /* 64-bit Channel Status Register */
 109 #define IOAT_CHANSTS_OFFSET(ver)                ((ver) < IOAT_VER_2_0 \
 110                                                 ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET)
 111 #define IOAT1_CHANSTS_OFFSET_LOW        0x04
 112 #define IOAT2_CHANSTS_OFFSET_LOW        0x08
 113 #define IOAT_CHANSTS_OFFSET_LOW(ver)            ((ver) < IOAT_VER_2_0 \
 114                                                 ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW)
 115 #define IOAT1_CHANSTS_OFFSET_HIGH       0x08
 116 #define IOAT2_CHANSTS_OFFSET_HIGH       0x0C
 117 #define IOAT_CHANSTS_OFFSET_HIGH(ver)           ((ver) < IOAT_VER_2_0 \
 118                                                 ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH)
 119 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR  (~0x3fULL)
 120 #define IOAT_CHANSTS_SOFT_ERR                   0x10ULL
 121 #define IOAT_CHANSTS_UNAFFILIATED_ERR           0x8ULL
 122 #define IOAT_CHANSTS_STATUS     0x7ULL
 123 #define IOAT_CHANSTS_ACTIVE     0x0
 124 #define IOAT_CHANSTS_DONE       0x1
 125 #define IOAT_CHANSTS_SUSPENDED  0x2
 126 #define IOAT_CHANSTS_HALTED     0x3
 127
 128
 129
 130 #define IOAT_CHAN_DMACOUNT_OFFSET       0x06    /* 16-bit DMA Count register */
 131
 132 #define IOAT_DCACTRL_OFFSET         0x30   /* 32 bit Direct Cache Access Control Register */
 133 #define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000
 134 #define IOAT_DCACTRL_TARGET_CPU_MASK   0xFFFF /* APIC ID */
 135
 136 /* CB DCA Memory Space Registers */
 137 #define IOAT_DCAOFFSET_OFFSET       0x14
 138 /* CB_BAR + IOAT_DCAOFFSET value */
 139 #define IOAT_DCA_VER_OFFSET         0x00
 140 #define IOAT_DCA_VER_MAJOR_MASK     0xF0
 141 #define IOAT_DCA_VER_MINOR_MASK     0x0F
 142
 143 #define IOAT_DCA_COMP_OFFSET        0x02
 144 #define IOAT_DCA_COMP_V1            0x1
 145
 146 #define IOAT_FSB_CAPABILITY_OFFSET  0x04
 147 #define IOAT_FSB_CAPABILITY_PREFETCH    0x1
 148
 149 #define IOAT_PCI_CAPABILITY_OFFSET  0x06
 150 #define IOAT_PCI_CAPABILITY_MEMWR   0x1
 151
 152 #define IOAT_FSB_CAP_ENABLE_OFFSET  0x08
 153 #define IOAT_FSB_CAP_ENABLE_PREFETCH    0x1
 154
 155 #define IOAT_PCI_CAP_ENABLE_OFFSET  0x0A
 156 #define IOAT_PCI_CAP_ENABLE_MEMWR   0x1
 157
 158 #define IOAT_APICID_TAG_MAP_OFFSET  0x0C
 159 #define IOAT_APICID_TAG_MAP_TAG0    0x0000000F
 160 #define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0
 161 #define IOAT_APICID_TAG_MAP_TAG1    0x000000F0
 162 #define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4
 163 #define IOAT_APICID_TAG_MAP_TAG2    0x00000F00
 164 #define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8
 165 #define IOAT_APICID_TAG_MAP_TAG3    0x0000F000
 166 #define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12
 167 #define IOAT_APICID_TAG_MAP_TAG4    0x000F0000
 168 #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16
 169 #define IOAT_APICID_TAG_CB2_VALID   0x8080808080
 170
 171 #define IOAT_DCA_GREQID_OFFSET      0x10
 172 #define IOAT_DCA_GREQID_SIZE        0x04
 173 #define IOAT_DCA_GREQID_MASK        0xFFFF
 174 #define IOAT_DCA_GREQID_IGNOREFUN   0x10000000
 175 #define IOAT_DCA_GREQID_VALID       0x20000000
 176 #define IOAT_DCA_GREQID_LASTID      0x80000000
 177
 178 #define IOAT3_CSI_CAPABILITY_OFFSET 0x08
 179 #define IOAT3_CSI_CAPABILITY_PREFETCH    0x1
 180
 181 #define IOAT3_PCI_CAPABILITY_OFFSET 0x0A
 182 #define IOAT3_PCI_CAPABILITY_MEMWR  0x1
 183
 184 #define IOAT3_CSI_CONTROL_OFFSET    0x0C
 185 #define IOAT3_CSI_CONTROL_PREFETCH  0x1
 186
 187 #define IOAT3_PCI_CONTROL_OFFSET    0x0E
 188 #define IOAT3_PCI_CONTROL_MEMWR     0x1
 189
 190 #define IOAT3_APICID_TAG_MAP_OFFSET 0x10
 191 #define IOAT3_APICID_TAG_MAP_OFFSET_LOW  0x10
 192 #define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14
 193
 194 #define IOAT3_DCA_GREQID_OFFSET     0x02
 195
 196 #define IOAT1_CHAINADDR_OFFSET          0x0C    /* 64-bit Descriptor Chain Address Register */
 197 #define IOAT2_CHAINADDR_OFFSET          0x10    /* 64-bit Descriptor Chain Address Register */
 198 #define IOAT_CHAINADDR_OFFSET(ver)              ((ver) < IOAT_VER_2_0 \
 199                                                 ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET)
 200 #define IOAT1_CHAINADDR_OFFSET_LOW      0x0C
 201 #define IOAT2_CHAINADDR_OFFSET_LOW      0x10
 202 #define IOAT_CHAINADDR_OFFSET_LOW(ver)          ((ver) < IOAT_VER_2_0 \
 203                                                 ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW)
 204 #define IOAT1_CHAINADDR_OFFSET_HIGH     0x10
 205 #define IOAT2_CHAINADDR_OFFSET_HIGH     0x14
 206 #define IOAT_CHAINADDR_OFFSET_HIGH(ver)         ((ver) < IOAT_VER_2_0 \
 207                                                 ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH)
 208
 209 #define IOAT1_CHANCMD_OFFSET            0x14    /*  8-bit DMA Channel Command Register */
 210 #define IOAT2_CHANCMD_OFFSET            0x04    /*  8-bit DMA Channel Command Register */
 211 #define IOAT_CHANCMD_OFFSET(ver)                ((ver) < IOAT_VER_2_0 \
 212                                                 ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET)
 213 #define IOAT_CHANCMD_RESET                      0x20
 214 #define IOAT_CHANCMD_RESUME                     0x10
 215 #define IOAT_CHANCMD_ABORT                      0x08
 216 #define IOAT_CHANCMD_SUSPEND                    0x04
 217 #define IOAT_CHANCMD_APPEND                     0x02
 218 #define IOAT_CHANCMD_START                      0x01
 219
 220 #define IOAT_CHANCMP_OFFSET                     0x18    /* 64-bit Channel Completion Address Register */
 221 #define IOAT_CHANCMP_OFFSET_LOW                 0x18
 222 #define IOAT_CHANCMP_OFFSET_HIGH                0x1C
 223
 224 #define IOAT_CDAR_OFFSET                        0x20    /* 64-bit Current Descriptor Address Register */
 225 #define IOAT_CDAR_OFFSET_LOW                    0x20
 226 #define IOAT_CDAR_OFFSET_HIGH                   0x24
 227
 228 #define IOAT_CHANERR_OFFSET                     0x28    /* 32-bit Channel Error Register */
 229 #define IOAT_CHANERR_SRC_ADDR_ERR       0x0001
 230 #define IOAT_CHANERR_DEST_ADDR_ERR      0x0002
 231 #define IOAT_CHANERR_NEXT_ADDR_ERR      0x0004
 232 #define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR        0x0008
 233 #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR       0x0010
 234 #define IOAT_CHANERR_CHANCMD_ERR                0x0020
 235 #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR   0x0040
 236 #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR       0x0080
 237 #define IOAT_CHANERR_READ_DATA_ERR              0x0100
 238 #define IOAT_CHANERR_WRITE_DATA_ERR             0x0200
 239 #define IOAT_CHANERR_CONTROL_ERR        0x0400
 240 #define IOAT_CHANERR_LENGTH_ERR 0x0800
 241 #define IOAT_CHANERR_COMPLETION_ADDR_ERR        0x1000
 242 #define IOAT_CHANERR_INT_CONFIGURATION_ERR      0x2000
 243 #define IOAT_CHANERR_SOFT_ERR                   0x4000
 244 #define IOAT_CHANERR_UNAFFILIATED_ERR           0x8000
 245 #define IOAT_CHANERR_XOR_P_OR_CRC_ERR           0x10000
 246 #define IOAT_CHANERR_XOR_Q_ERR                  0x20000
 247 #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR       0x40000
 248
 249 #define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR)
 250
 251 #define IOAT_CHANERR_MASK_OFFSET                0x2C    /* 32-bit Channel Error Register */
 252
 253 #endif /* _IOAT_REGISTERS_H_ */