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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / drivers / gpio / gpio-samsung.c
bloba85e00bf9834c01ac6cb0ebfe6883176f10c06cb
1 /*
2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * SAMSUNG - GPIOlib support
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
19 #include <linux/io.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
27 #include <linux/of.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
30
31 #include <asm/irq.h>
32
33 #include <mach/map.h>
34 #include <mach/regs-gpio.h>
35
36 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
37 #include <mach/gpio-samsung.h>
38 #endif
39
40 #include <plat/cpu.h>
41 #include <plat/gpio-core.h>
42 #include <plat/gpio-cfg.h>
43 #include <plat/gpio-cfg-helpers.h>
44 #include <plat/pm.h>
45
46 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
47 unsigned int off, samsung_gpio_pull_t pull)
48 {
49 void __iomem *reg = chip->base + 0x08;
50 int shift = off * 2;
51 u32 pup;
52
53 pup = __raw_readl(reg);
54 pup &= ~(3 << shift);
55 pup |= pull << shift;
56 __raw_writel(pup, reg);
57
58 return 0;
59 }
60
61 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
62 unsigned int off)
63 {
64 void __iomem *reg = chip->base + 0x08;
65 int shift = off * 2;
66 u32 pup = __raw_readl(reg);
67
68 pup >>= shift;
69 pup &= 0x3;
70
71 return (__force samsung_gpio_pull_t)pup;
72 }
73
74 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
75 unsigned int off, samsung_gpio_pull_t pull)
76 {
77 switch (pull) {
78 case S3C_GPIO_PULL_NONE:
79 pull = 0x01;
80 break;
81 case S3C_GPIO_PULL_UP:
82 pull = 0x00;
83 break;
84 case S3C_GPIO_PULL_DOWN:
85 pull = 0x02;
86 break;
87 }
88 return samsung_gpio_setpull_updown(chip, off, pull);
89 }
90
91 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
92 unsigned int off)
93 {
94 samsung_gpio_pull_t pull;
95
96 pull = samsung_gpio_getpull_updown(chip, off);
97
98 switch (pull) {
99 case 0x00:
100 pull = S3C_GPIO_PULL_UP;
101 break;
102 case 0x01:
103 case 0x03:
104 pull = S3C_GPIO_PULL_NONE;
105 break;
106 case 0x02:
107 pull = S3C_GPIO_PULL_DOWN;
108 break;
109 }
110
111 return pull;
112 }
113
114 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
115 unsigned int off, samsung_gpio_pull_t pull,
116 samsung_gpio_pull_t updown)
117 {
118 void __iomem *reg = chip->base + 0x08;
119 u32 pup = __raw_readl(reg);
120
121 if (pull == updown)
122 pup &= ~(1 << off);
123 else if (pull == S3C_GPIO_PULL_NONE)
124 pup |= (1 << off);
125 else
126 return -EINVAL;
127
128 __raw_writel(pup, reg);
129 return 0;
130 }
131
132 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
133 unsigned int off,
134 samsung_gpio_pull_t updown)
135 {
136 void __iomem *reg = chip->base + 0x08;
137 u32 pup = __raw_readl(reg);
138
139 pup &= (1 << off);
140 return pup ? S3C_GPIO_PULL_NONE : updown;
141 }
142
143 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
144 unsigned int off)
145 {
146 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
147 }
148
149 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
150 unsigned int off, samsung_gpio_pull_t pull)
151 {
152 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
153 }
154
155 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
156 unsigned int off)
157 {
158 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
159 }
160
161 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
162 unsigned int off, samsung_gpio_pull_t pull)
163 {
164 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
165 }
166
167 /*
168 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
169 * @chip: The gpio chip that is being configured.
170 * @off: The offset for the GPIO being configured.
171 * @cfg: The configuration value to set.
172 *
173 * This helper deal with the GPIO cases where the control register
174 * has two bits of configuration per gpio, which have the following
175 * functions:
176 * 00 = input
177 * 01 = output
178 * 1x = special function
179 */
180
181 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
182 unsigned int off, unsigned int cfg)
183 {
184 void __iomem *reg = chip->base;
185 unsigned int shift = off * 2;
186 u32 con;
187
188 if (samsung_gpio_is_cfg_special(cfg)) {
189 cfg &= 0xf;
190 if (cfg > 3)
191 return -EINVAL;
192
193 cfg <<= shift;
194 }
195
196 con = __raw_readl(reg);
197 con &= ~(0x3 << shift);
198 con |= cfg;
199 __raw_writel(con, reg);
200
201 return 0;
202 }
203
204 /*
205 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
206 * @chip: The gpio chip that is being configured.
207 * @off: The offset for the GPIO being configured.
208 *
209 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
210 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
211 * S3C_GPIO_SPECIAL() macro.
212 */
213
214 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
215 unsigned int off)
216 {
217 u32 con;
218
219 con = __raw_readl(chip->base);
220 con >>= off * 2;
221 con &= 3;
222
223 /* this conversion works for IN and OUT as well as special mode */
224 return S3C_GPIO_SPECIAL(con);
225 }
226
227 /*
228 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
229 * @chip: The gpio chip that is being configured.
230 * @off: The offset for the GPIO being configured.
231 * @cfg: The configuration value to set.
232 *
233 * This helper deal with the GPIO cases where the control register has 4 bits
234 * of control per GPIO, generally in the form of:
235 * 0000 = Input
236 * 0001 = Output
237 * others = Special functions (dependent on bank)
238 *
239 * Note, since the code to deal with the case where there are two control
240 * registers instead of one, we do not have a separate set of functions for
241 * each case.
242 */
243
244 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
245 unsigned int off, unsigned int cfg)
246 {
247 void __iomem *reg = chip->base;
248 unsigned int shift = (off & 7) * 4;
249 u32 con;
250
251 if (off < 8 && chip->chip.ngpio > 8)
252 reg -= 4;
253
254 if (samsung_gpio_is_cfg_special(cfg)) {
255 cfg &= 0xf;
256 cfg <<= shift;
257 }
258
259 con = __raw_readl(reg);
260 con &= ~(0xf << shift);
261 con |= cfg;
262 __raw_writel(con, reg);
263
264 return 0;
265 }
266
267 /*
268 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
269 * @chip: The gpio chip that is being configured.
270 * @off: The offset for the GPIO being configured.
271 *
272 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
273 * register setting into a value the software can use, such as could be passed
274 * to samsung_gpio_setcfg_4bit().
275 *
276 * @sa samsung_gpio_getcfg_2bit
277 */
278
279 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
280 unsigned int off)
281 {
282 void __iomem *reg = chip->base;
283 unsigned int shift = (off & 7) * 4;
284 u32 con;
285
286 if (off < 8 && chip->chip.ngpio > 8)
287 reg -= 4;
288
289 con = __raw_readl(reg);
290 con >>= shift;
291 con &= 0xf;
292
293 /* this conversion works for IN and OUT as well as special mode */
294 return S3C_GPIO_SPECIAL(con);
295 }
296
297 #ifdef CONFIG_PLAT_S3C24XX
298 /*
299 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
300 * @chip: The gpio chip that is being configured.
301 * @off: The offset for the GPIO being configured.
302 * @cfg: The configuration value to set.
303 *
304 * This helper deal with the GPIO cases where the control register
305 * has one bit of configuration for the gpio, where setting the bit
306 * means the pin is in special function mode and unset means output.
307 */
308
309 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
310 unsigned int off, unsigned int cfg)
311 {
312 void __iomem *reg = chip->base;
313 unsigned int shift = off;
314 u32 con;
315
316 if (samsung_gpio_is_cfg_special(cfg)) {
317 cfg &= 0xf;
318
319 /* Map output to 0, and SFN2 to 1 */
320 cfg -= 1;
321 if (cfg > 1)
322 return -EINVAL;
323
324 cfg <<= shift;
325 }
326
327 con = __raw_readl(reg);
328 con &= ~(0x1 << shift);
329 con |= cfg;
330 __raw_writel(con, reg);
331
332 return 0;
333 }
334
335 /*
336 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
337 * @chip: The gpio chip that is being configured.
338 * @off: The offset for the GPIO being configured.
339 *
340 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
341 * GPIO configuration value.
342 *
343 * @sa samsung_gpio_getcfg_2bit
344 * @sa samsung_gpio_getcfg_4bit
345 */
346
347 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
348 unsigned int off)
349 {
350 u32 con;
351
352 con = __raw_readl(chip->base);
353 con >>= off;
354 con &= 1;
355 con++;
356
357 return S3C_GPIO_SFN(con);
358 }
359 #endif
360
361 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
362 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
363 unsigned int off, unsigned int cfg)
364 {
365 void __iomem *reg = chip->base;
366 unsigned int shift;
367 u32 con;
368
369 switch (off) {
370 case 0:
371 case 1:
372 case 2:
373 case 3:
374 case 4:
375 case 5:
376 shift = (off & 7) * 4;
377 reg -= 4;
378 break;
379 case 6:
380 shift = ((off + 1) & 7) * 4;
381 reg -= 4;
382 default:
383 shift = ((off + 1) & 7) * 4;
384 break;
385 }
386
387 if (samsung_gpio_is_cfg_special(cfg)) {
388 cfg &= 0xf;
389 cfg <<= shift;
390 }
391
392 con = __raw_readl(reg);
393 con &= ~(0xf << shift);
394 con |= cfg;
395 __raw_writel(con, reg);
396
397 return 0;
398 }
399 #endif
400
401 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
402 int nr_chips)
403 {
404 for (; nr_chips > 0; nr_chips--, chipcfg++) {
405 if (!chipcfg->set_config)
406 chipcfg->set_config = samsung_gpio_setcfg_4bit;
407 if (!chipcfg->get_config)
408 chipcfg->get_config = samsung_gpio_getcfg_4bit;
409 if (!chipcfg->set_pull)
410 chipcfg->set_pull = samsung_gpio_setpull_updown;
411 if (!chipcfg->get_pull)
412 chipcfg->get_pull = samsung_gpio_getpull_updown;
413 }
414 }
415
416 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
417 .set_config = samsung_gpio_setcfg_2bit,
418 .get_config = samsung_gpio_getcfg_2bit,
419 };
420
421 #ifdef CONFIG_PLAT_S3C24XX
422 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
423 .set_config = s3c24xx_gpio_setcfg_abank,
424 .get_config = s3c24xx_gpio_getcfg_abank,
425 };
426 #endif
427
428 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
429 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
430 .cfg_eint = 0x3,
431 .set_config = s5p64x0_gpio_setcfg_rbank,
432 .get_config = samsung_gpio_getcfg_4bit,
433 .set_pull = samsung_gpio_setpull_updown,
434 .get_pull = samsung_gpio_getpull_updown,
435 };
436 #endif
437
438 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
439 [0] = {
440 .cfg_eint = 0x0,
441 },
442 [1] = {
443 .cfg_eint = 0x3,
444 },
445 [2] = {
446 .cfg_eint = 0x7,
447 },
448 [3] = {
449 .cfg_eint = 0xF,
450 },
451 [4] = {
452 .cfg_eint = 0x0,
453 .set_config = samsung_gpio_setcfg_2bit,
454 .get_config = samsung_gpio_getcfg_2bit,
455 },
456 [5] = {
457 .cfg_eint = 0x2,
458 .set_config = samsung_gpio_setcfg_2bit,
459 .get_config = samsung_gpio_getcfg_2bit,
460 },
461 [6] = {
462 .cfg_eint = 0x3,
463 .set_config = samsung_gpio_setcfg_2bit,
464 .get_config = samsung_gpio_getcfg_2bit,
465 },
466 [7] = {
467 .set_config = samsung_gpio_setcfg_2bit,
468 .get_config = samsung_gpio_getcfg_2bit,
469 },
470 };
471
472 /*
473 * Default routines for controlling GPIO, based on the original S3C24XX
474 * GPIO functions which deal with the case where each gpio bank of the
475 * chip is as following:
476 *
477 * base + 0x00: Control register, 2 bits per gpio
478 * gpio n: 2 bits starting at (2*n)
479 * 00 = input, 01 = output, others mean special-function
480 * base + 0x04: Data register, 1 bit per gpio
481 * bit n: data bit n
482 */
483
484 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
485 {
486 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
487 void __iomem *base = ourchip->base;
488 unsigned long flags;
489 unsigned long con;
490
491 samsung_gpio_lock(ourchip, flags);
492
493 con = __raw_readl(base + 0x00);
494 con &= ~(3 << (offset * 2));
495
496 __raw_writel(con, base + 0x00);
497
498 samsung_gpio_unlock(ourchip, flags);
499 return 0;
500 }
501
502 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
503 unsigned offset, int value)
504 {
505 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
506 void __iomem *base = ourchip->base;
507 unsigned long flags;
508 unsigned long dat;
509 unsigned long con;
510
511 samsung_gpio_lock(ourchip, flags);
512
513 dat = __raw_readl(base + 0x04);
514 dat &= ~(1 << offset);
515 if (value)
516 dat |= 1 << offset;
517 __raw_writel(dat, base + 0x04);
518
519 con = __raw_readl(base + 0x00);
520 con &= ~(3 << (offset * 2));
521 con |= 1 << (offset * 2);
522
523 __raw_writel(con, base + 0x00);
524 __raw_writel(dat, base + 0x04);
525
526 samsung_gpio_unlock(ourchip, flags);
527 return 0;
528 }
529
530 /*
531 * The samsung_gpiolib_4bit routines are to control the gpio banks where
532 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
533 * following example:
534 *
535 * base + 0x00: Control register, 4 bits per gpio
536 * gpio n: 4 bits starting at (4*n)
537 * 0000 = input, 0001 = output, others mean special-function
538 * base + 0x04: Data register, 1 bit per gpio
539 * bit n: data bit n
540 *
541 * Note, since the data register is one bit per gpio and is at base + 0x4
542 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
543 * state of the output.
544 */
545
546 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
547 unsigned int offset)
548 {
549 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
550 void __iomem *base = ourchip->base;
551 unsigned long con;
552
553 con = __raw_readl(base + GPIOCON_OFF);
554 if (ourchip->bitmap_gpio_int & BIT(offset))
555 con |= 0xf << con_4bit_shift(offset);
556 else
557 con &= ~(0xf << con_4bit_shift(offset));
558 __raw_writel(con, base + GPIOCON_OFF);
559
560 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
561
562 return 0;
563 }
564
565 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
566 unsigned int offset, int value)
567 {
568 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
569 void __iomem *base = ourchip->base;
570 unsigned long con;
571 unsigned long dat;
572
573 con = __raw_readl(base + GPIOCON_OFF);
574 con &= ~(0xf << con_4bit_shift(offset));
575 con |= 0x1 << con_4bit_shift(offset);
576
577 dat = __raw_readl(base + GPIODAT_OFF);
578
579 if (value)
580 dat |= 1 << offset;
581 else
582 dat &= ~(1 << offset);
583
584 __raw_writel(dat, base + GPIODAT_OFF);
585 __raw_writel(con, base + GPIOCON_OFF);
586 __raw_writel(dat, base + GPIODAT_OFF);
587
588 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
589
590 return 0;
591 }
592
593 /*
594 * The next set of routines are for the case where the GPIO configuration
595 * registers are 4 bits per GPIO but there is more than one register (the
596 * bank has more than 8 GPIOs.
597 *
598 * This case is the similar to the 4 bit case, but the registers are as
599 * follows:
600 *
601 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
602 * gpio n: 4 bits starting at (4*n)
603 * 0000 = input, 0001 = output, others mean special-function
604 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
605 * gpio n: 4 bits starting at (4*n)
606 * 0000 = input, 0001 = output, others mean special-function
607 * base + 0x08: Data register, 1 bit per gpio
608 * bit n: data bit n
609 *
610 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
611 * routines we store the 'base + 0x4' address so that these routines see
612 * the data register at ourchip->base + 0x04.
613 */
614
615 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
616 unsigned int offset)
617 {
618 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
619 void __iomem *base = ourchip->base;
620 void __iomem *regcon = base;
621 unsigned long con;
622
623 if (offset > 7)
624 offset -= 8;
625 else
626 regcon -= 4;
627
628 con = __raw_readl(regcon);
629 con &= ~(0xf << con_4bit_shift(offset));
630 __raw_writel(con, regcon);
631
632 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
633
634 return 0;
635 }
636
637 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
638 unsigned int offset, int value)
639 {
640 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
641 void __iomem *base = ourchip->base;
642 void __iomem *regcon = base;
643 unsigned long con;
644 unsigned long dat;
645 unsigned con_offset = offset;
646
647 if (con_offset > 7)
648 con_offset -= 8;
649 else
650 regcon -= 4;
651
652 con = __raw_readl(regcon);
653 con &= ~(0xf << con_4bit_shift(con_offset));
654 con |= 0x1 << con_4bit_shift(con_offset);
655
656 dat = __raw_readl(base + GPIODAT_OFF);
657
658 if (value)
659 dat |= 1 << offset;
660 else
661 dat &= ~(1 << offset);
662
663 __raw_writel(dat, base + GPIODAT_OFF);
664 __raw_writel(con, regcon);
665 __raw_writel(dat, base + GPIODAT_OFF);
666
667 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
668
669 return 0;
670 }
671
672 #ifdef CONFIG_PLAT_S3C24XX
673 /* The next set of routines are for the case of s3c24xx bank a */
674
675 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
676 {
677 return -EINVAL;
678 }
679
680 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
681 unsigned offset, int value)
682 {
683 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
684 void __iomem *base = ourchip->base;
685 unsigned long flags;
686 unsigned long dat;
687 unsigned long con;
688
689 local_irq_save(flags);
690
691 con = __raw_readl(base + 0x00);
692 dat = __raw_readl(base + 0x04);
693
694 dat &= ~(1 << offset);
695 if (value)
696 dat |= 1 << offset;
697
698 __raw_writel(dat, base + 0x04);
699
700 con &= ~(1 << offset);
701
702 __raw_writel(con, base + 0x00);
703 __raw_writel(dat, base + 0x04);
704
705 local_irq_restore(flags);
706 return 0;
707 }
708 #endif
709
710 /* The next set of routines are for the case of s5p64x0 bank r */
711
712 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
713 unsigned int offset)
714 {
715 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
716 void __iomem *base = ourchip->base;
717 void __iomem *regcon = base;
718 unsigned long con;
719 unsigned long flags;
720
721 switch (offset) {
722 case 6:
723 offset += 1;
724 case 0:
725 case 1:
726 case 2:
727 case 3:
728 case 4:
729 case 5:
730 regcon -= 4;
731 break;
732 default:
733 offset -= 7;
734 break;
735 }
736
737 samsung_gpio_lock(ourchip, flags);
738
739 con = __raw_readl(regcon);
740 con &= ~(0xf << con_4bit_shift(offset));
741 __raw_writel(con, regcon);
742
743 samsung_gpio_unlock(ourchip, flags);
744
745 return 0;
746 }
747
748 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
749 unsigned int offset, int value)
750 {
751 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
752 void __iomem *base = ourchip->base;
753 void __iomem *regcon = base;
754 unsigned long con;
755 unsigned long dat;
756 unsigned long flags;
757 unsigned con_offset = offset;
758
759 switch (con_offset) {
760 case 6:
761 con_offset += 1;
762 case 0:
763 case 1:
764 case 2:
765 case 3:
766 case 4:
767 case 5:
768 regcon -= 4;
769 break;
770 default:
771 con_offset -= 7;
772 break;
773 }
774
775 samsung_gpio_lock(ourchip, flags);
776
777 con = __raw_readl(regcon);
778 con &= ~(0xf << con_4bit_shift(con_offset));
779 con |= 0x1 << con_4bit_shift(con_offset);
780
781 dat = __raw_readl(base + GPIODAT_OFF);
782 if (value)
783 dat |= 1 << offset;
784 else
785 dat &= ~(1 << offset);
786
787 __raw_writel(con, regcon);
788 __raw_writel(dat, base + GPIODAT_OFF);
789
790 samsung_gpio_unlock(ourchip, flags);
791
792 return 0;
793 }
794
795 static void samsung_gpiolib_set(struct gpio_chip *chip,
796 unsigned offset, int value)
797 {
798 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
799 void __iomem *base = ourchip->base;
800 unsigned long flags;
801 unsigned long dat;
802
803 samsung_gpio_lock(ourchip, flags);
804
805 dat = __raw_readl(base + 0x04);
806 dat &= ~(1 << offset);
807 if (value)
808 dat |= 1 << offset;
809 __raw_writel(dat, base + 0x04);
810
811 samsung_gpio_unlock(ourchip, flags);
812 }
813
814 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
815 {
816 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
817 unsigned long val;
818
819 val = __raw_readl(ourchip->base + 0x04);
820 val >>= offset;
821 val &= 1;
822
823 return val;
824 }
825
826 /*
827 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
828 * for use with the configuration calls, and other parts of the s3c gpiolib
829 * support code.
830 *
831 * Not all s3c support code will need this, as some configurations of cpu
832 * may only support one or two different configuration options and have an
833 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
834 * the machine support file should provide its own samsung_gpiolib_getchip()
835 * and any other necessary functions.
836 */
837
838 #ifdef CONFIG_S3C_GPIO_TRACK
839 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
840
841 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
842 {
843 unsigned int gpn;
844 int i;
845
846 gpn = chip->chip.base;
847 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
848 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
849 s3c_gpios[gpn] = chip;
850 }
851 }
852 #endif /* CONFIG_S3C_GPIO_TRACK */
853
854 /*
855 * samsung_gpiolib_add() - add the Samsung gpio_chip.
856 * @chip: The chip to register
857 *
858 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
859 * information and makes the necessary alterations for the platform and
860 * notes the information for use with the configuration systems and any
861 * other parts of the system.
862 */
863
864 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
865 {
866 struct gpio_chip *gc = &chip->chip;
867 int ret;
868
869 BUG_ON(!chip->base);
870 BUG_ON(!gc->label);
871 BUG_ON(!gc->ngpio);
872
873 spin_lock_init(&chip->lock);
874
875 if (!gc->direction_input)
876 gc->direction_input = samsung_gpiolib_2bit_input;
877 if (!gc->direction_output)
878 gc->direction_output = samsung_gpiolib_2bit_output;
879 if (!gc->set)
880 gc->set = samsung_gpiolib_set;
881 if (!gc->get)
882 gc->get = samsung_gpiolib_get;
883
884 #ifdef CONFIG_PM
885 if (chip->pm != NULL) {
886 if (!chip->pm->save || !chip->pm->resume)
887 pr_err("gpio: %s has missing PM functions\n",
888 gc->label);
889 } else
890 pr_err("gpio: %s has no PM function\n", gc->label);
891 #endif
892
893 /* gpiochip_add() prints own failure message on error. */
894 ret = gpiochip_add(gc);
895 if (ret >= 0)
896 s3c_gpiolib_track(chip);
897 }
898
899 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
900 int nr_chips, void __iomem *base)
901 {
902 int i;
903 struct gpio_chip *gc = &chip->chip;
904
905 for (i = 0 ; i < nr_chips; i++, chip++) {
906 /* skip banks not present on SoC */
907 if (chip->chip.base >= S3C_GPIO_END)
908 continue;
909
910 if (!chip->config)
911 chip->config = &s3c24xx_gpiocfg_default;
912 if (!chip->pm)
913 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
914 if ((base != NULL) && (chip->base == NULL))
915 chip->base = base + ((i) * 0x10);
916
917 if (!gc->direction_input)
918 gc->direction_input = samsung_gpiolib_2bit_input;
919 if (!gc->direction_output)
920 gc->direction_output = samsung_gpiolib_2bit_output;
921
922 samsung_gpiolib_add(chip);
923 }
924 }
925
926 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
927 int nr_chips, void __iomem *base,
928 unsigned int offset)
929 {
930 int i;
931
932 for (i = 0 ; i < nr_chips; i++, chip++) {
933 chip->chip.direction_input = samsung_gpiolib_2bit_input;
934 chip->chip.direction_output = samsung_gpiolib_2bit_output;
935
936 if (!chip->config)
937 chip->config = &samsung_gpio_cfgs[7];
938 if (!chip->pm)
939 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
940 if ((base != NULL) && (chip->base == NULL))
941 chip->base = base + ((i) * offset);
942
943 samsung_gpiolib_add(chip);
944 }
945 }
946
947 /*
948 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
949 * @chip: The gpio chip that is being configured.
950 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
951 *
952 * This helper deal with the GPIO cases where the control register has 4 bits
953 * of control per GPIO, generally in the form of:
954 * 0000 = Input
955 * 0001 = Output
956 * others = Special functions (dependent on bank)
957 *
958 * Note, since the code to deal with the case where there are two control
959 * registers instead of one, we do not have a separate set of function
960 * (samsung_gpiolib_add_4bit2_chips)for each case.
961 */
962
963 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
964 int nr_chips, void __iomem *base)
965 {
966 int i;
967
968 for (i = 0 ; i < nr_chips; i++, chip++) {
969 chip->chip.direction_input = samsung_gpiolib_4bit_input;
970 chip->chip.direction_output = samsung_gpiolib_4bit_output;
971
972 if (!chip->config)
973 chip->config = &samsung_gpio_cfgs[2];
974 if (!chip->pm)
975 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
976 if ((base != NULL) && (chip->base == NULL))
977 chip->base = base + ((i) * 0x20);
978
979 chip->bitmap_gpio_int = 0;
980
981 samsung_gpiolib_add(chip);
982 }
983 }
984
985 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
986 int nr_chips)
987 {
988 for (; nr_chips > 0; nr_chips--, chip++) {
989 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
990 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
991
992 if (!chip->config)
993 chip->config = &samsung_gpio_cfgs[2];
994 if (!chip->pm)
995 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
996
997 samsung_gpiolib_add(chip);
998 }
999 }
1000
1001 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1002 int nr_chips)
1003 {
1004 for (; nr_chips > 0; nr_chips--, chip++) {
1005 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1006 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1007
1008 if (!chip->pm)
1009 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1010
1011 samsung_gpiolib_add(chip);
1012 }
1013 }
1014
1015 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1016 {
1017 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1018
1019 return samsung_chip->irq_base + offset;
1020 }
1021
1022 #ifdef CONFIG_PLAT_S3C24XX
1023 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1024 {
1025 if (offset < 4) {
1026 if (soc_is_s3c2412())
1027 return IRQ_EINT0_2412 + offset;
1028 else
1029 return IRQ_EINT0 + offset;
1030 }
1031
1032 if (offset < 8)
1033 return IRQ_EINT4 + offset - 4;
1034
1035 return -EINVAL;
1036 }
1037 #endif
1038
1039 #ifdef CONFIG_ARCH_S3C64XX
1040 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1041 {
1042 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1043 }
1044
1045 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1046 {
1047 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1048 }
1049 #endif
1050
1051 struct samsung_gpio_chip s3c24xx_gpios[] = {
1052 #ifdef CONFIG_PLAT_S3C24XX
1053 {
1054 .config = &s3c24xx_gpiocfg_banka,
1055 .chip = {
1056 .base = S3C2410_GPA(0),
1057 .owner = THIS_MODULE,
1058 .label = "GPIOA",
1059 .ngpio = 27,
1060 .direction_input = s3c24xx_gpiolib_banka_input,
1061 .direction_output = s3c24xx_gpiolib_banka_output,
1062 },
1063 }, {
1064 .chip = {
1065 .base = S3C2410_GPB(0),
1066 .owner = THIS_MODULE,
1067 .label = "GPIOB",
1068 .ngpio = 11,
1069 },
1070 }, {
1071 .chip = {
1072 .base = S3C2410_GPC(0),
1073 .owner = THIS_MODULE,
1074 .label = "GPIOC",
1075 .ngpio = 16,
1076 },
1077 }, {
1078 .chip = {
1079 .base = S3C2410_GPD(0),
1080 .owner = THIS_MODULE,
1081 .label = "GPIOD",
1082 .ngpio = 16,
1083 },
1084 }, {
1085 .chip = {
1086 .base = S3C2410_GPE(0),
1087 .label = "GPIOE",
1088 .owner = THIS_MODULE,
1089 .ngpio = 16,
1090 },
1091 }, {
1092 .chip = {
1093 .base = S3C2410_GPF(0),
1094 .owner = THIS_MODULE,
1095 .label = "GPIOF",
1096 .ngpio = 8,
1097 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1098 },
1099 }, {
1100 .irq_base = IRQ_EINT8,
1101 .chip = {
1102 .base = S3C2410_GPG(0),
1103 .owner = THIS_MODULE,
1104 .label = "GPIOG",
1105 .ngpio = 16,
1106 .to_irq = samsung_gpiolib_to_irq,
1107 },
1108 }, {
1109 .chip = {
1110 .base = S3C2410_GPH(0),
1111 .owner = THIS_MODULE,
1112 .label = "GPIOH",
1113 .ngpio = 15,
1114 },
1115 },
1116 /* GPIOS for the S3C2443 and later devices. */
1117 {
1118 .base = S3C2440_GPJCON,
1119 .chip = {
1120 .base = S3C2410_GPJ(0),
1121 .owner = THIS_MODULE,
1122 .label = "GPIOJ",
1123 .ngpio = 16,
1124 },
1125 }, {
1126 .base = S3C2443_GPKCON,
1127 .chip = {
1128 .base = S3C2410_GPK(0),
1129 .owner = THIS_MODULE,
1130 .label = "GPIOK",
1131 .ngpio = 16,
1132 },
1133 }, {
1134 .base = S3C2443_GPLCON,
1135 .chip = {
1136 .base = S3C2410_GPL(0),
1137 .owner = THIS_MODULE,
1138 .label = "GPIOL",
1139 .ngpio = 15,
1140 },
1141 }, {
1142 .base = S3C2443_GPMCON,
1143 .chip = {
1144 .base = S3C2410_GPM(0),
1145 .owner = THIS_MODULE,
1146 .label = "GPIOM",
1147 .ngpio = 2,
1148 },
1149 },
1150 #endif
1151 };
1152
1153 /*
1154 * GPIO bank summary:
1155 *
1156 * Bank GPIOs Style SlpCon ExtInt Group
1157 * A 8 4Bit Yes 1
1158 * B 7 4Bit Yes 1
1159 * C 8 4Bit Yes 2
1160 * D 5 4Bit Yes 3
1161 * E 5 4Bit Yes None
1162 * F 16 2Bit Yes 4 [1]
1163 * G 7 4Bit Yes 5
1164 * H 10 4Bit[2] Yes 6
1165 * I 16 2Bit Yes None
1166 * J 12 2Bit Yes None
1167 * K 16 4Bit[2] No None
1168 * L 15 4Bit[2] No None
1169 * M 6 4Bit No IRQ_EINT
1170 * N 16 2Bit No IRQ_EINT
1171 * O 16 2Bit Yes 7
1172 * P 15 2Bit Yes 8
1173 * Q 9 2Bit Yes 9
1174 *
1175 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1176 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1177 */
1178
1179 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1180 #ifdef CONFIG_ARCH_S3C64XX
1181 {
1182 .chip = {
1183 .base = S3C64XX_GPA(0),
1184 .ngpio = S3C64XX_GPIO_A_NR,
1185 .label = "GPA",
1186 },
1187 }, {
1188 .chip = {
1189 .base = S3C64XX_GPB(0),
1190 .ngpio = S3C64XX_GPIO_B_NR,
1191 .label = "GPB",
1192 },
1193 }, {
1194 .chip = {
1195 .base = S3C64XX_GPC(0),
1196 .ngpio = S3C64XX_GPIO_C_NR,
1197 .label = "GPC",
1198 },
1199 }, {
1200 .chip = {
1201 .base = S3C64XX_GPD(0),
1202 .ngpio = S3C64XX_GPIO_D_NR,
1203 .label = "GPD",
1204 },
1205 }, {
1206 .config = &samsung_gpio_cfgs[0],
1207 .chip = {
1208 .base = S3C64XX_GPE(0),
1209 .ngpio = S3C64XX_GPIO_E_NR,
1210 .label = "GPE",
1211 },
1212 }, {
1213 .base = S3C64XX_GPG_BASE,
1214 .chip = {
1215 .base = S3C64XX_GPG(0),
1216 .ngpio = S3C64XX_GPIO_G_NR,
1217 .label = "GPG",
1218 },
1219 }, {
1220 .base = S3C64XX_GPM_BASE,
1221 .config = &samsung_gpio_cfgs[1],
1222 .chip = {
1223 .base = S3C64XX_GPM(0),
1224 .ngpio = S3C64XX_GPIO_M_NR,
1225 .label = "GPM",
1226 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1227 },
1228 },
1229 #endif
1230 };
1231
1232 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1233 #ifdef CONFIG_ARCH_S3C64XX
1234 {
1235 .base = S3C64XX_GPH_BASE + 0x4,
1236 .chip = {
1237 .base = S3C64XX_GPH(0),
1238 .ngpio = S3C64XX_GPIO_H_NR,
1239 .label = "GPH",
1240 },
1241 }, {
1242 .base = S3C64XX_GPK_BASE + 0x4,
1243 .config = &samsung_gpio_cfgs[0],
1244 .chip = {
1245 .base = S3C64XX_GPK(0),
1246 .ngpio = S3C64XX_GPIO_K_NR,
1247 .label = "GPK",
1248 },
1249 }, {
1250 .base = S3C64XX_GPL_BASE + 0x4,
1251 .config = &samsung_gpio_cfgs[1],
1252 .chip = {
1253 .base = S3C64XX_GPL(0),
1254 .ngpio = S3C64XX_GPIO_L_NR,
1255 .label = "GPL",
1256 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1257 },
1258 },
1259 #endif
1260 };
1261
1262 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1263 #ifdef CONFIG_ARCH_S3C64XX
1264 {
1265 .base = S3C64XX_GPF_BASE,
1266 .config = &samsung_gpio_cfgs[6],
1267 .chip = {
1268 .base = S3C64XX_GPF(0),
1269 .ngpio = S3C64XX_GPIO_F_NR,
1270 .label = "GPF",
1271 },
1272 }, {
1273 .config = &samsung_gpio_cfgs[7],
1274 .chip = {
1275 .base = S3C64XX_GPI(0),
1276 .ngpio = S3C64XX_GPIO_I_NR,
1277 .label = "GPI",
1278 },
1279 }, {
1280 .config = &samsung_gpio_cfgs[7],
1281 .chip = {
1282 .base = S3C64XX_GPJ(0),
1283 .ngpio = S3C64XX_GPIO_J_NR,
1284 .label = "GPJ",
1285 },
1286 }, {
1287 .config = &samsung_gpio_cfgs[6],
1288 .chip = {
1289 .base = S3C64XX_GPO(0),
1290 .ngpio = S3C64XX_GPIO_O_NR,
1291 .label = "GPO",
1292 },
1293 }, {
1294 .config = &samsung_gpio_cfgs[6],
1295 .chip = {
1296 .base = S3C64XX_GPP(0),
1297 .ngpio = S3C64XX_GPIO_P_NR,
1298 .label = "GPP",
1299 },
1300 }, {
1301 .config = &samsung_gpio_cfgs[6],
1302 .chip = {
1303 .base = S3C64XX_GPQ(0),
1304 .ngpio = S3C64XX_GPIO_Q_NR,
1305 .label = "GPQ",
1306 },
1307 }, {
1308 .base = S3C64XX_GPN_BASE,
1309 .irq_base = IRQ_EINT(0),
1310 .config = &samsung_gpio_cfgs[5],
1311 .chip = {
1312 .base = S3C64XX_GPN(0),
1313 .ngpio = S3C64XX_GPIO_N_NR,
1314 .label = "GPN",
1315 .to_irq = samsung_gpiolib_to_irq,
1316 },
1317 },
1318 #endif
1319 };
1320
1321 /*
1322 * S5P6440 GPIO bank summary:
1323 *
1324 * Bank GPIOs Style SlpCon ExtInt Group
1325 * A 6 4Bit Yes 1
1326 * B 7 4Bit Yes 1
1327 * C 8 4Bit Yes 2
1328 * F 2 2Bit Yes 4 [1]
1329 * G 7 4Bit Yes 5
1330 * H 10 4Bit[2] Yes 6
1331 * I 16 2Bit Yes None
1332 * J 12 2Bit Yes None
1333 * N 16 2Bit No IRQ_EINT
1334 * P 8 2Bit Yes 8
1335 * R 15 4Bit[2] Yes 8
1336 */
1337
1338 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1339 #ifdef CONFIG_CPU_S5P6440
1340 {
1341 .chip = {
1342 .base = S5P6440_GPA(0),
1343 .ngpio = S5P6440_GPIO_A_NR,
1344 .label = "GPA",
1345 },
1346 }, {
1347 .chip = {
1348 .base = S5P6440_GPB(0),
1349 .ngpio = S5P6440_GPIO_B_NR,
1350 .label = "GPB",
1351 },
1352 }, {
1353 .chip = {
1354 .base = S5P6440_GPC(0),
1355 .ngpio = S5P6440_GPIO_C_NR,
1356 .label = "GPC",
1357 },
1358 }, {
1359 .base = S5P64X0_GPG_BASE,
1360 .chip = {
1361 .base = S5P6440_GPG(0),
1362 .ngpio = S5P6440_GPIO_G_NR,
1363 .label = "GPG",
1364 },
1365 },
1366 #endif
1367 };
1368
1369 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1370 #ifdef CONFIG_CPU_S5P6440
1371 {
1372 .base = S5P64X0_GPH_BASE + 0x4,
1373 .chip = {
1374 .base = S5P6440_GPH(0),
1375 .ngpio = S5P6440_GPIO_H_NR,
1376 .label = "GPH",
1377 },
1378 },
1379 #endif
1380 };
1381
1382 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1383 #ifdef CONFIG_CPU_S5P6440
1384 {
1385 .base = S5P64X0_GPR_BASE + 0x4,
1386 .config = &s5p64x0_gpio_cfg_rbank,
1387 .chip = {
1388 .base = S5P6440_GPR(0),
1389 .ngpio = S5P6440_GPIO_R_NR,
1390 .label = "GPR",
1391 },
1392 },
1393 #endif
1394 };
1395
1396 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1397 #ifdef CONFIG_CPU_S5P6440
1398 {
1399 .base = S5P64X0_GPF_BASE,
1400 .config = &samsung_gpio_cfgs[6],
1401 .chip = {
1402 .base = S5P6440_GPF(0),
1403 .ngpio = S5P6440_GPIO_F_NR,
1404 .label = "GPF",
1405 },
1406 }, {
1407 .base = S5P64X0_GPI_BASE,
1408 .config = &samsung_gpio_cfgs[4],
1409 .chip = {
1410 .base = S5P6440_GPI(0),
1411 .ngpio = S5P6440_GPIO_I_NR,
1412 .label = "GPI",
1413 },
1414 }, {
1415 .base = S5P64X0_GPJ_BASE,
1416 .config = &samsung_gpio_cfgs[4],
1417 .chip = {
1418 .base = S5P6440_GPJ(0),
1419 .ngpio = S5P6440_GPIO_J_NR,
1420 .label = "GPJ",
1421 },
1422 }, {
1423 .base = S5P64X0_GPN_BASE,
1424 .config = &samsung_gpio_cfgs[5],
1425 .chip = {
1426 .base = S5P6440_GPN(0),
1427 .ngpio = S5P6440_GPIO_N_NR,
1428 .label = "GPN",
1429 },
1430 }, {
1431 .base = S5P64X0_GPP_BASE,
1432 .config = &samsung_gpio_cfgs[6],
1433 .chip = {
1434 .base = S5P6440_GPP(0),
1435 .ngpio = S5P6440_GPIO_P_NR,
1436 .label = "GPP",
1437 },
1438 },
1439 #endif
1440 };
1441
1442 /*
1443 * S5P6450 GPIO bank summary:
1444 *
1445 * Bank GPIOs Style SlpCon ExtInt Group
1446 * A 6 4Bit Yes 1
1447 * B 7 4Bit Yes 1
1448 * C 8 4Bit Yes 2
1449 * D 8 4Bit Yes None
1450 * F 2 2Bit Yes None
1451 * G 14 4Bit[2] Yes 5
1452 * H 10 4Bit[2] Yes 6
1453 * I 16 2Bit Yes None
1454 * J 12 2Bit Yes None
1455 * K 5 4Bit Yes None
1456 * N 16 2Bit No IRQ_EINT
1457 * P 11 2Bit Yes 8
1458 * Q 14 2Bit Yes None
1459 * R 15 4Bit[2] Yes None
1460 * S 8 2Bit Yes None
1461 *
1462 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1463 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1464 */
1465
1466 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1467 #ifdef CONFIG_CPU_S5P6450
1468 {
1469 .chip = {
1470 .base = S5P6450_GPA(0),
1471 .ngpio = S5P6450_GPIO_A_NR,
1472 .label = "GPA",
1473 },
1474 }, {
1475 .chip = {
1476 .base = S5P6450_GPB(0),
1477 .ngpio = S5P6450_GPIO_B_NR,
1478 .label = "GPB",
1479 },
1480 }, {
1481 .chip = {
1482 .base = S5P6450_GPC(0),
1483 .ngpio = S5P6450_GPIO_C_NR,
1484 .label = "GPC",
1485 },
1486 }, {
1487 .chip = {
1488 .base = S5P6450_GPD(0),
1489 .ngpio = S5P6450_GPIO_D_NR,
1490 .label = "GPD",
1491 },
1492 }, {
1493 .base = S5P6450_GPK_BASE,
1494 .chip = {
1495 .base = S5P6450_GPK(0),
1496 .ngpio = S5P6450_GPIO_K_NR,
1497 .label = "GPK",
1498 },
1499 },
1500 #endif
1501 };
1502
1503 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1504 #ifdef CONFIG_CPU_S5P6450
1505 {
1506 .base = S5P64X0_GPG_BASE + 0x4,
1507 .chip = {
1508 .base = S5P6450_GPG(0),
1509 .ngpio = S5P6450_GPIO_G_NR,
1510 .label = "GPG",
1511 },
1512 }, {
1513 .base = S5P64X0_GPH_BASE + 0x4,
1514 .chip = {
1515 .base = S5P6450_GPH(0),
1516 .ngpio = S5P6450_GPIO_H_NR,
1517 .label = "GPH",
1518 },
1519 },
1520 #endif
1521 };
1522
1523 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1524 #ifdef CONFIG_CPU_S5P6450
1525 {
1526 .base = S5P64X0_GPR_BASE + 0x4,
1527 .config = &s5p64x0_gpio_cfg_rbank,
1528 .chip = {
1529 .base = S5P6450_GPR(0),
1530 .ngpio = S5P6450_GPIO_R_NR,
1531 .label = "GPR",
1532 },
1533 },
1534 #endif
1535 };
1536
1537 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1538 #ifdef CONFIG_CPU_S5P6450
1539 {
1540 .base = S5P64X0_GPF_BASE,
1541 .config = &samsung_gpio_cfgs[6],
1542 .chip = {
1543 .base = S5P6450_GPF(0),
1544 .ngpio = S5P6450_GPIO_F_NR,
1545 .label = "GPF",
1546 },
1547 }, {
1548 .base = S5P64X0_GPI_BASE,
1549 .config = &samsung_gpio_cfgs[4],
1550 .chip = {
1551 .base = S5P6450_GPI(0),
1552 .ngpio = S5P6450_GPIO_I_NR,
1553 .label = "GPI",
1554 },
1555 }, {
1556 .base = S5P64X0_GPJ_BASE,
1557 .config = &samsung_gpio_cfgs[4],
1558 .chip = {
1559 .base = S5P6450_GPJ(0),
1560 .ngpio = S5P6450_GPIO_J_NR,
1561 .label = "GPJ",
1562 },
1563 }, {
1564 .base = S5P64X0_GPN_BASE,
1565 .config = &samsung_gpio_cfgs[5],
1566 .chip = {
1567 .base = S5P6450_GPN(0),
1568 .ngpio = S5P6450_GPIO_N_NR,
1569 .label = "GPN",
1570 },
1571 }, {
1572 .base = S5P64X0_GPP_BASE,
1573 .config = &samsung_gpio_cfgs[6],
1574 .chip = {
1575 .base = S5P6450_GPP(0),
1576 .ngpio = S5P6450_GPIO_P_NR,
1577 .label = "GPP",
1578 },
1579 }, {
1580 .base = S5P6450_GPQ_BASE,
1581 .config = &samsung_gpio_cfgs[5],
1582 .chip = {
1583 .base = S5P6450_GPQ(0),
1584 .ngpio = S5P6450_GPIO_Q_NR,
1585 .label = "GPQ",
1586 },
1587 }, {
1588 .base = S5P6450_GPS_BASE,
1589 .config = &samsung_gpio_cfgs[6],
1590 .chip = {
1591 .base = S5P6450_GPS(0),
1592 .ngpio = S5P6450_GPIO_S_NR,
1593 .label = "GPS",
1594 },
1595 },
1596 #endif
1597 };
1598
1599 /*
1600 * S5PC100 GPIO bank summary:
1601 *
1602 * Bank GPIOs Style INT Type
1603 * A0 8 4Bit GPIO_INT0
1604 * A1 5 4Bit GPIO_INT1
1605 * B 8 4Bit GPIO_INT2
1606 * C 5 4Bit GPIO_INT3
1607 * D 7 4Bit GPIO_INT4
1608 * E0 8 4Bit GPIO_INT5
1609 * E1 6 4Bit GPIO_INT6
1610 * F0 8 4Bit GPIO_INT7
1611 * F1 8 4Bit GPIO_INT8
1612 * F2 8 4Bit GPIO_INT9
1613 * F3 4 4Bit GPIO_INT10
1614 * G0 8 4Bit GPIO_INT11
1615 * G1 3 4Bit GPIO_INT12
1616 * G2 7 4Bit GPIO_INT13
1617 * G3 7 4Bit GPIO_INT14
1618 * H0 8 4Bit WKUP_INT
1619 * H1 8 4Bit WKUP_INT
1620 * H2 8 4Bit WKUP_INT
1621 * H3 8 4Bit WKUP_INT
1622 * I 8 4Bit GPIO_INT15
1623 * J0 8 4Bit GPIO_INT16
1624 * J1 5 4Bit GPIO_INT17
1625 * J2 8 4Bit GPIO_INT18
1626 * J3 8 4Bit GPIO_INT19
1627 * J4 4 4Bit GPIO_INT20
1628 * K0 8 4Bit None
1629 * K1 6 4Bit None
1630 * K2 8 4Bit None
1631 * K3 8 4Bit None
1632 * L0 8 4Bit None
1633 * L1 8 4Bit None
1634 * L2 8 4Bit None
1635 * L3 8 4Bit None
1636 */
1637
1638 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1639 #ifdef CONFIG_CPU_S5PC100
1640 {
1641 .chip = {
1642 .base = S5PC100_GPA0(0),
1643 .ngpio = S5PC100_GPIO_A0_NR,
1644 .label = "GPA0",
1645 },
1646 }, {
1647 .chip = {
1648 .base = S5PC100_GPA1(0),
1649 .ngpio = S5PC100_GPIO_A1_NR,
1650 .label = "GPA1",
1651 },
1652 }, {
1653 .chip = {
1654 .base = S5PC100_GPB(0),
1655 .ngpio = S5PC100_GPIO_B_NR,
1656 .label = "GPB",
1657 },
1658 }, {
1659 .chip = {
1660 .base = S5PC100_GPC(0),
1661 .ngpio = S5PC100_GPIO_C_NR,
1662 .label = "GPC",
1663 },
1664 }, {
1665 .chip = {
1666 .base = S5PC100_GPD(0),
1667 .ngpio = S5PC100_GPIO_D_NR,
1668 .label = "GPD",
1669 },
1670 }, {
1671 .chip = {
1672 .base = S5PC100_GPE0(0),
1673 .ngpio = S5PC100_GPIO_E0_NR,
1674 .label = "GPE0",
1675 },
1676 }, {
1677 .chip = {
1678 .base = S5PC100_GPE1(0),
1679 .ngpio = S5PC100_GPIO_E1_NR,
1680 .label = "GPE1",
1681 },
1682 }, {
1683 .chip = {
1684 .base = S5PC100_GPF0(0),
1685 .ngpio = S5PC100_GPIO_F0_NR,
1686 .label = "GPF0",
1687 },
1688 }, {
1689 .chip = {
1690 .base = S5PC100_GPF1(0),
1691 .ngpio = S5PC100_GPIO_F1_NR,
1692 .label = "GPF1",
1693 },
1694 }, {
1695 .chip = {
1696 .base = S5PC100_GPF2(0),
1697 .ngpio = S5PC100_GPIO_F2_NR,
1698 .label = "GPF2",
1699 },
1700 }, {
1701 .chip = {
1702 .base = S5PC100_GPF3(0),
1703 .ngpio = S5PC100_GPIO_F3_NR,
1704 .label = "GPF3",
1705 },
1706 }, {
1707 .chip = {
1708 .base = S5PC100_GPG0(0),
1709 .ngpio = S5PC100_GPIO_G0_NR,
1710 .label = "GPG0",
1711 },
1712 }, {
1713 .chip = {
1714 .base = S5PC100_GPG1(0),
1715 .ngpio = S5PC100_GPIO_G1_NR,
1716 .label = "GPG1",
1717 },
1718 }, {
1719 .chip = {
1720 .base = S5PC100_GPG2(0),
1721 .ngpio = S5PC100_GPIO_G2_NR,
1722 .label = "GPG2",
1723 },
1724 }, {
1725 .chip = {
1726 .base = S5PC100_GPG3(0),
1727 .ngpio = S5PC100_GPIO_G3_NR,
1728 .label = "GPG3",
1729 },
1730 }, {
1731 .chip = {
1732 .base = S5PC100_GPI(0),
1733 .ngpio = S5PC100_GPIO_I_NR,
1734 .label = "GPI",
1735 },
1736 }, {
1737 .chip = {
1738 .base = S5PC100_GPJ0(0),
1739 .ngpio = S5PC100_GPIO_J0_NR,
1740 .label = "GPJ0",
1741 },
1742 }, {
1743 .chip = {
1744 .base = S5PC100_GPJ1(0),
1745 .ngpio = S5PC100_GPIO_J1_NR,
1746 .label = "GPJ1",
1747 },
1748 }, {
1749 .chip = {
1750 .base = S5PC100_GPJ2(0),
1751 .ngpio = S5PC100_GPIO_J2_NR,
1752 .label = "GPJ2",
1753 },
1754 }, {
1755 .chip = {
1756 .base = S5PC100_GPJ3(0),
1757 .ngpio = S5PC100_GPIO_J3_NR,
1758 .label = "GPJ3",
1759 },
1760 }, {
1761 .chip = {
1762 .base = S5PC100_GPJ4(0),
1763 .ngpio = S5PC100_GPIO_J4_NR,
1764 .label = "GPJ4",
1765 },
1766 }, {
1767 .chip = {
1768 .base = S5PC100_GPK0(0),
1769 .ngpio = S5PC100_GPIO_K0_NR,
1770 .label = "GPK0",
1771 },
1772 }, {
1773 .chip = {
1774 .base = S5PC100_GPK1(0),
1775 .ngpio = S5PC100_GPIO_K1_NR,
1776 .label = "GPK1",
1777 },
1778 }, {
1779 .chip = {
1780 .base = S5PC100_GPK2(0),
1781 .ngpio = S5PC100_GPIO_K2_NR,
1782 .label = "GPK2",
1783 },
1784 }, {
1785 .chip = {
1786 .base = S5PC100_GPK3(0),
1787 .ngpio = S5PC100_GPIO_K3_NR,
1788 .label = "GPK3",
1789 },
1790 }, {
1791 .chip = {
1792 .base = S5PC100_GPL0(0),
1793 .ngpio = S5PC100_GPIO_L0_NR,
1794 .label = "GPL0",
1795 },
1796 }, {
1797 .chip = {
1798 .base = S5PC100_GPL1(0),
1799 .ngpio = S5PC100_GPIO_L1_NR,
1800 .label = "GPL1",
1801 },
1802 }, {
1803 .chip = {
1804 .base = S5PC100_GPL2(0),
1805 .ngpio = S5PC100_GPIO_L2_NR,
1806 .label = "GPL2",
1807 },
1808 }, {
1809 .chip = {
1810 .base = S5PC100_GPL3(0),
1811 .ngpio = S5PC100_GPIO_L3_NR,
1812 .label = "GPL3",
1813 },
1814 }, {
1815 .chip = {
1816 .base = S5PC100_GPL4(0),
1817 .ngpio = S5PC100_GPIO_L4_NR,
1818 .label = "GPL4",
1819 },
1820 }, {
1821 .base = (S5P_VA_GPIO + 0xC00),
1822 .irq_base = IRQ_EINT(0),
1823 .chip = {
1824 .base = S5PC100_GPH0(0),
1825 .ngpio = S5PC100_GPIO_H0_NR,
1826 .label = "GPH0",
1827 .to_irq = samsung_gpiolib_to_irq,
1828 },
1829 }, {
1830 .base = (S5P_VA_GPIO + 0xC20),
1831 .irq_base = IRQ_EINT(8),
1832 .chip = {
1833 .base = S5PC100_GPH1(0),
1834 .ngpio = S5PC100_GPIO_H1_NR,
1835 .label = "GPH1",
1836 .to_irq = samsung_gpiolib_to_irq,
1837 },
1838 }, {
1839 .base = (S5P_VA_GPIO + 0xC40),
1840 .irq_base = IRQ_EINT(16),
1841 .chip = {
1842 .base = S5PC100_GPH2(0),
1843 .ngpio = S5PC100_GPIO_H2_NR,
1844 .label = "GPH2",
1845 .to_irq = samsung_gpiolib_to_irq,
1846 },
1847 }, {
1848 .base = (S5P_VA_GPIO + 0xC60),
1849 .irq_base = IRQ_EINT(24),
1850 .chip = {
1851 .base = S5PC100_GPH3(0),
1852 .ngpio = S5PC100_GPIO_H3_NR,
1853 .label = "GPH3",
1854 .to_irq = samsung_gpiolib_to_irq,
1855 },
1856 },
1857 #endif
1858 };
1859
1860 /*
1861 * Followings are the gpio banks in S5PV210/S5PC110
1862 *
1863 * The 'config' member when left to NULL, is initialized to the default
1864 * structure samsung_gpio_cfgs[3] in the init function below.
1865 *
1866 * The 'base' member is also initialized in the init function below.
1867 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1868 * uses the above macro and depends on the banks being listed in order here.
1869 */
1870
1871 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1872 #ifdef CONFIG_CPU_S5PV210
1873 {
1874 .chip = {
1875 .base = S5PV210_GPA0(0),
1876 .ngpio = S5PV210_GPIO_A0_NR,
1877 .label = "GPA0",
1878 },
1879 }, {
1880 .chip = {
1881 .base = S5PV210_GPA1(0),
1882 .ngpio = S5PV210_GPIO_A1_NR,
1883 .label = "GPA1",
1884 },
1885 }, {
1886 .chip = {
1887 .base = S5PV210_GPB(0),
1888 .ngpio = S5PV210_GPIO_B_NR,
1889 .label = "GPB",
1890 },
1891 }, {
1892 .chip = {
1893 .base = S5PV210_GPC0(0),
1894 .ngpio = S5PV210_GPIO_C0_NR,
1895 .label = "GPC0",
1896 },
1897 }, {
1898 .chip = {
1899 .base = S5PV210_GPC1(0),
1900 .ngpio = S5PV210_GPIO_C1_NR,
1901 .label = "GPC1",
1902 },
1903 }, {
1904 .chip = {
1905 .base = S5PV210_GPD0(0),
1906 .ngpio = S5PV210_GPIO_D0_NR,
1907 .label = "GPD0",
1908 },
1909 }, {
1910 .chip = {
1911 .base = S5PV210_GPD1(0),
1912 .ngpio = S5PV210_GPIO_D1_NR,
1913 .label = "GPD1",
1914 },
1915 }, {
1916 .chip = {
1917 .base = S5PV210_GPE0(0),
1918 .ngpio = S5PV210_GPIO_E0_NR,
1919 .label = "GPE0",
1920 },
1921 }, {
1922 .chip = {
1923 .base = S5PV210_GPE1(0),
1924 .ngpio = S5PV210_GPIO_E1_NR,
1925 .label = "GPE1",
1926 },
1927 }, {
1928 .chip = {
1929 .base = S5PV210_GPF0(0),
1930 .ngpio = S5PV210_GPIO_F0_NR,
1931 .label = "GPF0",
1932 },
1933 }, {
1934 .chip = {
1935 .base = S5PV210_GPF1(0),
1936 .ngpio = S5PV210_GPIO_F1_NR,
1937 .label = "GPF1",
1938 },
1939 }, {
1940 .chip = {
1941 .base = S5PV210_GPF2(0),
1942 .ngpio = S5PV210_GPIO_F2_NR,
1943 .label = "GPF2",
1944 },
1945 }, {
1946 .chip = {
1947 .base = S5PV210_GPF3(0),
1948 .ngpio = S5PV210_GPIO_F3_NR,
1949 .label = "GPF3",
1950 },
1951 }, {
1952 .chip = {
1953 .base = S5PV210_GPG0(0),
1954 .ngpio = S5PV210_GPIO_G0_NR,
1955 .label = "GPG0",
1956 },
1957 }, {
1958 .chip = {
1959 .base = S5PV210_GPG1(0),
1960 .ngpio = S5PV210_GPIO_G1_NR,
1961 .label = "GPG1",
1962 },
1963 }, {
1964 .chip = {
1965 .base = S5PV210_GPG2(0),
1966 .ngpio = S5PV210_GPIO_G2_NR,
1967 .label = "GPG2",
1968 },
1969 }, {
1970 .chip = {
1971 .base = S5PV210_GPG3(0),
1972 .ngpio = S5PV210_GPIO_G3_NR,
1973 .label = "GPG3",
1974 },
1975 }, {
1976 .chip = {
1977 .base = S5PV210_GPI(0),
1978 .ngpio = S5PV210_GPIO_I_NR,
1979 .label = "GPI",
1980 },
1981 }, {
1982 .chip = {
1983 .base = S5PV210_GPJ0(0),
1984 .ngpio = S5PV210_GPIO_J0_NR,
1985 .label = "GPJ0",
1986 },
1987 }, {
1988 .chip = {
1989 .base = S5PV210_GPJ1(0),
1990 .ngpio = S5PV210_GPIO_J1_NR,
1991 .label = "GPJ1",
1992 },
1993 }, {
1994 .chip = {
1995 .base = S5PV210_GPJ2(0),
1996 .ngpio = S5PV210_GPIO_J2_NR,
1997 .label = "GPJ2",
1998 },
1999 }, {
2000 .chip = {
2001 .base = S5PV210_GPJ3(0),
2002 .ngpio = S5PV210_GPIO_J3_NR,
2003 .label = "GPJ3",
2004 },
2005 }, {
2006 .chip = {
2007 .base = S5PV210_GPJ4(0),
2008 .ngpio = S5PV210_GPIO_J4_NR,
2009 .label = "GPJ4",
2010 },
2011 }, {
2012 .chip = {
2013 .base = S5PV210_MP01(0),
2014 .ngpio = S5PV210_GPIO_MP01_NR,
2015 .label = "MP01",
2016 },
2017 }, {
2018 .chip = {
2019 .base = S5PV210_MP02(0),
2020 .ngpio = S5PV210_GPIO_MP02_NR,
2021 .label = "MP02",
2022 },
2023 }, {
2024 .chip = {
2025 .base = S5PV210_MP03(0),
2026 .ngpio = S5PV210_GPIO_MP03_NR,
2027 .label = "MP03",
2028 },
2029 }, {
2030 .chip = {
2031 .base = S5PV210_MP04(0),
2032 .ngpio = S5PV210_GPIO_MP04_NR,
2033 .label = "MP04",
2034 },
2035 }, {
2036 .chip = {
2037 .base = S5PV210_MP05(0),
2038 .ngpio = S5PV210_GPIO_MP05_NR,
2039 .label = "MP05",
2040 },
2041 }, {
2042 .base = (S5P_VA_GPIO + 0xC00),
2043 .irq_base = IRQ_EINT(0),
2044 .chip = {
2045 .base = S5PV210_GPH0(0),
2046 .ngpio = S5PV210_GPIO_H0_NR,
2047 .label = "GPH0",
2048 .to_irq = samsung_gpiolib_to_irq,
2049 },
2050 }, {
2051 .base = (S5P_VA_GPIO + 0xC20),
2052 .irq_base = IRQ_EINT(8),
2053 .chip = {
2054 .base = S5PV210_GPH1(0),
2055 .ngpio = S5PV210_GPIO_H1_NR,
2056 .label = "GPH1",
2057 .to_irq = samsung_gpiolib_to_irq,
2058 },
2059 }, {
2060 .base = (S5P_VA_GPIO + 0xC40),
2061 .irq_base = IRQ_EINT(16),
2062 .chip = {
2063 .base = S5PV210_GPH2(0),
2064 .ngpio = S5PV210_GPIO_H2_NR,
2065 .label = "GPH2",
2066 .to_irq = samsung_gpiolib_to_irq,
2067 },
2068 }, {
2069 .base = (S5P_VA_GPIO + 0xC60),
2070 .irq_base = IRQ_EINT(24),
2071 .chip = {
2072 .base = S5PV210_GPH3(0),
2073 .ngpio = S5PV210_GPIO_H3_NR,
2074 .label = "GPH3",
2075 .to_irq = samsung_gpiolib_to_irq,
2076 },
2077 },
2078 #endif
2079 };
2080
2081 /* TODO: cleanup soc_is_* */
2082 static __init int samsung_gpiolib_init(void)
2083 {
2084 struct samsung_gpio_chip *chip;
2085 int i, nr_chips;
2086 int group = 0;
2087
2088 /*
2089 * Currently there are two drivers that can provide GPIO support for
2090 * Samsung SoCs. For device tree enabled platforms, the new
2091 * pinctrl-samsung driver is used, providing both GPIO and pin control
2092 * interfaces. For legacy (non-DT) platforms this driver is used.
2093 */
2094 if (of_have_populated_dt())
2095 return -ENODEV;
2096
2097 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2098
2099 if (soc_is_s3c24xx()) {
2100 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
2101 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
2102 } else if (soc_is_s3c64xx()) {
2103 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
2104 ARRAY_SIZE(s3c64xx_gpios_2bit),
2105 S3C64XX_VA_GPIO + 0xE0, 0x20);
2106 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
2107 ARRAY_SIZE(s3c64xx_gpios_4bit),
2108 S3C64XX_VA_GPIO);
2109 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2110 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2111 } else if (soc_is_s5p6440()) {
2112 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2113 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2114 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2115 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
2116 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
2117 ARRAY_SIZE(s5p6440_gpios_4bit2));
2118 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
2119 ARRAY_SIZE(s5p6440_gpios_rbank));
2120 } else if (soc_is_s5p6450()) {
2121 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
2122 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
2123 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
2124 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
2125 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
2126 ARRAY_SIZE(s5p6450_gpios_4bit2));
2127 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
2128 ARRAY_SIZE(s5p6450_gpios_rbank));
2129 } else if (soc_is_s5pc100()) {
2130 group = 0;
2131 chip = s5pc100_gpios_4bit;
2132 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
2133
2134 for (i = 0; i < nr_chips; i++, chip++) {
2135 if (!chip->config) {
2136 chip->config = &samsung_gpio_cfgs[3];
2137 chip->group = group++;
2138 }
2139 }
2140 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
2141 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2142 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2143 #endif
2144 } else if (soc_is_s5pv210()) {
2145 group = 0;
2146 chip = s5pv210_gpios_4bit;
2147 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
2148
2149 for (i = 0; i < nr_chips; i++, chip++) {
2150 if (!chip->config) {
2151 chip->config = &samsung_gpio_cfgs[3];
2152 chip->group = group++;
2153 }
2154 }
2155 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
2156 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
2157 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2158 #endif
2159 } else {
2160 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
2161 return -ENODEV;
2162 }
2163
2164 return 0;
2165 }
2166 core_initcall(samsung_gpiolib_init);
2167
2168 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
2169 {
2170 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2171 unsigned long flags;
2172 int offset;
2173 int ret;
2174
2175 if (!chip)
2176 return -EINVAL;
2177
2178 offset = pin - chip->chip.base;
2179
2180 samsung_gpio_lock(chip, flags);
2181 ret = samsung_gpio_do_setcfg(chip, offset, config);
2182 samsung_gpio_unlock(chip, flags);
2183
2184 return ret;
2185 }
2186 EXPORT_SYMBOL(s3c_gpio_cfgpin);
2187
2188 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
2189 unsigned int cfg)
2190 {
2191 int ret;
2192
2193 for (; nr > 0; nr--, start++) {
2194 ret = s3c_gpio_cfgpin(start, cfg);
2195 if (ret != 0)
2196 return ret;
2197 }
2198
2199 return 0;
2200 }
2201 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
2202
2203 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
2204 unsigned int cfg, samsung_gpio_pull_t pull)
2205 {
2206 int ret;
2207
2208 for (; nr > 0; nr--, start++) {
2209 s3c_gpio_setpull(start, pull);
2210 ret = s3c_gpio_cfgpin(start, cfg);
2211 if (ret != 0)
2212 return ret;
2213 }
2214
2215 return 0;
2216 }
2217 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
2218
2219 unsigned s3c_gpio_getcfg(unsigned int pin)
2220 {
2221 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2222 unsigned long flags;
2223 unsigned ret = 0;
2224 int offset;
2225
2226 if (chip) {
2227 offset = pin - chip->chip.base;
2228
2229 samsung_gpio_lock(chip, flags);
2230 ret = samsung_gpio_do_getcfg(chip, offset);
2231 samsung_gpio_unlock(chip, flags);
2232 }
2233
2234 return ret;
2235 }
2236 EXPORT_SYMBOL(s3c_gpio_getcfg);
2237
2238 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
2239 {
2240 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2241 unsigned long flags;
2242 int offset, ret;
2243
2244 if (!chip)
2245 return -EINVAL;
2246
2247 offset = pin - chip->chip.base;
2248
2249 samsung_gpio_lock(chip, flags);
2250 ret = samsung_gpio_do_setpull(chip, offset, pull);
2251 samsung_gpio_unlock(chip, flags);
2252
2253 return ret;
2254 }
2255 EXPORT_SYMBOL(s3c_gpio_setpull);
2256
2257 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
2258 {
2259 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2260 unsigned long flags;
2261 int offset;
2262 u32 pup = 0;
2263
2264 if (chip) {
2265 offset = pin - chip->chip.base;
2266
2267 samsung_gpio_lock(chip, flags);
2268 pup = samsung_gpio_do_getpull(chip, offset);
2269 samsung_gpio_unlock(chip, flags);
2270 }
2271
2272 return (__force samsung_gpio_pull_t)pup;
2273 }
2274 EXPORT_SYMBOL(s3c_gpio_getpull);
2275
2276 #ifdef CONFIG_S5P_GPIO_DRVSTR
2277 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
2278 {
2279 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2280 unsigned int off;
2281 void __iomem *reg;
2282 int shift;
2283 u32 drvstr;
2284
2285 if (!chip)
2286 return -EINVAL;
2287
2288 off = pin - chip->chip.base;
2289 shift = off * 2;
2290 reg = chip->base + 0x0C;
2291
2292 drvstr = __raw_readl(reg);
2293 drvstr = drvstr >> shift;
2294 drvstr &= 0x3;
2295
2296 return (__force s5p_gpio_drvstr_t)drvstr;
2297 }
2298 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
2299
2300 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
2301 {
2302 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2303 unsigned int off;
2304 void __iomem *reg;
2305 int shift;
2306 u32 tmp;
2307
2308 if (!chip)
2309 return -EINVAL;
2310
2311 off = pin - chip->chip.base;
2312 shift = off * 2;
2313 reg = chip->base + 0x0C;
2314
2315 tmp = __raw_readl(reg);
2316 tmp &= ~(0x3 << shift);
2317 tmp |= drvstr << shift;
2318
2319 __raw_writel(tmp, reg);
2320
2321 return 0;
2322 }
2323 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
2324 #endif /* CONFIG_S5P_GPIO_DRVSTR */
2325
2326 #ifdef CONFIG_PLAT_S3C24XX
2327 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
2328 {
2329 unsigned long flags;
2330 unsigned long misccr;
2331
2332 local_irq_save(flags);
2333 misccr = __raw_readl(S3C24XX_MISCCR);
2334 misccr &= ~clear;
2335 misccr ^= change;
2336 __raw_writel(misccr, S3C24XX_MISCCR);
2337 local_irq_restore(flags);
2338
2339 return misccr;
2340 }
2341 EXPORT_SYMBOL(s3c2410_modify_misccr);
2342 #endif
Linux with added FPC-III support