Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / drivers / gpio / gpio-tb10x.c
blob07bce97647a684901db5c8e10f7b5d96072909af
1 /* Abilis Systems MODULE DESCRIPTION
3 * Copyright (C) Abilis Systems 2013
5 * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
6 * Christian Ruppert <christian.ruppert@abilis.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/gpio.h>
26 #include <linux/slab.h>
27 #include <linux/irq.h>
28 #include <linux/irqdomain.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/of.h>
32 #include <linux/of_platform.h>
33 #include <linux/of_gpio.h>
34 #include <linux/spinlock.h>
35 #include <linux/bitops.h>
36 #include <linux/pinctrl/consumer.h>
38 #define TB10X_GPIO_DIR_IN (0x00000000)
39 #define TB10X_GPIO_DIR_OUT (0x00000001)
40 #define OFFSET_TO_REG_DDR (0x00)
41 #define OFFSET_TO_REG_DATA (0x04)
42 #define OFFSET_TO_REG_INT_EN (0x08)
43 #define OFFSET_TO_REG_CHANGE (0x0C)
44 #define OFFSET_TO_REG_WRMASK (0x10)
45 #define OFFSET_TO_REG_INT_TYPE (0x14)
48 /**
49 * @spinlock: used for atomic read/modify/write of registers
50 * @base: register base address
51 * @domain: IRQ domain of GPIO generated interrupts managed by this controller
52 * @irq: Interrupt line of parent interrupt controller
53 * @gc: gpio_chip structure associated to this GPIO controller
55 struct tb10x_gpio {
56 spinlock_t spinlock;
57 void __iomem *base;
58 struct irq_domain *domain;
59 int irq;
60 struct gpio_chip gc;
63 static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
65 return ioread32(gpio->base + offs);
68 static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
69 u32 val)
71 iowrite32(val, gpio->base + offs);
74 static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
75 u32 mask, u32 val)
77 u32 r;
78 unsigned long flags;
80 spin_lock_irqsave(&gpio->spinlock, flags);
82 r = tb10x_reg_read(gpio, offs);
83 r = (r & ~mask) | (val & mask);
85 tb10x_reg_write(gpio, offs, r);
87 spin_unlock_irqrestore(&gpio->spinlock, flags);
90 static inline struct tb10x_gpio *to_tb10x_gpio(struct gpio_chip *chip)
92 return container_of(chip, struct tb10x_gpio, gc);
95 static int tb10x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
97 struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
98 int mask = BIT(offset);
99 int val = TB10X_GPIO_DIR_IN << offset;
101 tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
103 return 0;
106 static int tb10x_gpio_get(struct gpio_chip *chip, unsigned offset)
108 struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
109 int val;
111 val = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_DATA);
113 if (val & BIT(offset))
114 return 1;
115 else
116 return 0;
119 static void tb10x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
121 struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
122 int mask = BIT(offset);
123 int val = value << offset;
125 tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DATA, mask, val);
128 static int tb10x_gpio_direction_out(struct gpio_chip *chip,
129 unsigned offset, int value)
131 struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
132 int mask = BIT(offset);
133 int val = TB10X_GPIO_DIR_OUT << offset;
135 tb10x_gpio_set(chip, offset, value);
136 tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
138 return 0;
141 static int tb10x_gpio_request(struct gpio_chip *chip, unsigned offset)
143 return pinctrl_request_gpio(chip->base + offset);
146 static void tb10x_gpio_free(struct gpio_chip *chip, unsigned offset)
148 pinctrl_free_gpio(chip->base + offset);
151 static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
153 struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
155 return irq_create_mapping(tb10x_gpio->domain, offset);
158 static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
160 if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
161 pr_err("Only (both) edge triggered interrupts supported.\n");
162 return -EINVAL;
165 irqd_set_trigger_type(data, type);
167 return IRQ_SET_MASK_OK;
170 static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
172 struct tb10x_gpio *tb10x_gpio = data;
173 u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
174 u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
175 const unsigned long bits = r & m;
176 int i;
178 for_each_set_bit(i, &bits, 32)
179 generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
181 return IRQ_HANDLED;
184 static int tb10x_gpio_probe(struct platform_device *pdev)
186 struct tb10x_gpio *tb10x_gpio;
187 struct resource *mem;
188 struct device_node *dn = pdev->dev.of_node;
189 int ret = -EBUSY;
190 u32 ngpio;
192 if (!dn)
193 return -EINVAL;
195 if (of_property_read_u32(dn, "abilis,ngpio", &ngpio))
196 return -EINVAL;
198 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
199 if (!mem) {
200 dev_err(&pdev->dev, "No memory resource defined.\n");
201 return -EINVAL;
204 tb10x_gpio = devm_kzalloc(&pdev->dev, sizeof(*tb10x_gpio), GFP_KERNEL);
205 if (tb10x_gpio == NULL)
206 return -ENOMEM;
208 spin_lock_init(&tb10x_gpio->spinlock);
210 tb10x_gpio->base = devm_ioremap_resource(&pdev->dev, mem);
211 if (IS_ERR(tb10x_gpio->base))
212 return PTR_ERR(tb10x_gpio->base);
214 tb10x_gpio->gc.label = of_node_full_name(dn);
215 tb10x_gpio->gc.dev = &pdev->dev;
216 tb10x_gpio->gc.owner = THIS_MODULE;
217 tb10x_gpio->gc.direction_input = tb10x_gpio_direction_in;
218 tb10x_gpio->gc.get = tb10x_gpio_get;
219 tb10x_gpio->gc.direction_output = tb10x_gpio_direction_out;
220 tb10x_gpio->gc.set = tb10x_gpio_set;
221 tb10x_gpio->gc.request = tb10x_gpio_request;
222 tb10x_gpio->gc.free = tb10x_gpio_free;
223 tb10x_gpio->gc.base = -1;
224 tb10x_gpio->gc.ngpio = ngpio;
225 tb10x_gpio->gc.can_sleep = false;
228 ret = gpiochip_add(&tb10x_gpio->gc);
229 if (ret < 0) {
230 dev_err(&pdev->dev, "Could not add gpiochip.\n");
231 goto fail_gpiochip_registration;
234 platform_set_drvdata(pdev, tb10x_gpio);
236 if (of_find_property(dn, "interrupt-controller", NULL)) {
237 struct irq_chip_generic *gc;
239 ret = platform_get_irq(pdev, 0);
240 if (ret < 0) {
241 dev_err(&pdev->dev, "No interrupt specified.\n");
242 goto fail_get_irq;
245 tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
246 tb10x_gpio->irq = ret;
248 ret = devm_request_irq(&pdev->dev, ret, tb10x_gpio_irq_cascade,
249 IRQF_TRIGGER_NONE | IRQF_SHARED,
250 dev_name(&pdev->dev), tb10x_gpio);
251 if (ret != 0)
252 goto fail_request_irq;
254 tb10x_gpio->domain = irq_domain_add_linear(dn,
255 tb10x_gpio->gc.ngpio,
256 &irq_generic_chip_ops, NULL);
257 if (!tb10x_gpio->domain) {
258 ret = -ENOMEM;
259 goto fail_irq_domain;
262 ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
263 tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
264 handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
265 IRQ_GC_INIT_MASK_CACHE);
266 if (ret)
267 goto fail_irq_domain;
269 gc = tb10x_gpio->domain->gc->gc[0];
270 gc->reg_base = tb10x_gpio->base;
271 gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
272 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
273 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
274 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
275 gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type;
276 gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE;
277 gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN;
280 return 0;
282 fail_irq_domain:
283 fail_request_irq:
284 fail_get_irq:
285 gpiochip_remove(&tb10x_gpio->gc);
286 fail_gpiochip_registration:
287 fail_ioremap:
288 return ret;
291 static int __exit tb10x_gpio_remove(struct platform_device *pdev)
293 struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
294 int ret;
296 if (tb10x_gpio->gc.to_irq) {
297 irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
298 BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
299 kfree(tb10x_gpio->domain->gc);
300 irq_domain_remove(tb10x_gpio->domain);
301 free_irq(tb10x_gpio->irq, tb10x_gpio);
303 ret = gpiochip_remove(&tb10x_gpio->gc);
304 if (ret)
305 return ret;
307 return 0;
310 static const struct of_device_id tb10x_gpio_dt_ids[] = {
311 { .compatible = "abilis,tb10x-gpio" },
314 MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
316 static struct platform_driver tb10x_gpio_driver = {
317 .probe = tb10x_gpio_probe,
318 .remove = tb10x_gpio_remove,
319 .driver = {
320 .name = "tb10x-gpio",
321 .of_match_table = tb10x_gpio_dt_ids,
322 .owner = THIS_MODULE,
326 module_platform_driver(tb10x_gpio_driver);
327 MODULE_LICENSE("GPL");
328 MODULE_DESCRIPTION("tb10x gpio.");
329 MODULE_VERSION("0.0.1");