2 * Toumaz Xenif TZ1090 PDC GPIO handling.
4 * Copyright (C) 2012-2013 Imagination Technologies Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/bitops.h>
12 #include <linux/gpio.h>
14 #include <linux/module.h>
15 #include <linux/of_irq.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/syscore_ops.h>
20 #include <asm/global_lock.h>
22 /* Register offsets from SOC_GPIO_CONTROL0 */
23 #define REG_SOC_GPIO_CONTROL0 0x00
24 #define REG_SOC_GPIO_CONTROL1 0x04
25 #define REG_SOC_GPIO_CONTROL2 0x08
26 #define REG_SOC_GPIO_CONTROL3 0x0c
27 #define REG_SOC_GPIO_STATUS 0x80
29 /* PDC GPIOs go after normal GPIOs */
30 #define GPIO_PDC_BASE 90
31 #define GPIO_PDC_NGPIO 7
33 /* Out of PDC gpios, only syswakes have irqs */
34 #define GPIO_PDC_IRQ_FIRST 2
35 #define GPIO_PDC_NIRQ 3
38 * struct tz1090_pdc_gpio - GPIO bank private data
39 * @chip: Generic GPIO chip for GPIO bank
40 * @reg: Base of registers, offset for this GPIO bank
41 * @irq: IRQ numbers for Syswake GPIOs
43 * This is the main private data for the PDC GPIO driver. It encapsulates a
44 * gpio_chip, and the callbacks for the gpio_chip can access the private data
45 * with the to_pdc() macro below.
47 struct tz1090_pdc_gpio
{
48 struct gpio_chip chip
;
50 int irq
[GPIO_PDC_NIRQ
];
52 #define to_pdc(c) container_of(c, struct tz1090_pdc_gpio, chip)
54 /* Register accesses into the PDC MMIO area */
56 static inline void pdc_write(struct tz1090_pdc_gpio
*priv
, unsigned int reg_offs
,
59 writel(data
, priv
->reg
+ reg_offs
);
62 static inline unsigned int pdc_read(struct tz1090_pdc_gpio
*priv
,
63 unsigned int reg_offs
)
65 return readl(priv
->reg
+ reg_offs
);
68 /* Generic GPIO interface */
70 static int tz1090_pdc_gpio_direction_input(struct gpio_chip
*chip
,
73 struct tz1090_pdc_gpio
*priv
= to_pdc(chip
);
77 __global_lock2(lstat
);
78 value
= pdc_read(priv
, REG_SOC_GPIO_CONTROL1
);
80 pdc_write(priv
, REG_SOC_GPIO_CONTROL1
, value
);
81 __global_unlock2(lstat
);
86 static int tz1090_pdc_gpio_direction_output(struct gpio_chip
*chip
,
90 struct tz1090_pdc_gpio
*priv
= to_pdc(chip
);
94 __global_lock2(lstat
);
95 /* EXT_POWER doesn't seem to have an output value bit */
97 value
= pdc_read(priv
, REG_SOC_GPIO_CONTROL0
);
101 value
&= ~BIT(offset
);
102 pdc_write(priv
, REG_SOC_GPIO_CONTROL0
, value
);
105 value
= pdc_read(priv
, REG_SOC_GPIO_CONTROL1
);
106 value
&= ~BIT(offset
);
107 pdc_write(priv
, REG_SOC_GPIO_CONTROL1
, value
);
108 __global_unlock2(lstat
);
113 static int tz1090_pdc_gpio_get(struct gpio_chip
*chip
, unsigned int offset
)
115 struct tz1090_pdc_gpio
*priv
= to_pdc(chip
);
116 return pdc_read(priv
, REG_SOC_GPIO_STATUS
) & BIT(offset
);
119 static void tz1090_pdc_gpio_set(struct gpio_chip
*chip
, unsigned int offset
,
122 struct tz1090_pdc_gpio
*priv
= to_pdc(chip
);
126 /* EXT_POWER doesn't seem to have an output value bit */
130 __global_lock2(lstat
);
131 value
= pdc_read(priv
, REG_SOC_GPIO_CONTROL0
);
133 value
|= BIT(offset
);
135 value
&= ~BIT(offset
);
136 pdc_write(priv
, REG_SOC_GPIO_CONTROL0
, value
);
137 __global_unlock2(lstat
);
140 static int tz1090_pdc_gpio_request(struct gpio_chip
*chip
, unsigned int offset
)
142 return pinctrl_request_gpio(chip
->base
+ offset
);
145 static void tz1090_pdc_gpio_free(struct gpio_chip
*chip
, unsigned int offset
)
147 pinctrl_free_gpio(chip
->base
+ offset
);
150 static int tz1090_pdc_gpio_to_irq(struct gpio_chip
*chip
, unsigned int offset
)
152 struct tz1090_pdc_gpio
*priv
= to_pdc(chip
);
153 unsigned int syswake
= offset
- GPIO_PDC_IRQ_FIRST
;
156 /* only syswakes have irqs */
157 if (syswake
>= GPIO_PDC_NIRQ
)
160 irq
= priv
->irq
[syswake
];
167 static int tz1090_pdc_gpio_probe(struct platform_device
*pdev
)
169 struct device_node
*np
= pdev
->dev
.of_node
;
170 struct resource
*res_regs
;
171 struct tz1090_pdc_gpio
*priv
;
175 dev_err(&pdev
->dev
, "must be instantiated via devicetree\n");
179 res_regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
181 dev_err(&pdev
->dev
, "cannot find registers resource\n");
185 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
187 dev_err(&pdev
->dev
, "unable to allocate driver data\n");
191 /* Ioremap the registers */
192 priv
->reg
= devm_ioremap(&pdev
->dev
, res_regs
->start
,
193 res_regs
->end
- res_regs
->start
);
195 dev_err(&pdev
->dev
, "unable to ioremap registers\n");
199 /* Set up GPIO chip */
200 priv
->chip
.label
= "tz1090-pdc-gpio";
201 priv
->chip
.dev
= &pdev
->dev
;
202 priv
->chip
.direction_input
= tz1090_pdc_gpio_direction_input
;
203 priv
->chip
.direction_output
= tz1090_pdc_gpio_direction_output
;
204 priv
->chip
.get
= tz1090_pdc_gpio_get
;
205 priv
->chip
.set
= tz1090_pdc_gpio_set
;
206 priv
->chip
.free
= tz1090_pdc_gpio_free
;
207 priv
->chip
.request
= tz1090_pdc_gpio_request
;
208 priv
->chip
.to_irq
= tz1090_pdc_gpio_to_irq
;
209 priv
->chip
.of_node
= np
;
212 priv
->chip
.base
= GPIO_PDC_BASE
;
213 priv
->chip
.ngpio
= GPIO_PDC_NGPIO
;
215 /* Map the syswake irqs */
216 for (i
= 0; i
< GPIO_PDC_NIRQ
; ++i
)
217 priv
->irq
[i
] = irq_of_parse_and_map(np
, i
);
219 /* Add the GPIO bank */
220 gpiochip_add(&priv
->chip
);
225 static struct of_device_id tz1090_pdc_gpio_of_match
[] = {
226 { .compatible
= "img,tz1090-pdc-gpio" },
230 static struct platform_driver tz1090_pdc_gpio_driver
= {
232 .name
= "tz1090-pdc-gpio",
233 .owner
= THIS_MODULE
,
234 .of_match_table
= tz1090_pdc_gpio_of_match
,
236 .probe
= tz1090_pdc_gpio_probe
,
239 static int __init
tz1090_pdc_gpio_init(void)
241 return platform_driver_register(&tz1090_pdc_gpio_driver
);
243 subsys_initcall(tz1090_pdc_gpio_init
);