drivers/misc/mei/hw-me.c

   1 /*
   2  *
   3  * Intel Management Engine Interface (Intel MEI) Linux driver
   4  * Copyright (c) 2003-2012, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16
  17 #include <linux/pci.h>
  18
  19 #include <linux/kthread.h>
  20 #include <linux/interrupt.h>
  21
  22 #include "mei_dev.h"
  23 #include "hw-me.h"
  24
  25 #include "hbm.h"
  26
  27
  28 /**
  29  * mei_me_reg_read - Reads 32bit data from the mei device
  30  *
  31  * @dev: the device structure
  32  * @offset: offset from which to read the data
  33  *
  34  * returns register value (u32)
  35  */
  36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
  37                                unsigned long offset)
  38 {
  39         return ioread32(hw->mem_addr + offset);
  40 }
  41
  42
  43 /**
  44  * mei_me_reg_write - Writes 32bit data to the mei device
  45  *
  46  * @dev: the device structure
  47  * @offset: offset from which to write the data
  48  * @value: register value to write (u32)
  49  */
  50 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
  51                                  unsigned long offset, u32 value)
  52 {
  53         iowrite32(value, hw->mem_addr + offset);
  54 }
  55
  56 /**
  57  * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
  58  *  read window register
  59  *
  60  * @dev: the device structure
  61  *
  62  * returns ME_CB_RW register value (u32)
  63  */
  64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
  65 {
  66         return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
  67 }
  68 /**
  69  * mei_me_mecsr_read - Reads 32bit data from the ME CSR
  70  *
  71  * @dev: the device structure
  72  *
  73  * returns ME_CSR_HA register value (u32)
  74  */
  75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
  76 {
  77         return mei_me_reg_read(hw, ME_CSR_HA);
  78 }
  79
  80 /**
  81  * mei_hcsr_read - Reads 32bit data from the host CSR
  82  *
  83  * @dev: the device structure
  84  *
  85  * returns H_CSR register value (u32)
  86  */
  87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
  88 {
  89         return mei_me_reg_read(hw, H_CSR);
  90 }
  91
  92 /**
  93  * mei_hcsr_set - writes H_CSR register to the mei device,
  94  * and ignores the H_IS bit for it is write-one-to-zero.
  95  *
  96  * @dev: the device structure
  97  */
  98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
  99 {
 100         hcsr &= ~H_IS;
 101         mei_me_reg_write(hw, H_CSR, hcsr);
 102 }
 103
 104
 105 /**
 106  * mei_me_hw_config - configure hw dependent settings
 107  *
 108  * @dev: mei device
 109  */
 110 static void mei_me_hw_config(struct mei_device *dev)
 111 {
 112         u32 hcsr = mei_hcsr_read(to_me_hw(dev));
 113         /* Doesn't change in runtime */
 114         dev->hbuf_depth = (hcsr & H_CBD) >> 24;
 115 }
 116 /**
 117  * mei_clear_interrupts - clear and stop interrupts
 118  *
 119  * @dev: the device structure
 120  */
 121 static void mei_me_intr_clear(struct mei_device *dev)
 122 {
 123         struct mei_me_hw *hw = to_me_hw(dev);
 124         u32 hcsr = mei_hcsr_read(hw);
 125         if ((hcsr & H_IS) == H_IS)
 126                 mei_me_reg_write(hw, H_CSR, hcsr);
 127 }
 128 /**
 129  * mei_me_intr_enable - enables mei device interrupts
 130  *
 131  * @dev: the device structure
 132  */
 133 static void mei_me_intr_enable(struct mei_device *dev)
 134 {
 135         struct mei_me_hw *hw = to_me_hw(dev);
 136         u32 hcsr = mei_hcsr_read(hw);
 137         hcsr |= H_IE;
 138         mei_hcsr_set(hw, hcsr);
 139 }
 140
 141 /**
 142  * mei_disable_interrupts - disables mei device interrupts
 143  *
 144  * @dev: the device structure
 145  */
 146 static void mei_me_intr_disable(struct mei_device *dev)
 147 {
 148         struct mei_me_hw *hw = to_me_hw(dev);
 149         u32 hcsr = mei_hcsr_read(hw);
 150         hcsr  &= ~H_IE;
 151         mei_hcsr_set(hw, hcsr);
 152 }
 153
 154 /**
 155  * mei_me_hw_reset_release - release device from the reset
 156  *
 157  * @dev: the device structure
 158  */
 159 static void mei_me_hw_reset_release(struct mei_device *dev)
 160 {
 161         struct mei_me_hw *hw = to_me_hw(dev);
 162         u32 hcsr = mei_hcsr_read(hw);
 163
 164         hcsr |= H_IG;
 165         hcsr &= ~H_RST;
 166         mei_hcsr_set(hw, hcsr);
 167 }
 168 /**
 169  * mei_me_hw_reset - resets fw via mei csr register.
 170  *
 171  * @dev: the device structure
 172  * @intr_enable: if interrupt should be enabled after reset.
 173  */
 174 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
 175 {
 176         struct mei_me_hw *hw = to_me_hw(dev);
 177         u32 hcsr = mei_hcsr_read(hw);
 178
 179         hcsr |= H_RST | H_IG | H_IS;
 180
 181         if (intr_enable)
 182                 hcsr |= H_IE;
 183         else
 184                 hcsr &= ~H_IE;
 185
 186         mei_me_reg_write(hw, H_CSR, hcsr);
 187
 188         if (intr_enable == false)
 189                 mei_me_hw_reset_release(dev);
 190
 191         return 0;
 192 }
 193
 194 /**
 195  * mei_me_host_set_ready - enable device
 196  *
 197  * @dev - mei device
 198  * returns bool
 199  */
 200
 201 static void mei_me_host_set_ready(struct mei_device *dev)
 202 {
 203         struct mei_me_hw *hw = to_me_hw(dev);
 204         hw->host_hw_state |= H_IE | H_IG | H_RDY;
 205         mei_hcsr_set(hw, hw->host_hw_state);
 206 }
 207 /**
 208  * mei_me_host_is_ready - check whether the host has turned ready
 209  *
 210  * @dev - mei device
 211  * returns bool
 212  */
 213 static bool mei_me_host_is_ready(struct mei_device *dev)
 214 {
 215         struct mei_me_hw *hw = to_me_hw(dev);
 216         hw->host_hw_state = mei_hcsr_read(hw);
 217         return (hw->host_hw_state & H_RDY) == H_RDY;
 218 }
 219
 220 /**
 221  * mei_me_hw_is_ready - check whether the me(hw) has turned ready
 222  *
 223  * @dev - mei device
 224  * returns bool
 225  */
 226 static bool mei_me_hw_is_ready(struct mei_device *dev)
 227 {
 228         struct mei_me_hw *hw = to_me_hw(dev);
 229         hw->me_hw_state = mei_me_mecsr_read(hw);
 230         return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
 231 }
 232
 233 static int mei_me_hw_ready_wait(struct mei_device *dev)
 234 {
 235         int err;
 236         if (mei_me_hw_is_ready(dev))
 237                 return 0;
 238
 239         dev->recvd_hw_ready = false;
 240         mutex_unlock(&dev->device_lock);
 241         err = wait_event_interruptible_timeout(dev->wait_hw_ready,
 242                         dev->recvd_hw_ready,
 243                         mei_secs_to_jiffies(MEI_INTEROP_TIMEOUT));
 244         mutex_lock(&dev->device_lock);
 245         if (!err && !dev->recvd_hw_ready) {
 246                 if (!err)
 247                         err = -ETIMEDOUT;
 248                 dev_err(&dev->pdev->dev,
 249                         "wait hw ready failed. status = %d\n", err);
 250                 return err;
 251         }
 252
 253         dev->recvd_hw_ready = false;
 254         return 0;
 255 }
 256
 257 static int mei_me_hw_start(struct mei_device *dev)
 258 {
 259         int ret = mei_me_hw_ready_wait(dev);
 260         if (ret)
 261                 return ret;
 262         dev_dbg(&dev->pdev->dev, "hw is ready\n");
 263
 264         mei_me_host_set_ready(dev);
 265         return ret;
 266 }
 267
 268
 269 /**
 270  * mei_hbuf_filled_slots - gets number of device filled buffer slots
 271  *
 272  * @dev: the device structure
 273  *
 274  * returns number of filled slots
 275  */
 276 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
 277 {
 278         struct mei_me_hw *hw = to_me_hw(dev);
 279         char read_ptr, write_ptr;
 280
 281         hw->host_hw_state = mei_hcsr_read(hw);
 282
 283         read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
 284         write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
 285
 286         return (unsigned char) (write_ptr - read_ptr);
 287 }
 288
 289 /**
 290  * mei_me_hbuf_is_empty - checks if host buffer is empty.
 291  *
 292  * @dev: the device structure
 293  *
 294  * returns true if empty, false - otherwise.
 295  */
 296 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
 297 {
 298         return mei_hbuf_filled_slots(dev) == 0;
 299 }
 300
 301 /**
 302  * mei_me_hbuf_empty_slots - counts write empty slots.
 303  *
 304  * @dev: the device structure
 305  *
 306  * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise empty slots count
 307  */
 308 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
 309 {
 310         unsigned char filled_slots, empty_slots;
 311
 312         filled_slots = mei_hbuf_filled_slots(dev);
 313         empty_slots = dev->hbuf_depth - filled_slots;
 314
 315         /* check for overflow */
 316         if (filled_slots > dev->hbuf_depth)
 317                 return -EOVERFLOW;
 318
 319         return empty_slots;
 320 }
 321
 322 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
 323 {
 324         return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
 325 }
 326
 327
 328 /**
 329  * mei_write_message - writes a message to mei device.
 330  *
 331  * @dev: the device structure
 332  * @header: mei HECI header of message
 333  * @buf: message payload will be written
 334  *
 335  * This function returns -EIO if write has failed
 336  */
 337 static int mei_me_write_message(struct mei_device *dev,
 338                         struct mei_msg_hdr *header,
 339                         unsigned char *buf)
 340 {
 341         struct mei_me_hw *hw = to_me_hw(dev);
 342         unsigned long rem;
 343         unsigned long length = header->length;
 344         u32 *reg_buf = (u32 *)buf;
 345         u32 hcsr;
 346         u32 dw_cnt;
 347         int i;
 348         int empty_slots;
 349
 350         dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
 351
 352         empty_slots = mei_hbuf_empty_slots(dev);
 353         dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
 354
 355         dw_cnt = mei_data2slots(length);
 356         if (empty_slots < 0 || dw_cnt > empty_slots)
 357                 return -EIO;
 358
 359         mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
 360
 361         for (i = 0; i < length / 4; i++)
 362                 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
 363
 364         rem = length & 0x3;
 365         if (rem > 0) {
 366                 u32 reg = 0;
 367                 memcpy(&reg, &buf[length - rem], rem);
 368                 mei_me_reg_write(hw, H_CB_WW, reg);
 369         }
 370
 371         hcsr = mei_hcsr_read(hw) | H_IG;
 372         mei_hcsr_set(hw, hcsr);
 373         if (!mei_me_hw_is_ready(dev))
 374                 return -EIO;
 375
 376         return 0;
 377 }
 378
 379 /**
 380  * mei_me_count_full_read_slots - counts read full slots.
 381  *
 382  * @dev: the device structure
 383  *
 384  * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise filled slots count
 385  */
 386 static int mei_me_count_full_read_slots(struct mei_device *dev)
 387 {
 388         struct mei_me_hw *hw = to_me_hw(dev);
 389         char read_ptr, write_ptr;
 390         unsigned char buffer_depth, filled_slots;
 391
 392         hw->me_hw_state = mei_me_mecsr_read(hw);
 393         buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
 394         read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
 395         write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
 396         filled_slots = (unsigned char) (write_ptr - read_ptr);
 397
 398         /* check for overflow */
 399         if (filled_slots > buffer_depth)
 400                 return -EOVERFLOW;
 401
 402         dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
 403         return (int)filled_slots;
 404 }
 405
 406 /**
 407  * mei_me_read_slots - reads a message from mei device.
 408  *
 409  * @dev: the device structure
 410  * @buffer: message buffer will be written
 411  * @buffer_length: message size will be read
 412  */
 413 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
 414                     unsigned long buffer_length)
 415 {
 416         struct mei_me_hw *hw = to_me_hw(dev);
 417         u32 *reg_buf = (u32 *)buffer;
 418         u32 hcsr;
 419
 420         for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
 421                 *reg_buf++ = mei_me_mecbrw_read(dev);
 422
 423         if (buffer_length > 0) {
 424                 u32 reg = mei_me_mecbrw_read(dev);
 425                 memcpy(reg_buf, &reg, buffer_length);
 426         }
 427
 428         hcsr = mei_hcsr_read(hw) | H_IG;
 429         mei_hcsr_set(hw, hcsr);
 430         return 0;
 431 }
 432
 433 /**
 434  * mei_me_irq_quick_handler - The ISR of the MEI device
 435  *
 436  * @irq: The irq number
 437  * @dev_id: pointer to the device structure
 438  *
 439  * returns irqreturn_t
 440  */
 441
 442 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
 443 {
 444         struct mei_device *dev = (struct mei_device *) dev_id;
 445         struct mei_me_hw *hw = to_me_hw(dev);
 446         u32 csr_reg = mei_hcsr_read(hw);
 447
 448         if ((csr_reg & H_IS) != H_IS)
 449                 return IRQ_NONE;
 450
 451         /* clear H_IS bit in H_CSR */
 452         mei_me_reg_write(hw, H_CSR, csr_reg);
 453
 454         return IRQ_WAKE_THREAD;
 455 }
 456
 457 /**
 458  * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
 459  * processing.
 460  *
 461  * @irq: The irq number
 462  * @dev_id: pointer to the device structure
 463  *
 464  * returns irqreturn_t
 465  *
 466  */
 467 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
 468 {
 469         struct mei_device *dev = (struct mei_device *) dev_id;
 470         struct mei_cl_cb complete_list;
 471         s32 slots;
 472         int rets = 0;
 473
 474         dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
 475         /* initialize our complete list */
 476         mutex_lock(&dev->device_lock);
 477         mei_io_list_init(&complete_list);
 478
 479         /* Ack the interrupt here
 480          * In case of MSI we don't go through the quick handler */
 481         if (pci_dev_msi_enabled(dev->pdev))
 482                 mei_clear_interrupts(dev);
 483
 484         /* check if ME wants a reset */
 485         if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
 486                 dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n");
 487                 schedule_work(&dev->reset_work);
 488                 goto end;
 489         }
 490
 491         /*  check if we need to start the dev */
 492         if (!mei_host_is_ready(dev)) {
 493                 if (mei_hw_is_ready(dev)) {
 494                         dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
 495
 496                         dev->recvd_hw_ready = true;
 497                         wake_up_interruptible(&dev->wait_hw_ready);
 498                 } else {
 499
 500                         dev_dbg(&dev->pdev->dev, "Reset Completed.\n");
 501                         mei_me_hw_reset_release(dev);
 502                 }
 503                 goto end;
 504         }
 505         /* check slots available for reading */
 506         slots = mei_count_full_read_slots(dev);
 507         while (slots > 0) {
 508                 /* we have urgent data to send so break the read */
 509                 if (dev->wr_ext_msg.hdr.length)
 510                         break;
 511                 dev_dbg(&dev->pdev->dev, "slots to read = %08x\n", slots);
 512                 rets = mei_irq_read_handler(dev, &complete_list, &slots);
 513                 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
 514                         schedule_work(&dev->reset_work);
 515                         goto end;
 516                 }
 517         }
 518
 519         rets = mei_irq_write_handler(dev, &complete_list);
 520
 521         dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
 522
 523         mei_irq_compl_handler(dev, &complete_list);
 524
 525 end:
 526         dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets);
 527         mutex_unlock(&dev->device_lock);
 528         return IRQ_HANDLED;
 529 }
 530 static const struct mei_hw_ops mei_me_hw_ops = {
 531
 532         .host_is_ready = mei_me_host_is_ready,
 533
 534         .hw_is_ready = mei_me_hw_is_ready,
 535         .hw_reset = mei_me_hw_reset,
 536         .hw_config = mei_me_hw_config,
 537         .hw_start = mei_me_hw_start,
 538
 539         .intr_clear = mei_me_intr_clear,
 540         .intr_enable = mei_me_intr_enable,
 541         .intr_disable = mei_me_intr_disable,
 542
 543         .hbuf_free_slots = mei_me_hbuf_empty_slots,
 544         .hbuf_is_ready = mei_me_hbuf_is_empty,
 545         .hbuf_max_len = mei_me_hbuf_max_len,
 546
 547         .write = mei_me_write_message,
 548
 549         .rdbuf_full_slots = mei_me_count_full_read_slots,
 550         .read_hdr = mei_me_mecbrw_read,
 551         .read = mei_me_read_slots
 552 };
 553
 554 /**
 555  * mei_me_dev_init - allocates and initializes the mei device structure
 556  *
 557  * @pdev: The pci device structure
 558  *
 559  * returns The mei_device_device pointer on success, NULL on failure.
 560  */
 561 struct mei_device *mei_me_dev_init(struct pci_dev *pdev)
 562 {
 563         struct mei_device *dev;
 564
 565         dev = kzalloc(sizeof(struct mei_device) +
 566                          sizeof(struct mei_me_hw), GFP_KERNEL);
 567         if (!dev)
 568                 return NULL;
 569
 570         mei_device_init(dev);
 571
 572         dev->ops = &mei_me_hw_ops;
 573
 574         dev->pdev = pdev;
 575         return dev;
 576 }
 577