drivers/pinctrl/pinctrl-baytrail.c

   1 /*
   2  * Pinctrl GPIO driver for Intel Baytrail
   3  * Copyright (c) 2012-2013, Intel Corporation.
   4  *
   5  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/init.h>
  25 #include <linux/types.h>
  26 #include <linux/bitops.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/irq.h>
  29 #include <linux/gpio.h>
  30 #include <linux/irqdomain.h>
  31 #include <linux/acpi.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/seq_file.h>
  34 #include <linux/io.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/pinctrl/pinctrl.h>
  37
  38 /* memory mapped register offsets */
  39 #define BYT_CONF0_REG           0x000
  40 #define BYT_CONF1_REG           0x004
  41 #define BYT_VAL_REG             0x008
  42 #define BYT_DFT_REG             0x00c
  43 #define BYT_INT_STAT_REG        0x800
  44
  45 /* BYT_CONF0_REG register bits */
  46 #define BYT_TRIG_NEG            BIT(26)
  47 #define BYT_TRIG_POS            BIT(25)
  48 #define BYT_TRIG_LVL            BIT(24)
  49 #define BYT_PIN_MUX             0x07
  50
  51 /* BYT_VAL_REG register bits */
  52 #define BYT_INPUT_EN            BIT(2)  /* 0: input enabled (active low)*/
  53 #define BYT_OUTPUT_EN           BIT(1)  /* 0: output enabled (active low)*/
  54 #define BYT_LEVEL               BIT(0)
  55
  56 #define BYT_DIR_MASK            (BIT(1) | BIT(2))
  57 #define BYT_TRIG_MASK           (BIT(26) | BIT(25) | BIT(24))
  58
  59 #define BYT_NGPIO_SCORE         102
  60 #define BYT_NGPIO_NCORE         28
  61 #define BYT_NGPIO_SUS           44
  62
  63 /*
  64  * Baytrail gpio controller consist of three separate sub-controllers called
  65  * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
  66  *
  67  * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
  68  * _not_ correspond to the first gpio register at controller's gpio base.
  69  * There is no logic or pattern in mapping gpio numbers to registers (pads) so
  70  * each sub-controller needs to have its own mapping table
  71  */
  72
  73 /* score_pins[gpio_nr] = pad_nr */
  74
  75 static unsigned const score_pins[BYT_NGPIO_SCORE] = {
  76         85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
  77         36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
  78         54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
  79         52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
  80         95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
  81         86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
  82         80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
  83         2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
  84         31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
  85         24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
  86         97, 100,
  87 };
  88
  89 static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
  90         19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
  91         14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
  92         3, 6, 10, 13, 2, 5, 9, 7,
  93 };
  94
  95 static unsigned const sus_pins[BYT_NGPIO_SUS] = {
  96         29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
  97         18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
  98         0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
  99         26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
 100         52, 53, 59, 40,
 101 };
 102
 103 static struct pinctrl_gpio_range byt_ranges[] = {
 104         {
 105                 .name = "1", /* match with acpi _UID in probe */
 106                 .npins = BYT_NGPIO_SCORE,
 107                 .pins = score_pins,
 108         },
 109         {
 110                 .name = "2",
 111                 .npins = BYT_NGPIO_NCORE,
 112                 .pins = ncore_pins,
 113         },
 114         {
 115                 .name = "3",
 116                 .npins = BYT_NGPIO_SUS,
 117                 .pins = sus_pins,
 118         },
 119         {
 120         },
 121 };
 122
 123 struct byt_gpio {
 124         struct gpio_chip                chip;
 125         struct irq_domain               *domain;
 126         struct platform_device          *pdev;
 127         spinlock_t                      lock;
 128         void __iomem                    *reg_base;
 129         struct pinctrl_gpio_range       *range;
 130 };
 131
 132 #define to_byt_gpio(c)  container_of(c, struct byt_gpio, chip)
 133
 134 static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
 135                                  int reg)
 136 {
 137         struct byt_gpio *vg = to_byt_gpio(chip);
 138         u32 reg_offset;
 139
 140         if (reg == BYT_INT_STAT_REG)
 141                 reg_offset = (offset / 32) * 4;
 142         else
 143                 reg_offset = vg->range->pins[offset] * 16;
 144
 145         return vg->reg_base + reg_offset + reg;
 146 }
 147
 148 static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
 149 {
 150         struct byt_gpio *vg = to_byt_gpio(chip);
 151
 152         pm_runtime_get(&vg->pdev->dev);
 153
 154         return 0;
 155 }
 156
 157 static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
 158 {
 159         struct byt_gpio *vg = to_byt_gpio(chip);
 160         void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
 161         u32 value;
 162
 163         /* clear interrupt triggering */
 164         value = readl(reg);
 165         value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
 166         writel(value, reg);
 167
 168         pm_runtime_put(&vg->pdev->dev);
 169 }
 170
 171 static int byt_irq_type(struct irq_data *d, unsigned type)
 172 {
 173         struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
 174         u32 offset = irqd_to_hwirq(d);
 175         u32 value;
 176         unsigned long flags;
 177         void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
 178
 179         if (offset >= vg->chip.ngpio)
 180                 return -EINVAL;
 181
 182         spin_lock_irqsave(&vg->lock, flags);
 183         value = readl(reg);
 184
 185         /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
 186          * are used to indicate high and low level triggering
 187          */
 188         value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
 189
 190         switch (type) {
 191         case IRQ_TYPE_LEVEL_HIGH:
 192                 value |= BYT_TRIG_LVL;
 193         case IRQ_TYPE_EDGE_RISING:
 194                 value |= BYT_TRIG_POS;
 195                 break;
 196         case IRQ_TYPE_LEVEL_LOW:
 197                 value |= BYT_TRIG_LVL;
 198         case IRQ_TYPE_EDGE_FALLING:
 199                 value |= BYT_TRIG_NEG;
 200                 break;
 201         case IRQ_TYPE_EDGE_BOTH:
 202                 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
 203                 break;
 204         }
 205         writel(value, reg);
 206
 207         spin_unlock_irqrestore(&vg->lock, flags);
 208
 209         return 0;
 210 }
 211
 212 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
 213 {
 214         void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
 215         return readl(reg) & BYT_LEVEL;
 216 }
 217
 218 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 219 {
 220         struct byt_gpio *vg = to_byt_gpio(chip);
 221         void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
 222         unsigned long flags;
 223         u32 old_val;
 224
 225         spin_lock_irqsave(&vg->lock, flags);
 226
 227         old_val = readl(reg);
 228
 229         if (value)
 230                 writel(old_val | BYT_LEVEL, reg);
 231         else
 232                 writel(old_val & ~BYT_LEVEL, reg);
 233
 234         spin_unlock_irqrestore(&vg->lock, flags);
 235 }
 236
 237 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 238 {
 239         struct byt_gpio *vg = to_byt_gpio(chip);
 240         void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
 241         unsigned long flags;
 242         u32 value;
 243
 244         spin_lock_irqsave(&vg->lock, flags);
 245
 246         value = readl(reg) | BYT_DIR_MASK;
 247         value &= ~BYT_INPUT_EN;         /* active low */
 248         writel(value, reg);
 249
 250         spin_unlock_irqrestore(&vg->lock, flags);
 251
 252         return 0;
 253 }
 254
 255 static int byt_gpio_direction_output(struct gpio_chip *chip,
 256                                      unsigned gpio, int value)
 257 {
 258         struct byt_gpio *vg = to_byt_gpio(chip);
 259         void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
 260         unsigned long flags;
 261         u32 reg_val;
 262
 263         spin_lock_irqsave(&vg->lock, flags);
 264
 265         reg_val = readl(reg) | BYT_DIR_MASK;
 266         reg_val &= ~BYT_OUTPUT_EN;
 267
 268         if (value)
 269                 writel(reg_val | BYT_LEVEL, reg);
 270         else
 271                 writel(reg_val & ~BYT_LEVEL, reg);
 272
 273         spin_unlock_irqrestore(&vg->lock, flags);
 274
 275         return 0;
 276 }
 277
 278 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 279 {
 280         struct byt_gpio *vg = to_byt_gpio(chip);
 281         int i;
 282         unsigned long flags;
 283         u32 conf0, val, offs;
 284
 285         spin_lock_irqsave(&vg->lock, flags);
 286
 287         for (i = 0; i < vg->chip.ngpio; i++) {
 288                 const char *label;
 289                 offs = vg->range->pins[i] * 16;
 290                 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
 291                 val = readl(vg->reg_base + offs + BYT_VAL_REG);
 292
 293                 label = gpiochip_is_requested(chip, i);
 294                 if (!label)
 295                         label = "Unrequested";
 296
 297                 seq_printf(s,
 298                            " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n",
 299                            i,
 300                            label,
 301                            val & BYT_INPUT_EN ? "  " : "in",
 302                            val & BYT_OUTPUT_EN ? "   " : "out",
 303                            val & BYT_LEVEL ? "hi" : "lo",
 304                            vg->range->pins[i], offs,
 305                            conf0 & 0x7,
 306                            conf0 & BYT_TRIG_NEG ? " fall" : "",
 307                            conf0 & BYT_TRIG_POS ? " rise" : "",
 308                            conf0 & BYT_TRIG_LVL ? " level" : "");
 309         }
 310         spin_unlock_irqrestore(&vg->lock, flags);
 311 }
 312
 313 static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 314 {
 315         struct byt_gpio *vg = to_byt_gpio(chip);
 316         return irq_create_mapping(vg->domain, offset);
 317 }
 318
 319 static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 320 {
 321         struct irq_data *data = irq_desc_get_irq_data(desc);
 322         struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
 323         struct irq_chip *chip = irq_data_get_irq_chip(data);
 324         u32 base, pin, mask;
 325         void __iomem *reg;
 326         u32 pending;
 327         unsigned virq;
 328         int looplimit = 0;
 329
 330         /* check from GPIO controller which pin triggered the interrupt */
 331         for (base = 0; base < vg->chip.ngpio; base += 32) {
 332
 333                 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
 334
 335                 while ((pending = readl(reg))) {
 336                         pin = __ffs(pending);
 337                         mask = BIT(pin);
 338                         /* Clear before handling so we can't lose an edge */
 339                         writel(mask, reg);
 340
 341                         virq = irq_find_mapping(vg->domain, base + pin);
 342                         generic_handle_irq(virq);
 343
 344                         /* In case bios or user sets triggering incorretly a pin
 345                          * might remain in "interrupt triggered" state.
 346                          */
 347                         if (looplimit++ > 32) {
 348                                 dev_err(&vg->pdev->dev,
 349                                         "Gpio %d interrupt flood, disabling\n",
 350                                         base + pin);
 351
 352                                 reg = byt_gpio_reg(&vg->chip, base + pin,
 353                                                    BYT_CONF0_REG);
 354                                 mask = readl(reg);
 355                                 mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
 356                                           BYT_TRIG_LVL);
 357                                 writel(mask, reg);
 358                                 mask = readl(reg); /* flush */
 359                                 break;
 360                         }
 361                 }
 362         }
 363         chip->irq_eoi(data);
 364 }
 365
 366 static void byt_irq_unmask(struct irq_data *d)
 367 {
 368 }
 369
 370 static void byt_irq_mask(struct irq_data *d)
 371 {
 372 }
 373
 374 static unsigned int byt_irq_startup(struct irq_data *d)
 375 {
 376         struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
 377
 378         if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d)))
 379                 dev_err(vg->chip.dev,
 380                         "unable to lock HW IRQ %lu for IRQ\n",
 381                         irqd_to_hwirq(d));
 382         byt_irq_unmask(d);
 383         return 0;
 384 }
 385
 386 static void byt_irq_shutdown(struct irq_data *d)
 387 {
 388         struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
 389
 390         byt_irq_mask(d);
 391         gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
 392 }
 393
 394 static struct irq_chip byt_irqchip = {
 395         .name = "BYT-GPIO",
 396         .irq_mask = byt_irq_mask,
 397         .irq_unmask = byt_irq_unmask,
 398         .irq_set_type = byt_irq_type,
 399         .irq_startup = byt_irq_startup,
 400         .irq_shutdown = byt_irq_shutdown,
 401 };
 402
 403 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
 404 {
 405         void __iomem *reg;
 406         u32 base, value;
 407
 408         /* clear interrupt status trigger registers */
 409         for (base = 0; base < vg->chip.ngpio; base += 32) {
 410                 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
 411                 writel(0xffffffff, reg);
 412                 /* make sure trigger bits are cleared, if not then a pin
 413                    might be misconfigured in bios */
 414                 value = readl(reg);
 415                 if (value)
 416                         dev_err(&vg->pdev->dev,
 417                                 "GPIO interrupt error, pins misconfigured\n");
 418         }
 419 }
 420
 421 static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
 422                             irq_hw_number_t hw)
 423 {
 424         struct byt_gpio *vg = d->host_data;
 425
 426         irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
 427                                       "demux");
 428         irq_set_chip_data(virq, vg);
 429         irq_set_irq_type(virq, IRQ_TYPE_NONE);
 430
 431         return 0;
 432 }
 433
 434 static const struct irq_domain_ops byt_gpio_irq_ops = {
 435         .map = byt_gpio_irq_map,
 436 };
 437
 438 static int byt_gpio_probe(struct platform_device *pdev)
 439 {
 440         struct byt_gpio *vg;
 441         struct gpio_chip *gc;
 442         struct resource *mem_rc, *irq_rc;
 443         struct device *dev = &pdev->dev;
 444         struct acpi_device *acpi_dev;
 445         struct pinctrl_gpio_range *range;
 446         acpi_handle handle = ACPI_HANDLE(dev);
 447         unsigned hwirq;
 448         int ret;
 449
 450         if (acpi_bus_get_device(handle, &acpi_dev))
 451                 return -ENODEV;
 452
 453         vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
 454         if (!vg) {
 455                 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
 456                 return -ENOMEM;
 457         }
 458
 459         for (range = byt_ranges; range->name; range++) {
 460                 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
 461                         vg->chip.ngpio = range->npins;
 462                         vg->range = range;
 463                         break;
 464                 }
 465         }
 466
 467         if (!vg->chip.ngpio || !vg->range)
 468                 return -ENODEV;
 469
 470         vg->pdev = pdev;
 471         platform_set_drvdata(pdev, vg);
 472
 473         mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 474         vg->reg_base = devm_ioremap_resource(dev, mem_rc);
 475         if (IS_ERR(vg->reg_base))
 476                 return PTR_ERR(vg->reg_base);
 477
 478         spin_lock_init(&vg->lock);
 479
 480         gc = &vg->chip;
 481         gc->label = dev_name(&pdev->dev);
 482         gc->owner = THIS_MODULE;
 483         gc->request = byt_gpio_request;
 484         gc->free = byt_gpio_free;
 485         gc->direction_input = byt_gpio_direction_input;
 486         gc->direction_output = byt_gpio_direction_output;
 487         gc->get = byt_gpio_get;
 488         gc->set = byt_gpio_set;
 489         gc->dbg_show = byt_gpio_dbg_show;
 490         gc->base = -1;
 491         gc->can_sleep = false;
 492         gc->dev = dev;
 493
 494         ret = gpiochip_add(gc);
 495         if (ret) {
 496                 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
 497                 return ret;
 498         }
 499
 500         /* set up interrupts  */
 501         irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 502         if (irq_rc && irq_rc->start) {
 503                 hwirq = irq_rc->start;
 504                 gc->to_irq = byt_gpio_to_irq;
 505
 506                 vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
 507                                                    &byt_gpio_irq_ops, vg);
 508                 if (!vg->domain)
 509                         return -ENXIO;
 510
 511                 byt_gpio_irq_init_hw(vg);
 512
 513                 irq_set_handler_data(hwirq, vg);
 514                 irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
 515         }
 516
 517         pm_runtime_enable(dev);
 518
 519         return 0;
 520 }
 521
 522 static int byt_gpio_runtime_suspend(struct device *dev)
 523 {
 524         return 0;
 525 }
 526
 527 static int byt_gpio_runtime_resume(struct device *dev)
 528 {
 529         return 0;
 530 }
 531
 532 static const struct dev_pm_ops byt_gpio_pm_ops = {
 533         .runtime_suspend = byt_gpio_runtime_suspend,
 534         .runtime_resume = byt_gpio_runtime_resume,
 535 };
 536
 537 static const struct acpi_device_id byt_gpio_acpi_match[] = {
 538         { "INT33B2", 0 },
 539         { }
 540 };
 541 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
 542
 543 static int byt_gpio_remove(struct platform_device *pdev)
 544 {
 545         struct byt_gpio *vg = platform_get_drvdata(pdev);
 546         int err;
 547
 548         pm_runtime_disable(&pdev->dev);
 549         err = gpiochip_remove(&vg->chip);
 550         if (err)
 551                 dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
 552
 553         return 0;
 554 }
 555
 556 static struct platform_driver byt_gpio_driver = {
 557         .probe          = byt_gpio_probe,
 558         .remove         = byt_gpio_remove,
 559         .driver         = {
 560                 .name   = "byt_gpio",
 561                 .owner  = THIS_MODULE,
 562                 .pm     = &byt_gpio_pm_ops,
 563                 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
 564         },
 565 };
 566
 567 static int __init byt_gpio_init(void)
 568 {
 569         return platform_driver_register(&byt_gpio_driver);
 570 }
 571
 572 subsys_initcall(byt_gpio_init);