drivers/pinctrl/pinctrl-samsung.h

   1 /*
   2  * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2012 Linaro Ltd
   7  *              http://www.linaro.org
   8  *
   9  * Author: Thomas Abraham <thomas.ab@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #ifndef __PINCTRL_SAMSUNG_H
  18 #define __PINCTRL_SAMSUNG_H
  19
  20 #include <linux/pinctrl/pinctrl.h>
  21 #include <linux/pinctrl/pinmux.h>
  22 #include <linux/pinctrl/pinconf.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pinctrl/machine.h>
  25
  26 #include <linux/gpio.h>
  27
  28 /* pinmux function number for pin as gpio output line */
  29 #define FUNC_OUTPUT     0x1
  30
  31 /**
  32  * enum pincfg_type - possible pin configuration types supported.
  33  * @PINCFG_TYPE_FUNC: Function configuration.
  34  * @PINCFG_TYPE_DAT: Pin value configuration.
  35  * @PINCFG_TYPE_PUD: Pull up/down configuration.
  36  * @PINCFG_TYPE_DRV: Drive strength configuration.
  37  * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
  38  * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
  39  */
  40 enum pincfg_type {
  41         PINCFG_TYPE_FUNC,
  42         PINCFG_TYPE_DAT,
  43         PINCFG_TYPE_PUD,
  44         PINCFG_TYPE_DRV,
  45         PINCFG_TYPE_CON_PDN,
  46         PINCFG_TYPE_PUD_PDN,
  47
  48         PINCFG_TYPE_NUM
  49 };
  50
  51 /*
  52  * pin configuration (pull up/down and drive strength) type and its value are
  53  * packed together into a 16-bits. The upper 8-bits represent the configuration
  54  * type and the lower 8-bits hold the value of the configuration type.
  55  */
  56 #define PINCFG_TYPE_MASK                0xFF
  57 #define PINCFG_VALUE_SHIFT              8
  58 #define PINCFG_VALUE_MASK               (0xFF << PINCFG_VALUE_SHIFT)
  59 #define PINCFG_PACK(type, value)        (((value) << PINCFG_VALUE_SHIFT) | type)
  60 #define PINCFG_UNPACK_TYPE(cfg)         ((cfg) & PINCFG_TYPE_MASK)
  61 #define PINCFG_UNPACK_VALUE(cfg)        (((cfg) & PINCFG_VALUE_MASK) >> \
  62                                                 PINCFG_VALUE_SHIFT)
  63 /**
  64  * enum eint_type - possible external interrupt types.
  65  * @EINT_TYPE_NONE: bank does not support external interrupts
  66  * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
  67  * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
  68  * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
  69  *
  70  * Samsung GPIO controller groups all the available pins into banks. The pins
  71  * in a pin bank can support external gpio interrupts or external wakeup
  72  * interrupts or no interrupts at all. From a software perspective, the only
  73  * difference between external gpio and external wakeup interrupts is that
  74  * the wakeup interrupts can additionally wakeup the system if it is in
  75  * suspended state.
  76  */
  77 enum eint_type {
  78         EINT_TYPE_NONE,
  79         EINT_TYPE_GPIO,
  80         EINT_TYPE_WKUP,
  81         EINT_TYPE_WKUP_MUX,
  82 };
  83
  84 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
  85 #define PIN_NAME_LENGTH 10
  86
  87 #define PIN_GROUP(n, p, f)                              \
  88         {                                               \
  89                 .name           = n,                    \
  90                 .pins           = p,                    \
  91                 .num_pins       = ARRAY_SIZE(p),        \
  92                 .func           = f                     \
  93         }
  94
  95 #define PMX_FUNC(n, g)                                  \
  96         {                                               \
  97                 .name           = n,                    \
  98                 .groups         = g,                    \
  99                 .num_groups     = ARRAY_SIZE(g),        \
 100         }
 101
 102 struct samsung_pinctrl_drv_data;
 103
 104 /**
 105  * struct samsung_pin_bank_type: pin bank type description
 106  * @fld_width: widths of configuration bitfields (0 if unavailable)
 107  * @reg_offset: offsets of configuration registers (don't care of width is 0)
 108  */
 109 struct samsung_pin_bank_type {
 110         u8 fld_width[PINCFG_TYPE_NUM];
 111         u8 reg_offset[PINCFG_TYPE_NUM];
 112 };
 113
 114 /**
 115  * struct samsung_pin_bank: represent a controller pin-bank.
 116  * @type: type of the bank (register offsets and bitfield widths)
 117  * @pctl_offset: starting offset of the pin-bank registers.
 118  * @pin_base: starting pin number of the bank.
 119  * @nr_pins: number of pins included in this bank.
 120  * @eint_func: function to set in CON register to configure pin as EINT.
 121  * @eint_type: type of the external interrupt supported by the bank.
 122  * @eint_mask: bit mask of pins which support EINT function.
 123  * @name: name to be prefixed for each pin in this pin bank.
 124  * @of_node: OF node of the bank.
 125  * @drvdata: link to controller driver data
 126  * @irq_domain: IRQ domain of the bank.
 127  * @gpio_chip: GPIO chip of the bank.
 128  * @grange: linux gpio pin range supported by this bank.
 129  * @slock: spinlock protecting bank registers
 130  * @pm_save: saved register values during suspend
 131  */
 132 struct samsung_pin_bank {
 133         struct samsung_pin_bank_type *type;
 134         u32             pctl_offset;
 135         u32             pin_base;
 136         u8              nr_pins;
 137         u8              eint_func;
 138         enum eint_type  eint_type;
 139         u32             eint_mask;
 140         u32             eint_offset;
 141         char            *name;
 142         void            *soc_priv;
 143         struct device_node *of_node;
 144         struct samsung_pinctrl_drv_data *drvdata;
 145         struct irq_domain *irq_domain;
 146         struct gpio_chip gpio_chip;
 147         struct pinctrl_gpio_range grange;
 148         spinlock_t slock;
 149
 150         u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
 151 };
 152
 153 /**
 154  * struct samsung_pin_ctrl: represent a pin controller.
 155  * @pin_banks: list of pin banks included in this controller.
 156  * @nr_banks: number of pin banks.
 157  * @base: starting system wide pin number.
 158  * @nr_pins: number of pins supported by the controller.
 159  * @geint_con: offset of the ext-gpio controller registers.
 160  * @geint_mask: offset of the ext-gpio interrupt mask registers.
 161  * @geint_pend: offset of the ext-gpio interrupt pending registers.
 162  * @weint_con: offset of the ext-wakeup controller registers.
 163  * @weint_mask: offset of the ext-wakeup interrupt mask registers.
 164  * @weint_pend: offset of the ext-wakeup interrupt pending registers.
 165  * @svc: offset of the interrupt service register.
 166  * @eint_gpio_init: platform specific callback to setup the external gpio
 167  *      interrupts for the controller.
 168  * @eint_wkup_init: platform specific callback to setup the external wakeup
 169  *      interrupts for the controller.
 170  * @label: for debug information.
 171  */
 172 struct samsung_pin_ctrl {
 173         struct samsung_pin_bank *pin_banks;
 174         u32             nr_banks;
 175
 176         u32             base;
 177         u32             nr_pins;
 178
 179         u32             geint_con;
 180         u32             geint_mask;
 181         u32             geint_pend;
 182
 183         u32             weint_con;
 184         u32             weint_mask;
 185         u32             weint_pend;
 186
 187         u32             svc;
 188
 189         int             (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
 190         int             (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
 191         void            (*suspend)(struct samsung_pinctrl_drv_data *);
 192         void            (*resume)(struct samsung_pinctrl_drv_data *);
 193
 194         char            *label;
 195 };
 196
 197 /**
 198  * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
 199  * @node: global list node
 200  * @virt_base: register base address of the controller.
 201  * @dev: device instance representing the controller.
 202  * @irq: interrpt number used by the controller to notify gpio interrupts.
 203  * @ctrl: pin controller instance managed by the driver.
 204  * @pctl: pin controller descriptor registered with the pinctrl subsystem.
 205  * @pctl_dev: cookie representing pinctrl device instance.
 206  * @pin_groups: list of pin groups available to the driver.
 207  * @nr_groups: number of such pin groups.
 208  * @pmx_functions: list of pin functions available to the driver.
 209  * @nr_function: number of such pin functions.
 210  */
 211 struct samsung_pinctrl_drv_data {
 212         struct list_head                node;
 213         void __iomem                    *virt_base;
 214         struct device                   *dev;
 215         int                             irq;
 216
 217         struct samsung_pin_ctrl         *ctrl;
 218         struct pinctrl_desc             pctl;
 219         struct pinctrl_dev              *pctl_dev;
 220
 221         const struct samsung_pin_group  *pin_groups;
 222         unsigned int                    nr_groups;
 223         const struct samsung_pmx_func   *pmx_functions;
 224         unsigned int                    nr_functions;
 225 };
 226
 227 /**
 228  * struct samsung_pin_group: represent group of pins of a pinmux function.
 229  * @name: name of the pin group, used to lookup the group.
 230  * @pins: the pins included in this group.
 231  * @num_pins: number of pins included in this group.
 232  * @func: the function number to be programmed when selected.
 233  */
 234 struct samsung_pin_group {
 235         const char              *name;
 236         const unsigned int      *pins;
 237         u8                      num_pins;
 238         u8                      func;
 239 };
 240
 241 /**
 242  * struct samsung_pmx_func: represent a pin function.
 243  * @name: name of the pin function, used to lookup the function.
 244  * @groups: one or more names of pin groups that provide this function.
 245  * @num_groups: number of groups included in @groups.
 246  */
 247 struct samsung_pmx_func {
 248         const char              *name;
 249         const char              **groups;
 250         u8                      num_groups;
 251 };
 252
 253 /* list of all exported SoC specific data */
 254 extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
 255 extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
 256 extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
 257 extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];
 258 extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
 259 extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
 260 extern struct samsung_pin_ctrl s3c2416_pin_ctrl[];
 261 extern struct samsung_pin_ctrl s3c2440_pin_ctrl[];
 262 extern struct samsung_pin_ctrl s3c2450_pin_ctrl[];
 263 extern struct samsung_pin_ctrl s5pv210_pin_ctrl[];
 264
 265 #endif /* __PINCTRL_SAMSUNG_H */