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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / drivers / staging / rtl8821ae / pci.c
blobcfa651edd2381ebbfa33a964b514bddb45981dc0
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "core.h"
31 #include "wifi.h"
32 #include "pci.h"
33 #include "base.h"
34 #include "ps.h"
35 #include "efuse.h"
36 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
37 #include <linux/export.h>
38 #endif
39
40 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
41 INTEL_VENDOR_ID,
42 ATI_VENDOR_ID,
43 AMD_VENDOR_ID,
44 SIS_VENDOR_ID
45 };
46
47 static const u8 ac_to_hwq[] = {
48 VO_QUEUE,
49 VI_QUEUE,
50 BE_QUEUE,
51 BK_QUEUE
52 };
53
54 u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
55 struct sk_buff *skb)
56 {
57 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
58 u16 fc = rtl_get_fc(skb);
59 u8 queue_index = skb_get_queue_mapping(skb);
60
61 if (unlikely(ieee80211_is_beacon(fc)))
62 return BEACON_QUEUE;
63 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
64 return MGNT_QUEUE;
65 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
66 if (ieee80211_is_nullfunc(fc))
67 return HIGH_QUEUE;
68
69 return ac_to_hwq[queue_index];
70 }
71
72 /* Update PCI dependent default settings*/
73 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
74 {
75 struct rtl_priv *rtlpriv = rtl_priv(hw);
76 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
77 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
78 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
79 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
80 u8 init_aspm;
81
82 ppsc->reg_rfps_level = 0;
83 ppsc->b_support_aspm = 0;
84
85 /*Update PCI ASPM setting */
86 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
87 switch (rtlpci->const_pci_aspm) {
88 case 0:
89 /*No ASPM */
90 break;
91
92 case 1:
93 /*ASPM dynamically enabled/disable. */
94 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
95 break;
96
97 case 2:
98 /*ASPM with Clock Req dynamically enabled/disable. */
99 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
100 RT_RF_OFF_LEVL_CLK_REQ);
101 break;
102
103 case 3:
104 /*
105 * Always enable ASPM and Clock Req
106 * from initialization to halt.
107 * */
108 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
109 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
110 RT_RF_OFF_LEVL_CLK_REQ);
111 break;
112
113 case 4:
114 /*
115 * Always enable ASPM without Clock Req
116 * from initialization to halt.
117 * */
118 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
119 RT_RF_OFF_LEVL_CLK_REQ);
120 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
121 break;
122 }
123
124 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
125
126 /*Update Radio OFF setting */
127 switch (rtlpci->const_hwsw_rfoff_d3) {
128 case 1:
129 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
130 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
131 break;
132
133 case 2:
134 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
135 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
136 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
137 break;
138
139 case 3:
140 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
141 break;
142 }
143
144 /*Set HW definition to determine if it supports ASPM. */
145 switch (rtlpci->const_support_pciaspm) {
146 case 0:{
147 /*Not support ASPM. */
148 bool b_support_aspm = false;
149 ppsc->b_support_aspm = b_support_aspm;
150 break;
151 }
152 case 1:{
153 /*Support ASPM. */
154 bool b_support_aspm = true;
155 bool b_support_backdoor = true;
156 ppsc->b_support_aspm = b_support_aspm;
157
158 /*if(priv->oem_id == RT_CID_TOSHIBA &&
159 !priv->ndis_adapter.amd_l1_patch)
160 b_support_backdoor = false; */
161
162 ppsc->b_support_backdoor = b_support_backdoor;
163
164 break;
165 }
166 case 2:
167 /*ASPM value set by chipset. */
168 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
169 bool b_support_aspm = true;
170 ppsc->b_support_aspm = b_support_aspm;
171 }
172 break;
173 default:
174 RT_TRACE(COMP_ERR, DBG_EMERG,
175 ("switch case not process \n"));
176 break;
177 }
178
179 /* toshiba aspm issue, toshiba will set aspm selfly
180 * so we should not set aspm in driver */
181 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
182 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
183 init_aspm == 0x43)
184 ppsc->b_support_aspm = false;
185 }
186
187 static bool _rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw *hw,
188 u8 value)
189 {
190 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192 bool bresult = false;
193
194 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
195 value |= 0x40;
196
197 pci_write_config_byte(rtlpci->pdev, 0x80, value);
198
199 return bresult;
200 }
201
202 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
203 static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
204 {
205 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
206 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
207 bool bresult = false;
208
209 pci_write_config_byte(rtlpci->pdev, 0x81, value);
210 bresult = true;
211
212 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
213 udelay(100);
214
215 return bresult;
216 }
217
218 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
219 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
220 {
221 struct rtl_priv *rtlpriv = rtl_priv(hw);
222 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
223 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
224 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
225 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
226 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
227 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
228 /*Retrieve original configuration settings. */
229 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
230 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
231 pcibridge_linkctrlreg;
232 u16 aspmlevel = 0;
233
234 if (!ppsc->b_support_aspm)
235 return;
236
237 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
238 RT_TRACE(COMP_POWER, DBG_TRACE,
239 ("PCI(Bridge) UNKNOWN.\n"));
240
241 return;
242 }
243
244 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
245 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
246 _rtl_pci_switch_clk_req(hw, 0x0);
247 }
248
249 if (1) {
250 /*for promising device will in L0 state after an I/O. */
251 u8 tmp_u1b;
252 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
253 }
254
255 /*Set corresponding value. */
256 aspmlevel |= BIT(0) | BIT(1);
257 linkctrl_reg &= ~aspmlevel;
258 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
259
260 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
261 udelay(50);
262
263 /*4 Disable Pci Bridge ASPM */
264 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
265 pcicfg_addrport + (num4bytes << 2));
266 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
267
268 udelay(50);
269
270 }
271
272 /*
273 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
274 *power saving We should follow the sequence to enable
275 *RTL8192SE first then enable Pci Bridge ASPM
276 *or the system will show bluescreen.
277 */
278 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
279 {
280 struct rtl_priv *rtlpriv = rtl_priv(hw);
281 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
282 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
283 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
284 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
285 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
286 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
287 u16 aspmlevel;
288 u8 u_pcibridge_aspmsetting;
289 u8 u_device_aspmsetting;
290
291 if (!ppsc->b_support_aspm)
292 return;
293
294 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
295 RT_TRACE(COMP_POWER, DBG_TRACE,
296 ("PCI(Bridge) UNKNOWN.\n"));
297 return;
298 }
299
300 /*4 Enable Pci Bridge ASPM */
301 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
302 pcicfg_addrport + (num4bytes << 2));
303
304 u_pcibridge_aspmsetting =
305 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
306 rtlpci->const_hostpci_aspm_setting;
307
308 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
309 u_pcibridge_aspmsetting &= ~BIT(0);
310
311 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
312
313 RT_TRACE(COMP_INIT, DBG_LOUD,
314 ("PlatformEnableASPM(): Write reg[%x] = %x\n",
315 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
316 u_pcibridge_aspmsetting));
317
318 udelay(50);
319
320 /*Get ASPM level (with/without Clock Req) */
321 aspmlevel = rtlpci->const_devicepci_aspm_setting;
322 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
323
324 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
325 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
326
327 u_device_aspmsetting |= aspmlevel;
328
329 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
330
331 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
332 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
333 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
334 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
335 }
336 udelay(100);
337 }
338
339 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
340 {
341 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
342 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
343
344 bool status = false;
345 u8 offset_e0;
346 unsigned offset_e4;
347
348 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
349 pcicfg_addrport + 0xE0);
350 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
351
352 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
353 pcicfg_addrport + 0xE0);
354 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
355
356 if (offset_e0 == 0xA0) {
357 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
358 pcicfg_addrport + 0xE4);
359 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
360 if (offset_e4 & BIT(23))
361 status = true;
362 }
363
364 return status;
365 }
366
367 /*<delete in kernel start>*/
368 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35))
369 static u8 _rtl_pci_get_pciehdr_offset(struct ieee80211_hw *hw)
370 {
371 u8 capability_offset;
372 u8 num4bytes = 0x34/4;
373 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
374 u32 pcicfg_addr_port = (pcipriv->ndis_adapter.pcibridge_busnum << 16)|
375 (pcipriv->ndis_adapter.pcibridge_devnum << 11)|
376 (pcipriv->ndis_adapter.pcibridge_funcnum << 8)|
377 (1 << 31);
378
379 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS , pcicfg_addr_port
380 + (num4bytes << 2));
381 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &capability_offset);
382 while (capability_offset != 0) {
383 struct rtl_pci_capabilities_header capability_hdr;
384
385 num4bytes = capability_offset / 4;
386 /* Read the header of the capability at this offset.
387 * If the retrieved capability is not the power management
388 * capability that we are looking for, follow the link to
389 * the next capability and continue looping.
390 */
391 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS ,
392 pcicfg_addr_port +
393 (num4bytes << 2));
394 rtl_pci_raw_read_port_ushort(PCI_CONF_DATA,
395 (u16*)&capability_hdr);
396 /* Found the PCI express capability. */
397 if (capability_hdr.capability_id ==
398 PCI_CAPABILITY_ID_PCI_EXPRESS)
399 break;
400 else
401 capability_offset = capability_hdr.next;
402 }
403 return capability_offset;
404 }
405 #endif
406 /*<delete in kernel end>*/
407
408 bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
409 struct rtl_priv **buddy_priv)
410 {
411 struct rtl_priv *rtlpriv = rtl_priv(hw);
412 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
413 bool b_find_buddy_priv = false;
414 struct rtl_priv *temp_priv = NULL;
415 struct rtl_pci_priv *temp_pcipriv = NULL;
416
417 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
418 list_for_each_entry(temp_priv, &rtlpriv->glb_var->glb_priv_list,
419 list) {
420 if (temp_priv) {
421 temp_pcipriv =
422 (struct rtl_pci_priv *)temp_priv->priv;
423 RT_TRACE(COMP_INIT, DBG_LOUD,
424 (("pcipriv->ndis_adapter.funcnumber %x \n"),
425 pcipriv->ndis_adapter.funcnumber));
426 RT_TRACE(COMP_INIT, DBG_LOUD,
427 (("temp_pcipriv->ndis_adapter.funcnumber %x \n"),
428 temp_pcipriv->ndis_adapter.funcnumber));
429
430 if ((pcipriv->ndis_adapter.busnumber ==
431 temp_pcipriv->ndis_adapter.busnumber) &&
432 (pcipriv->ndis_adapter.devnumber ==
433 temp_pcipriv->ndis_adapter.devnumber) &&
434 (pcipriv->ndis_adapter.funcnumber !=
435 temp_pcipriv->ndis_adapter.funcnumber)) {
436 b_find_buddy_priv = true;
437 break;
438 }
439 }
440 }
441 }
442
443 RT_TRACE(COMP_INIT, DBG_LOUD,
444 (("b_find_buddy_priv %d \n"), b_find_buddy_priv));
445
446 if (b_find_buddy_priv)
447 *buddy_priv = temp_priv;
448
449 return b_find_buddy_priv;
450 }
451
452 void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
453 {
454 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
455 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
456 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
457 u8 linkctrl_reg;
458 u8 num4bbytes;
459
460 num4bbytes = (capabilityoffset + 0x10) / 4;
461
462 /*Read Link Control Register */
463 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
464 pcicfg_addrport + (num4bbytes << 2));
465 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
466
467 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
468 }
469
470 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
471 struct ieee80211_hw *hw)
472 {
473 struct rtl_priv *rtlpriv = rtl_priv(hw);
474 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
475
476 u8 tmp;
477 int pos;
478 u8 linkctrl_reg;
479
480 /*Link Control Register */
481 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
482 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
483 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
484
485 RT_TRACE(COMP_INIT, DBG_TRACE,
486 ("Link Control Register =%x\n",
487 pcipriv->ndis_adapter.linkctrl_reg));
488
489 pci_read_config_byte(pdev, 0x98, &tmp);
490 tmp |= BIT(4);
491 pci_write_config_byte(pdev, 0x98, tmp);
492
493 tmp = 0x17;
494 pci_write_config_byte(pdev, 0x70f, tmp);
495 }
496
497 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
498 {
499 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
500
501 _rtl_pci_update_default_setting(hw);
502
503 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
504 /*Always enable ASPM & Clock Req. */
505 rtl_pci_enable_aspm(hw);
506 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
507 }
508
509 }
510
511 static void _rtl_pci_io_handler_init(struct device *dev,
512 struct ieee80211_hw *hw)
513 {
514 struct rtl_priv *rtlpriv = rtl_priv(hw);
515
516 rtlpriv->io.dev = dev;
517
518 rtlpriv->io.write8_async = pci_write8_async;
519 rtlpriv->io.write16_async = pci_write16_async;
520 rtlpriv->io.write32_async = pci_write32_async;
521
522 rtlpriv->io.read8_sync = pci_read8_sync;
523 rtlpriv->io.read16_sync = pci_read16_sync;
524 rtlpriv->io.read32_sync = pci_read32_sync;
525
526 }
527
528 static bool _rtl_pci_update_earlymode_info(struct ieee80211_hw *hw,
529 struct sk_buff *skb,
530 struct rtl_tcb_desc *tcb_desc,
531 u8 tid)
532 {
533 struct rtl_priv *rtlpriv = rtl_priv(hw);
534 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
535 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
536 u8 additionlen = FCS_LEN;
537 struct sk_buff *next_skb;
538
539 /* here open is 4, wep/tkip is 8, aes is 12*/
540 if (info->control.hw_key)
541 additionlen += info->control.hw_key->icv_len;
542
543 /* The most skb num is 6 */
544 tcb_desc->empkt_num = 0;
545 spin_lock_bh(&rtlpriv->locks.waitq_lock);
546 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
547 struct ieee80211_tx_info *next_info =
548 IEEE80211_SKB_CB(next_skb);
549 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
550 tcb_desc->empkt_len[tcb_desc->empkt_num] =
551 next_skb->len + additionlen;
552 tcb_desc->empkt_num++;
553 } else {
554 break;
555 }
556
557 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
558 next_skb))
559 break;
560
561 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
562 break;
563 }
564 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
565 return true;
566 }
567
568 /* just for early mode now */
569 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
570 {
571 struct rtl_priv *rtlpriv = rtl_priv(hw);
572 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
573 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
574 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
575 struct sk_buff *skb = NULL;
576 struct ieee80211_tx_info *info = NULL;
577 int tid; /* should be int */
578
579 if (!rtlpriv->rtlhal.b_earlymode_enable)
580 return;
581 if (rtlpriv->dm.supp_phymode_switch &&
582 (rtlpriv->easy_concurrent_ctl.bswitch_in_process ||
583 (rtlpriv->buddy_priv &&
584 rtlpriv->buddy_priv->easy_concurrent_ctl.bswitch_in_process)))
585 return;
586 /* we juse use em for BE/BK/VI/VO */
587 for (tid = 7; tid >= 0; tid--) {
588 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
589 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
590 while (!mac->act_scanning &&
591 rtlpriv->psc.rfpwr_state == ERFON) {
592 struct rtl_tcb_desc tcb_desc;
593 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
594
595 spin_lock_bh(&rtlpriv->locks.waitq_lock);
596 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
597 (ring->entries - skb_queue_len(&ring->queue) >
598 rtlhal->max_earlymode_num)) {
599 skb = skb_dequeue(&mac->skb_waitq[tid]);
600 } else {
601 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
602 break;
603 }
604 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
605
606 /* Some macaddr can't do early mode. like
607 * multicast/broadcast/no_qos data */
608 info = IEEE80211_SKB_CB(skb);
609 if (info->flags & IEEE80211_TX_CTL_AMPDU)
610 _rtl_pci_update_earlymode_info(hw, skb,
611 &tcb_desc, tid);
612
613 /*<delete in kernel start>*/
614 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
615 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
616 #else
617 /*<delete in kernel end>*/
618 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
619 #endif
620 /*<delete in kernel end>*/
621 }
622 }
623 }
624
625 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
626 {
627 struct rtl_priv *rtlpriv = rtl_priv(hw);
628 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
629 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
630
631 while (skb_queue_len(&ring->queue)) {
632 struct sk_buff *skb;
633 struct ieee80211_tx_info *info;
634 u16 fc;
635 u8 tid;
636 u8 *entry;
637
638
639 if (rtlpriv->use_new_trx_flow)
640 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
641 else
642 entry = (u8 *)(&ring->desc[ring->idx]);
643
644 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
645 return;
646
647 ring->idx = (ring->idx + 1) % ring->entries;
648
649 skb = __skb_dequeue(&ring->queue);
650
651 pci_unmap_single(rtlpci->pdev,
652 le32_to_cpu(rtlpriv->cfg->ops->
653 get_desc((u8 *) entry, true,
654 HW_DESC_TXBUFF_ADDR)),
655 skb->len, PCI_DMA_TODEVICE);
656
657 /* remove early mode header */
658 if(rtlpriv->rtlhal.b_earlymode_enable)
659 skb_pull(skb, EM_HDR_LEN);
660
661 RT_TRACE((COMP_INTR | COMP_SEND), DBG_TRACE,
662 ("new ring->idx:%d, "
663 "free: skb_queue_len:%d, free: seq:%d\n",
664 ring->idx,
665 skb_queue_len(&ring->queue),
666 *(u16 *) (skb->data + 22)));
667
668 if(prio == TXCMD_QUEUE) {
669 dev_kfree_skb(skb);
670 goto tx_status_ok;
671
672 }
673
674 /* for sw LPS, just after NULL skb send out, we can
675 * sure AP kown we are sleeped, our we should not let
676 * rf to sleep*/
677 fc = rtl_get_fc(skb);
678 if (ieee80211_is_nullfunc(fc)) {
679 if(ieee80211_has_pm(fc)) {
680 rtlpriv->mac80211.offchan_deley = true;
681 rtlpriv->psc.state_inap = 1;
682 } else {
683 rtlpriv->psc.state_inap = 0;
684 }
685 }
686 if (ieee80211_is_action(fc)) {
687 struct ieee80211_mgmt_compat *action_frame =
688 (struct ieee80211_mgmt_compat *)skb->data;
689 if (action_frame->u.action.u.ht_smps.action ==
690 WLAN_HT_ACTION_SMPS) {
691 dev_kfree_skb(skb);
692 goto tx_status_ok;
693 }
694 }
695
696 /* update tid tx pkt num */
697 tid = rtl_get_tid(skb);
698 if (tid <= 7)
699 rtlpriv->link_info.tidtx_inperiod[tid]++;
700
701 info = IEEE80211_SKB_CB(skb);
702 ieee80211_tx_info_clear_status(info);
703
704 info->flags |= IEEE80211_TX_STAT_ACK;
705 /*info->status.rates[0].count = 1; */
706
707 ieee80211_tx_status_irqsafe(hw, skb);
708
709 if ((ring->entries - skb_queue_len(&ring->queue))
710 == 2) {
711
712 RT_TRACE(COMP_ERR, DBG_LOUD,
713 ("more desc left, wake"
714 "skb_queue@%d,ring->idx = %d,"
715 "skb_queue_len = 0x%d\n",
716 prio, ring->idx,
717 skb_queue_len(&ring->queue)));
718
719 ieee80211_wake_queue(hw,
720 skb_get_queue_mapping
721 (skb));
722 }
723 tx_status_ok:
724 skb = NULL;
725 }
726
727 if (((rtlpriv->link_info.num_rx_inperiod +
728 rtlpriv->link_info.num_tx_inperiod) > 8) ||
729 (rtlpriv->link_info.num_rx_inperiod > 2)) {
730 rtl_lps_leave(hw);
731 }
732 }
733
734 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
735 u8 *entry, int rxring_idx, int desc_idx)
736 {
737 struct rtl_priv *rtlpriv = rtl_priv(hw);
738 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
739 u32 bufferaddress;
740 u8 tmp_one = 1;
741 struct sk_buff *skb;
742
743 skb = dev_alloc_skb(rtlpci->rxbuffersize);
744 if (!skb)
745 return 0;
746 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
747
748 /* just set skb->cb to mapping addr
749 * for pci_unmap_single use */
750 *((dma_addr_t *) skb->cb) = pci_map_single(rtlpci->pdev,
751 skb_tail_pointer(skb), rtlpci->rxbuffersize,
752 PCI_DMA_FROMDEVICE);
753 bufferaddress = cpu_to_le32(*((dma_addr_t *) skb->cb));
754 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
755 return 0;
756 if (rtlpriv->use_new_trx_flow) {
757 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry, false,
758 HW_DESC_RX_PREPARE,
759 (u8 *) & bufferaddress);
760 } else {
761 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry, false,
762 HW_DESC_RXBUFF_ADDR,
763 (u8 *) & bufferaddress);
764 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry, false,
765 HW_DESC_RXPKT_LEN,
766 (u8 *) & rtlpci->rxbuffersize);
767 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry, false,
768 HW_DESC_RXOWN,
769 (u8 *) & tmp_one);
770 }
771
772 return 1;
773 }
774
775 /* inorder to receive 8K AMSDU we have set skb to
776 * 9100bytes in init rx ring, but if this packet is
777 * not a AMSDU, this so big packet will be sent to
778 * TCP/IP directly, this cause big packet ping fail
779 * like: "ping -s 65507", so here we will realloc skb
780 * based on the true size of packet, I think mac80211
781 * do it will be better, but now mac80211 haven't */
782
783 /* but some platform will fail when alloc skb sometimes.
784 * in this condition, we will send the old skb to
785 * mac80211 directly, this will not cause any other
786 * issues, but only be losted by TCP/IP */
787 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
788 struct sk_buff *skb, struct ieee80211_rx_status rx_status)
789 {
790 if (unlikely(!rtl_action_proc(hw, skb, false))) {
791 dev_kfree_skb_any(skb);
792 } else {
793 struct sk_buff *uskb = NULL;
794 u8 *pdata;
795
796 uskb = dev_alloc_skb(skb->len + 128);
797 if (likely(uskb)) {
798 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
799 sizeof(rx_status));
800 pdata = (u8 *)skb_put(uskb, skb->len);
801 memcpy(pdata, skb->data, skb->len);
802 dev_kfree_skb_any(skb);
803
804 ieee80211_rx_irqsafe(hw, uskb);
805 } else {
806 ieee80211_rx_irqsafe(hw, skb);
807 }
808 }
809 }
810
811 /*hsisr interrupt handler*/
812 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
813 {
814 struct rtl_priv *rtlpriv = rtl_priv(hw);
815 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
816
817 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
818 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
819 rtlpci->sys_irq_mask);
820
821
822 }
823 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
824 {
825 struct rtl_priv *rtlpriv = rtl_priv(hw);
826 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
827 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
828
829 struct ieee80211_rx_status rx_status = { 0 };
830 unsigned int count = rtlpci->rxringcount;
831 bool unicast = false;
832 u8 hw_queue = 0;
833 unsigned int rx_remained_cnt;
834 u8 own;
835 u8 tmp_one;
836
837 struct rtl_stats status = {
838 .signal = 0,
839 .noise = -98,
840 .rate = 0,
841 };
842
843 /*RX NORMAL PKT */
844 while (count--) {
845 struct ieee80211_hdr *hdr;
846 u16 fc;
847 u16 len;
848 /*rx buffer descriptor */
849 struct rtl_rx_buffer_desc *buffer_desc = NULL;
850 /*if use new trx flow, it means wifi info */
851 struct rtl_rx_desc *pdesc = NULL;
852 /*rx pkt */
853 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
854 rtlpci->rx_ring[rxring_idx].idx];
855
856 if (rtlpriv->use_new_trx_flow) {
857 rx_remained_cnt =
858 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
859 hw_queue);
860 if (rx_remained_cnt < 1)
861 return;
862
863 } else { /* rx descriptor */
864 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
865 rtlpci->rx_ring[rxring_idx].idx];
866
867 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
868 false,
869 HW_DESC_OWN);
870 if (own) /* wait data to be filled by hardware */
871 return;
872 }
873
874 /* Get here means: data is filled already*/
875 /* AAAAAAttention !!!
876 * We can NOT access 'skb' before 'pci_unmap_single' */
877 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *) skb->cb),
878 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
879
880 if (rtlpriv->use_new_trx_flow) {
881 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
882 rtlpci->rx_ring[rxring_idx].idx];
883 /*means rx wifi info*/
884 pdesc = (struct rtl_rx_desc *)skb->data;
885 }
886
887 rtlpriv->cfg->ops->query_rx_desc(hw, &status,
888 &rx_status, (u8 *) pdesc, skb);
889
890 if (rtlpriv->use_new_trx_flow)
891 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
892 (u8 *)buffer_desc,
893 hw_queue);
894
895
896 len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false,
897 HW_DESC_RXPKT_LEN);
898
899 if (skb->end - skb->tail > len) {
900 skb_put(skb, len);
901 if (rtlpriv->use_new_trx_flow)
902 skb_reserve(skb, status.rx_drvinfo_size +
903 status.rx_bufshift + 24);
904 else
905 skb_reserve(skb, status.rx_drvinfo_size +
906 status.rx_bufshift);
907
908 } else {
909 printk("skb->end - skb->tail = %d, len is %d\n",
910 skb->end - skb->tail, len);
911 break;
912 }
913
914 rtlpriv->cfg->ops->rx_command_packet_handler(hw, status, skb);
915
916 /*
917 *NOTICE This can not be use for mac80211,
918 *this is done in mac80211 code,
919 *if you done here sec DHCP will fail
920 *skb_trim(skb, skb->len - 4);
921 */
922
923 hdr = rtl_get_hdr(skb);
924 fc = rtl_get_fc(skb);
925
926 if (!status.b_crc && !status.b_hwerror) {
927 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
928 sizeof(rx_status));
929
930 if (is_broadcast_ether_addr(hdr->addr1)) {
931 ;/*TODO*/
932 } else if (is_multicast_ether_addr(hdr->addr1)) {
933 ;/*TODO*/
934 } else {
935 unicast = true;
936 rtlpriv->stats.rxbytesunicast += skb->len;
937 }
938
939 rtl_is_special_data(hw, skb, false);
940
941 if (ieee80211_is_data(fc)) {
942 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
943
944 if (unicast)
945 rtlpriv->link_info.num_rx_inperiod++;
946 }
947
948 /* static bcn for roaming */
949 rtl_beacon_statistic(hw, skb);
950 rtl_p2p_info(hw, (void*)skb->data, skb->len);
951 /* for sw lps */
952 rtl_swlps_beacon(hw, (void*)skb->data, skb->len);
953 rtl_recognize_peer(hw, (void*)skb->data, skb->len);
954 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
955 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)&&
956 (ieee80211_is_beacon(fc) ||
957 ieee80211_is_probe_resp(fc))) {
958 dev_kfree_skb_any(skb);
959 } else {
960 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
961 }
962 } else {
963 dev_kfree_skb_any(skb);
964 }
965 if (rtlpriv->use_new_trx_flow) {
966 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
967 rtlpci->rx_ring[hw_queue].next_rx_rp %=
968 RTL_PCI_MAX_RX_COUNT;
969
970
971 rx_remained_cnt--;
972 if (1/*rx_remained_cnt == 0*/) {
973 rtl_write_word(rtlpriv, 0x3B4,
974 rtlpci->rx_ring[hw_queue].next_rx_rp);
975 }
976 }
977 if (((rtlpriv->link_info.num_rx_inperiod +
978 rtlpriv->link_info.num_tx_inperiod) > 8) ||
979 (rtlpriv->link_info.num_rx_inperiod > 2)) {
980 rtl_lps_leave(hw);
981 }
982
983 if (rtlpriv->use_new_trx_flow) {
984 _rtl_pci_init_one_rxdesc(hw, (u8 *)buffer_desc,
985 rxring_idx,
986 rtlpci->rx_ring[rxring_idx].idx);
987 } else {
988 _rtl_pci_init_one_rxdesc(hw, (u8 *)pdesc, rxring_idx,
989 rtlpci->rx_ring[rxring_idx].idx);
990
991 if (rtlpci->rx_ring[rxring_idx].idx ==
992 rtlpci->rxringcount - 1)
993 rtlpriv->cfg->ops->set_desc(hw, (u8 *) pdesc,
994 false,
995 HW_DESC_RXERO,
996 (u8 *) & tmp_one);
997 }
998 rtlpci->rx_ring[rxring_idx].idx =
999 (rtlpci->rx_ring[rxring_idx].idx + 1) %
1000 rtlpci->rxringcount;
1001 }
1002 }
1003
1004 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
1005 {
1006 struct ieee80211_hw *hw = dev_id;
1007 struct rtl_priv *rtlpriv = rtl_priv(hw);
1008 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1009 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1010 unsigned long flags;
1011 u32 inta = 0;
1012 u32 intb = 0;
1013
1014
1015
1016 if (rtlpci->irq_enabled == 0)
1017 return IRQ_HANDLED;
1018
1019 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock,flags);
1020
1021
1022 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMR], 0x0);
1023
1024
1025 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMRE], 0x0);
1026
1027
1028 /*read ISR: 4/8bytes */
1029 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
1030
1031
1032 /*Shared IRQ or HW disappared */
1033 if (!inta || inta == 0xffff)
1034 goto done;
1035 /*<1> beacon related */
1036 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
1037 RT_TRACE(COMP_INTR, DBG_TRACE, ("beacon ok interrupt!\n"));
1038 }
1039
1040 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
1041 RT_TRACE(COMP_INTR, DBG_TRACE, ("beacon err interrupt!\n"));
1042 }
1043
1044 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
1045 RT_TRACE(COMP_INTR, DBG_TRACE, ("beacon interrupt!\n"));
1046 }
1047
1048 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
1049 RT_TRACE(COMP_INTR, DBG_TRACE,
1050 ("prepare beacon for interrupt!\n"));
1051 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
1052 }
1053
1054
1055 /*<2> tx related */
1056 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
1057 RT_TRACE(COMP_ERR, DBG_TRACE, ("IMR_TXFOVW!\n"));
1058
1059 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
1060 RT_TRACE(COMP_INTR, DBG_TRACE, ("Manage ok interrupt!\n"));
1061 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
1062 }
1063
1064 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
1065 RT_TRACE(COMP_INTR, DBG_TRACE, ("HIGH_QUEUE ok interrupt!\n"));
1066 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
1067 }
1068
1069 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
1070 rtlpriv->link_info.num_tx_inperiod++;
1071
1072 RT_TRACE(COMP_INTR, DBG_TRACE, ("BK Tx OK interrupt!\n"));
1073 _rtl_pci_tx_isr(hw, BK_QUEUE);
1074 }
1075
1076 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
1077 rtlpriv->link_info.num_tx_inperiod++;
1078
1079 RT_TRACE(COMP_INTR, DBG_TRACE, ("BE TX OK interrupt!\n"));
1080 _rtl_pci_tx_isr(hw, BE_QUEUE);
1081 }
1082
1083 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
1084 rtlpriv->link_info.num_tx_inperiod++;
1085
1086 RT_TRACE(COMP_INTR, DBG_TRACE, ("VI TX OK interrupt!\n"));
1087 _rtl_pci_tx_isr(hw, VI_QUEUE);
1088 }
1089
1090 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1091 rtlpriv->link_info.num_tx_inperiod++;
1092
1093 RT_TRACE(COMP_INTR, DBG_TRACE, ("Vo TX OK interrupt!\n"));
1094 _rtl_pci_tx_isr(hw, VO_QUEUE);
1095 }
1096
1097 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1098 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1099 rtlpriv->link_info.num_tx_inperiod++;
1100
1101 RT_TRACE(COMP_INTR, DBG_TRACE,
1102 ("CMD TX OK interrupt!\n"));
1103 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1104 }
1105 }
1106
1107 /*<3> rx related */
1108 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1109 RT_TRACE(COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
1110
1111 _rtl_pci_rx_interrupt(hw);
1112
1113 }
1114
1115 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1116 RT_TRACE(COMP_ERR, DBG_WARNING,
1117 ("rx descriptor unavailable!\n"));
1118 rtl_write_byte(rtlpriv, 0xb4, BIT(1) );
1119 _rtl_pci_rx_interrupt(hw);
1120 }
1121
1122 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1123 RT_TRACE(COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
1124 _rtl_pci_rx_interrupt(hw);
1125 }
1126
1127 /*<4> fw related*/
1128 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1129 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1130 RT_TRACE(COMP_INTR, DBG_TRACE,
1131 ("firmware interrupt!\n"));
1132 queue_delayed_work(rtlpriv->works.rtl_wq,
1133 &rtlpriv->works.fwevt_wq, 0);
1134 }
1135 }
1136
1137 /*<5> hsisr related*/
1138 /* Only 8188EE & 8723BE Supported.
1139 * If Other ICs Come in, System will corrupt,
1140 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1141 * are not initialized*/
1142 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1143 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1144 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1145 RT_TRACE(COMP_INTR, DBG_TRACE,
1146 ("hsisr interrupt!\n"));
1147 _rtl_pci_hs_interrupt(hw);
1148 }
1149 }
1150
1151
1152 if(rtlpriv->rtlhal.b_earlymode_enable)
1153 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1154
1155 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMR],
1156 rtlpci->irq_mask[0]);
1157 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMRE],
1158 rtlpci->irq_mask[1]);
1159 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1160
1161 return IRQ_HANDLED;
1162
1163 done:
1164 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1165 return IRQ_HANDLED;
1166 }
1167
1168 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1169 {
1170 _rtl_pci_tx_chk_waitq(hw);
1171 }
1172
1173 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1174 {
1175 struct rtl_priv *rtlpriv = rtl_priv(hw);
1176 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1177 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1178 struct rtl8192_tx_ring *ring = NULL;
1179 struct ieee80211_hdr *hdr = NULL;
1180 struct ieee80211_tx_info *info = NULL;
1181 struct sk_buff *pskb = NULL;
1182 struct rtl_tx_desc *pdesc = NULL;
1183 struct rtl_tcb_desc tcb_desc;
1184 /*This is for new trx flow*/
1185 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1186 u8 temp_one = 1;
1187
1188 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1189 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1190 pskb = __skb_dequeue(&ring->queue);
1191 if (pskb)
1192 kfree_skb(pskb);
1193
1194 /*NB: the beacon data buffer must be 32-bit aligned. */
1195 pskb = ieee80211_beacon_get(hw, mac->vif);
1196 if (pskb == NULL)
1197 return;
1198 hdr = rtl_get_hdr(pskb);
1199 info = IEEE80211_SKB_CB(pskb);
1200 pdesc = &ring->desc[0];
1201 if (rtlpriv->use_new_trx_flow)
1202 pbuffer_desc = &ring->buffer_desc[0];
1203
1204 /*<delete in kernel start>*/
1205 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1206 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1207 (u8 *)pbuffer_desc, info, pskb,
1208 BEACON_QUEUE, &tcb_desc);
1209 #else
1210 /*<delete in kernel end>*/
1211 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1212 (u8 *)pbuffer_desc, info, NULL, pskb,
1213 BEACON_QUEUE, &tcb_desc);
1214 /*<delete in kernel start>*/
1215 #endif
1216 /*<delete in kernel end>*/
1217
1218 __skb_queue_tail(&ring->queue, pskb);
1219
1220 rtlpriv->cfg->ops->set_desc(hw, (u8 *) pdesc, true, HW_DESC_OWN,
1221 (u8 *) & temp_one);
1222
1223 return;
1224 }
1225
1226 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1227 {
1228 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1229 struct rtl_priv *rtlpriv = rtl_priv(hw);
1230 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1231 u8 i;
1232 u16 desc_num;
1233
1234 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1235 desc_num = TX_DESC_NUM_92E;
1236 else
1237 desc_num = RT_TXDESC_NUM;
1238
1239 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1240 rtlpci->txringcount[i] = desc_num;
1241 }
1242 /*
1243 *we just alloc 2 desc for beacon queue,
1244 *because we just need first desc in hw beacon.
1245 */
1246 rtlpci->txringcount[BEACON_QUEUE] = 2;
1247
1248 /*
1249 *BE queue need more descriptor for performance
1250 *consideration or, No more tx desc will happen,
1251 *and may cause mac80211 mem leakage.
1252 */
1253 if (rtl_priv(hw)->use_new_trx_flow == false)
1254 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1255
1256 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1257 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1258 }
1259
1260 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1261 struct pci_dev *pdev)
1262 {
1263 struct rtl_priv *rtlpriv = rtl_priv(hw);
1264 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1265 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1266 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1267
1268 rtlpriv->rtlhal.up_first_time = true;
1269 rtlpriv->rtlhal.being_init_adapter = false;
1270
1271 rtlhal->hw = hw;
1272 rtlpci->pdev = pdev;
1273
1274 /*Tx/Rx related var */
1275 _rtl_pci_init_trx_var(hw);
1276
1277 /*IBSS*/ mac->beacon_interval = 100;
1278
1279 /*AMPDU*/
1280 mac->min_space_cfg = 0;
1281 mac->max_mss_density = 0;
1282 /*set sane AMPDU defaults */
1283 mac->current_ampdu_density = 7;
1284 mac->current_ampdu_factor = 3;
1285
1286 /*QOS*/
1287 rtlpci->acm_method = eAcmWay2_SW;
1288
1289 /*task */
1290 tasklet_init(&rtlpriv->works.irq_tasklet,
1291 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1292 (unsigned long)hw);
1293 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1294 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1295 (unsigned long)hw);
1296 }
1297
1298 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1299 unsigned int prio, unsigned int entries)
1300 {
1301 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1302 struct rtl_priv *rtlpriv = rtl_priv(hw);
1303 struct rtl_tx_buffer_desc *buffer_desc;
1304 struct rtl_tx_desc *desc;
1305 dma_addr_t buffer_desc_dma, desc_dma;
1306 u32 nextdescaddress;
1307 int i;
1308
1309 /* alloc tx buffer desc for new trx flow*/
1310 if (rtlpriv->use_new_trx_flow) {
1311 buffer_desc = pci_alloc_consistent(rtlpci->pdev,
1312 sizeof(*buffer_desc) * entries,
1313 &buffer_desc_dma);
1314
1315 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1316 RT_TRACE(COMP_ERR, DBG_EMERG,
1317 ("Cannot allocate TX ring (prio = %d)\n",
1318 prio));
1319 return -ENOMEM;
1320 }
1321
1322 memset(buffer_desc, 0, sizeof(*buffer_desc) * entries);
1323 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1324 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1325
1326 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1327 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1328 rtlpci->tx_ring[prio].avl_desc = entries;
1329
1330 }
1331
1332 /* alloc dma for this ring */
1333 desc = pci_alloc_consistent(rtlpci->pdev,
1334 sizeof(*desc) * entries, &desc_dma);
1335
1336 if (!desc || (unsigned long)desc & 0xFF) {
1337 RT_TRACE(COMP_ERR, DBG_EMERG,
1338 ("Cannot allocate TX ring (prio = %d)\n", prio));
1339 return -ENOMEM;
1340 }
1341
1342 memset(desc, 0, sizeof(*desc) * entries);
1343 rtlpci->tx_ring[prio].desc = desc;
1344 rtlpci->tx_ring[prio].dma = desc_dma;
1345
1346 rtlpci->tx_ring[prio].idx = 0;
1347 rtlpci->tx_ring[prio].entries = entries;
1348 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1349 RT_TRACE(COMP_INIT, DBG_LOUD,
1350 ("queue:%d, ring_addr:%p\n", prio, desc));
1351
1352 /* init every desc in this ring */
1353 if (rtlpriv->use_new_trx_flow == false) {
1354 for (i = 0; i < entries; i++) {
1355 nextdescaddress = cpu_to_le32((u32) desc_dma +
1356 ((i + 1) % entries) *
1357 sizeof(*desc));
1358
1359 rtlpriv->cfg->ops->set_desc(hw, (u8 *) & (desc[i]),
1360 true,
1361 HW_DESC_TX_NEXTDESC_ADDR,
1362 (u8 *) & nextdescaddress);
1363 }
1364 }
1365 return 0;
1366 }
1367
1368 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1369 {
1370 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1371 struct rtl_priv *rtlpriv = rtl_priv(hw);
1372
1373 int i;
1374
1375 if (rtlpriv->use_new_trx_flow) {
1376 struct rtl_rx_buffer_desc *entry = NULL;
1377 /* alloc dma for this ring */
1378 rtlpci->rx_ring[rxring_idx].buffer_desc =
1379 pci_alloc_consistent(rtlpci->pdev,
1380 sizeof(*rtlpci->rx_ring[rxring_idx].
1381 buffer_desc) *
1382 rtlpci->rxringcount,
1383 &rtlpci->rx_ring[rxring_idx].dma);
1384 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1385 (unsigned long)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1386 RT_TRACE(COMP_ERR, DBG_EMERG, ("Cannot allocate RX ring\n"));
1387 return -ENOMEM;
1388 }
1389
1390 memset(rtlpci->rx_ring[rxring_idx].buffer_desc, 0,
1391 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1392 rtlpci->rxringcount);
1393
1394 /* init every desc in this ring */
1395 rtlpci->rx_ring[rxring_idx].idx = 0;
1396 for (i = 0; i < rtlpci->rxringcount; i++) {
1397 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1398 if (!_rtl_pci_init_one_rxdesc(hw, (u8 *)entry,
1399 rxring_idx, i))
1400 return -ENOMEM;
1401 }
1402 } else {
1403 struct rtl_rx_desc *entry = NULL;
1404 u8 tmp_one = 1;
1405 /* alloc dma for this ring */
1406 rtlpci->rx_ring[rxring_idx].desc =
1407 pci_alloc_consistent(rtlpci->pdev,
1408 sizeof(*rtlpci->rx_ring[rxring_idx].
1409 desc) * rtlpci->rxringcount,
1410 &rtlpci->rx_ring[rxring_idx].dma);
1411 if (!rtlpci->rx_ring[rxring_idx].desc ||
1412 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1413 RT_TRACE(COMP_ERR, DBG_EMERG,
1414 ("Cannot allocate RX ring\n"));
1415 return -ENOMEM;
1416 }
1417
1418 memset(rtlpci->rx_ring[rxring_idx].desc, 0,
1419 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1420 rtlpci->rxringcount);
1421
1422 /* init every desc in this ring */
1423 rtlpci->rx_ring[rxring_idx].idx = 0;
1424 for (i = 0; i < rtlpci->rxringcount; i++) {
1425 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1426 if (!_rtl_pci_init_one_rxdesc(hw, (u8 *)entry,
1427 rxring_idx, i))
1428 return -ENOMEM;
1429 }
1430 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry, false,
1431 HW_DESC_RXERO, (u8 *) & tmp_one);
1432 }
1433 return 0;
1434 }
1435
1436 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1437 unsigned int prio)
1438 {
1439 struct rtl_priv *rtlpriv = rtl_priv(hw);
1440 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1441 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1442
1443 /* free every desc in this ring */
1444 while (skb_queue_len(&ring->queue)) {
1445 u8 *entry;
1446 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1447 if (rtlpriv->use_new_trx_flow)
1448 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1449 else
1450 entry = (u8 *)(&ring->desc[ring->idx]);
1451
1452 pci_unmap_single(rtlpci->pdev,
1453 le32_to_cpu(rtlpriv->cfg->ops->get_desc(
1454 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR)),
1455 skb->len, PCI_DMA_TODEVICE);
1456 kfree_skb(skb);
1457 ring->idx = (ring->idx + 1) % ring->entries;
1458 }
1459
1460 /* free dma of this ring */
1461 pci_free_consistent(rtlpci->pdev,
1462 sizeof(*ring->desc) * ring->entries,
1463 ring->desc, ring->dma);
1464 ring->desc = NULL;
1465 if (rtlpriv->use_new_trx_flow) {
1466 pci_free_consistent(rtlpci->pdev,
1467 sizeof(*ring->buffer_desc) * ring->entries,
1468 ring->buffer_desc, ring->buffer_desc_dma);
1469 ring->buffer_desc = NULL;
1470 }
1471 }
1472
1473 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1474 {
1475 struct rtl_priv *rtlpriv = rtl_priv(hw);
1476 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1477 int i;
1478
1479 /* free every desc in this ring */
1480 for (i = 0; i < rtlpci->rxringcount; i++) {
1481 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1482 if (!skb)
1483 continue;
1484
1485 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *) skb->cb),
1486 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1487 kfree_skb(skb);
1488 }
1489
1490 /* free dma of this ring */
1491 if (rtlpriv->use_new_trx_flow) {
1492 pci_free_consistent(rtlpci->pdev,
1493 sizeof(*rtlpci->rx_ring[rxring_idx].
1494 buffer_desc) * rtlpci->rxringcount,
1495 rtlpci->rx_ring[rxring_idx].buffer_desc,
1496 rtlpci->rx_ring[rxring_idx].dma);
1497 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1498 } else {
1499 pci_free_consistent(rtlpci->pdev,
1500 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1501 rtlpci->rxringcount,
1502 rtlpci->rx_ring[rxring_idx].desc,
1503 rtlpci->rx_ring[rxring_idx].dma);
1504 rtlpci->rx_ring[rxring_idx].desc = NULL;
1505 }
1506 }
1507
1508 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1509 {
1510 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1511 int ret;
1512 int i, rxring_idx;
1513
1514 /* rxring_idx 0:RX_MPDU_QUEUE
1515 * rxring_idx 1:RX_CMD_QUEUE */
1516 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1517 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1518 if (ret)
1519 return ret;
1520 }
1521
1522 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1523 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1524 if (ret)
1525 goto err_free_rings;
1526 }
1527
1528 return 0;
1529
1530 err_free_rings:
1531 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1532 _rtl_pci_free_rx_ring(hw, rxring_idx);
1533
1534 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1535 if (rtlpci->tx_ring[i].desc ||
1536 rtlpci->tx_ring[i].buffer_desc)
1537 _rtl_pci_free_tx_ring(hw, i);
1538
1539 return 1;
1540 }
1541
1542 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1543 {
1544 u32 i, rxring_idx;
1545
1546 /*free rx rings */
1547 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1548 _rtl_pci_free_rx_ring(hw, rxring_idx);
1549
1550 /*free tx rings */
1551 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1552 _rtl_pci_free_tx_ring(hw, i);
1553
1554 return 0;
1555 }
1556
1557 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1558 {
1559 struct rtl_priv *rtlpriv = rtl_priv(hw);
1560 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1561 int i, rxring_idx;
1562 unsigned long flags;
1563 u8 tmp_one = 1;
1564 /* rxring_idx 0:RX_MPDU_QUEUE */
1565 /* rxring_idx 1:RX_CMD_QUEUE */
1566 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1567 /* force the rx_ring[RX_MPDU_QUEUE/
1568 * RX_CMD_QUEUE].idx to the first one */
1569 /*new trx flow, do nothing*/
1570 if ((rtlpriv->use_new_trx_flow == false) &&
1571 rtlpci->rx_ring[rxring_idx].desc) {
1572 struct rtl_rx_desc *entry = NULL;
1573
1574 for (i = 0; i < rtlpci->rxringcount; i++) {
1575 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1576 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry,
1577 false,
1578 HW_DESC_RXOWN,
1579 (u8 *) & tmp_one);
1580 }
1581 }
1582 rtlpci->rx_ring[rxring_idx].idx = 0; }
1583
1584 /* after reset, release previous pending packet,
1585 * and force the tx idx to the first one */
1586 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1587 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1588 if (rtlpci->tx_ring[i].desc ||
1589 rtlpci->tx_ring[i].buffer_desc) {
1590 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1591
1592 while (skb_queue_len(&ring->queue)) {
1593 u8 *entry;
1594 struct sk_buff *skb =
1595 __skb_dequeue(&ring->queue);
1596 if (rtlpriv->use_new_trx_flow)
1597 entry = (u8 *)(&ring->buffer_desc
1598 [ring->idx]);
1599 else
1600 entry = (u8 *)(&ring->desc[ring->idx]);
1601
1602 pci_unmap_single(rtlpci->pdev,
1603 le32_to_cpu(rtlpriv->cfg->ops->get_desc(
1604 (u8 *)entry, true,
1605 HW_DESC_TXBUFF_ADDR)),
1606 skb->len, PCI_DMA_TODEVICE);
1607 kfree_skb(skb);
1608 ring->idx = (ring->idx + 1) % ring->entries;
1609 }
1610 ring->idx = 0;
1611 }
1612 }
1613
1614 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1615
1616 return 0;
1617 }
1618
1619 /*<delete in kernel start>*/
1620 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1621 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1622 struct sk_buff *skb)
1623 #else
1624 /*<delete in kernel end>*/
1625 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1626 struct ieee80211_sta *sta,
1627 struct sk_buff *skb)
1628 /*<delete in kernel start>*/
1629 #endif
1630 /*<delete in kernel end>*/
1631 {
1632 struct rtl_priv *rtlpriv = rtl_priv(hw);
1633 /*<delete in kernel start>*/
1634 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1635 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1636 struct ieee80211_sta *sta = info->control.sta;
1637 #endif
1638 /*<delete in kernel end>*/
1639 struct rtl_sta_info *sta_entry = NULL;
1640 u8 tid = rtl_get_tid(skb);
1641 u16 fc = rtl_get_fc(skb);
1642
1643 if(!sta)
1644 return false;
1645 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1646
1647 if (!rtlpriv->rtlhal.b_earlymode_enable)
1648 return false;
1649 if (ieee80211_is_nullfunc(fc))
1650 return false;
1651 if (ieee80211_is_qos_nullfunc(fc))
1652 return false;
1653 if (ieee80211_is_pspoll(fc)) {
1654 return false;
1655 }
1656
1657 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1658 return false;
1659 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1660 return false;
1661 if (tid > 7)
1662 return false;
1663 /* maybe every tid should be checked */
1664 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1665 return false;
1666
1667 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1668 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1669 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1670
1671 return true;
1672 }
1673
1674 /*<delete in kernel start>*/
1675 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1676 int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
1677 struct rtl_tcb_desc *ptcb_desc)
1678 #else
1679 /*<delete in kernel end>*/
1680 static int rtl_pci_tx(struct ieee80211_hw *hw,
1681 struct ieee80211_sta *sta,
1682 struct sk_buff *skb,
1683 struct rtl_tcb_desc *ptcb_desc)
1684 /*<delete in kernel start>*/
1685 #endif
1686 /*<delete in kernel end>*/
1687 {
1688 struct rtl_priv *rtlpriv = rtl_priv(hw);
1689 struct rtl_sta_info *sta_entry = NULL;
1690 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1691 /*<delete in kernel start>*/
1692 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1693 struct ieee80211_sta *sta = info->control.sta;
1694 #endif
1695 /*<delete in kernel end>*/
1696 struct rtl8192_tx_ring *ring;
1697 struct rtl_tx_desc *pdesc;
1698 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1699 u16 idx;
1700 u8 own;
1701 u8 temp_one = 1;
1702 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1703 unsigned long flags;
1704 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1705 u16 fc = rtl_get_fc(skb);
1706 u8 *pda_addr = hdr->addr1;
1707 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1708 /*ssn */
1709 u8 tid = 0;
1710 u16 seq_number = 0;
1711
1712
1713 if (ieee80211_is_mgmt(fc))
1714 rtl_tx_mgmt_proc(hw, skb);
1715
1716 if (rtlpriv->psc.sw_ps_enabled) {
1717 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1718 !ieee80211_has_pm(fc))
1719 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1720 }
1721
1722 rtl_action_proc(hw, skb, true);
1723
1724 if (is_multicast_ether_addr(pda_addr))
1725 rtlpriv->stats.txbytesmulticast += skb->len;
1726 else if (is_broadcast_ether_addr(pda_addr))
1727 rtlpriv->stats.txbytesbroadcast += skb->len;
1728 else
1729 rtlpriv->stats.txbytesunicast += skb->len;
1730
1731 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1732 ring = &rtlpci->tx_ring[hw_queue];
1733 if (hw_queue != BEACON_QUEUE) {
1734 if (rtlpriv->use_new_trx_flow)
1735 idx = ring->cur_tx_wp;
1736 else
1737 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1738 ring->entries;
1739 } else {
1740 idx = 0;
1741 }
1742
1743 pdesc = &ring->desc[idx];
1744
1745 if (rtlpriv->use_new_trx_flow) {
1746 ptx_bd_desc = &ring->buffer_desc[idx];
1747 } else {
1748 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1749 true, HW_DESC_OWN);
1750
1751 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1752 RT_TRACE(COMP_ERR, DBG_WARNING,
1753 ("No more TX desc@%d, ring->idx = %d,"
1754 "idx = %d, skb_queue_len = 0x%d\n",
1755 hw_queue, ring->idx, idx,
1756 skb_queue_len(&ring->queue)));
1757
1758 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1759 flags);
1760 return skb->len;
1761 }
1762 }
1763
1764 if (ieee80211_is_data_qos(fc)) {
1765 tid = rtl_get_tid(skb);
1766 if (sta) {
1767 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1768 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1769 IEEE80211_SCTL_SEQ) >> 4;
1770 seq_number += 1;
1771
1772 if (!ieee80211_has_morefrags(hdr->frame_control))
1773 sta_entry->tids[tid].seq_number = seq_number;
1774 }
1775 }
1776
1777 if (ieee80211_is_data(fc))
1778 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1779
1780 /*<delete in kernel start>*/
1781 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1782 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1783 (u8 *)ptx_bd_desc, info, skb,
1784 hw_queue, ptcb_desc);
1785 #else
1786 /*<delete in kernel end>*/
1787 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1788 (u8 *)ptx_bd_desc, info, sta, skb,
1789 hw_queue, ptcb_desc);
1790 /*<delete in kernel start>*/
1791 #endif
1792 /*<delete in kernel end>*/
1793
1794 __skb_queue_tail(&ring->queue, skb);
1795 if (rtlpriv->use_new_trx_flow) {
1796 rtlpriv->cfg->ops->set_desc(hw, (u8 *) pdesc, true,
1797 HW_DESC_OWN, (u8 *) & hw_queue);
1798 } else {
1799 rtlpriv->cfg->ops->set_desc(hw, (u8 *) pdesc, true,
1800 HW_DESC_OWN, (u8 *) & temp_one);
1801 }
1802
1803 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1804 hw_queue != BEACON_QUEUE) {
1805
1806 RT_TRACE(COMP_ERR, DBG_LOUD,
1807 ("less desc left, stop skb_queue@%d, "
1808 "ring->idx = %d,"
1809 "idx = %d, skb_queue_len = 0x%d\n",
1810 hw_queue, ring->idx, idx,
1811 skb_queue_len(&ring->queue)));
1812
1813 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1814 }
1815
1816 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1817
1818 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1819
1820 return 0;
1821 }
1822 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
1823 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1824 #else
1825 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1826 #endif
1827 {
1828 struct rtl_priv *rtlpriv = rtl_priv(hw);
1829 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1830 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1831 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1832 u16 i = 0;
1833 int queue_id;
1834 struct rtl8192_tx_ring *ring;
1835
1836 if (mac->skip_scan)
1837 return;
1838
1839 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1840 u32 queue_len;
1841 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
1842 if (((queues >> queue_id) & 0x1) == 0) {
1843 queue_id--;
1844 continue;
1845 }
1846 #endif
1847 ring = &pcipriv->dev.tx_ring[queue_id];
1848 queue_len = skb_queue_len(&ring->queue);
1849 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1850 queue_id == TXCMD_QUEUE) {
1851 queue_id--;
1852 continue;
1853 } else {
1854 msleep(5);
1855 i++;
1856 }
1857
1858 /* we just wait 1s for all queues */
1859 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1860 is_hal_stop(rtlhal) || i >= 200)
1861 return;
1862 }
1863 }
1864
1865 void rtl_pci_deinit(struct ieee80211_hw *hw)
1866 {
1867 struct rtl_priv *rtlpriv = rtl_priv(hw);
1868 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1869
1870 _rtl_pci_deinit_trx_ring(hw);
1871
1872 synchronize_irq(rtlpci->pdev->irq);
1873 tasklet_kill(&rtlpriv->works.irq_tasklet);
1874
1875 flush_workqueue(rtlpriv->works.rtl_wq);
1876 destroy_workqueue(rtlpriv->works.rtl_wq);
1877
1878 }
1879
1880 int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1881 {
1882 struct rtl_priv *rtlpriv = rtl_priv(hw);
1883 int err;
1884
1885 _rtl_pci_init_struct(hw, pdev);
1886
1887 err = _rtl_pci_init_trx_ring(hw);
1888 if (err) {
1889 RT_TRACE(COMP_ERR, DBG_EMERG,
1890 ("tx ring initialization failed"));
1891 return err;
1892 }
1893
1894 return 1;
1895 }
1896
1897 int rtl_pci_start(struct ieee80211_hw *hw)
1898 {
1899 struct rtl_priv *rtlpriv = rtl_priv(hw);
1900 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1901 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1902
1903 int err = 0;
1904 RT_TRACE(COMP_INIT, DBG_DMESG, (" rtl_pci_start \n"));
1905 rtl_pci_reset_trx_ring(hw);
1906
1907 rtlpriv->rtlhal.driver_is_goingto_unload = false;
1908 err = rtlpriv->cfg->ops->hw_init(hw);
1909 if (err) {
1910 RT_TRACE(COMP_INIT, DBG_DMESG,
1911 ("Failed to config hardware err %x!\n",err));
1912 return err;
1913 }
1914
1915 rtlpriv->cfg->ops->enable_interrupt(hw);
1916 RT_TRACE(COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1917
1918 rtl_init_rx_config(hw);
1919
1920 /*should after adapter start and interrupt enable. */
1921 set_hal_start(rtlhal);
1922
1923 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1924
1925 rtlpriv->rtlhal.up_first_time = false;
1926
1927 RT_TRACE(COMP_INIT, DBG_DMESG, ("rtl_pci_start OK\n"));
1928 return 0;
1929 }
1930
1931 void rtl_pci_stop(struct ieee80211_hw *hw)
1932 {
1933 struct rtl_priv *rtlpriv = rtl_priv(hw);
1934 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1935 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1936 u8 RFInProgressTimeOut = 0;
1937
1938 /*
1939 *should before disable interrrupt&adapter
1940 *and will do it immediately.
1941 */
1942 set_hal_stop(rtlhal);
1943
1944 rtlpriv->cfg->ops->disable_interrupt(hw);
1945
1946 spin_lock(&rtlpriv->locks.rf_ps_lock);
1947 while (ppsc->rfchange_inprogress) {
1948 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1949 if (RFInProgressTimeOut > 100) {
1950 spin_lock(&rtlpriv->locks.rf_ps_lock);
1951 break;
1952 }
1953 mdelay(1);
1954 RFInProgressTimeOut++;
1955 spin_lock(&rtlpriv->locks.rf_ps_lock);
1956 }
1957 ppsc->rfchange_inprogress = true;
1958 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1959
1960 rtlpriv->rtlhal.driver_is_goingto_unload = true;
1961 rtlpriv->cfg->ops->hw_disable(hw);
1962 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1963
1964 spin_lock(&rtlpriv->locks.rf_ps_lock);
1965 ppsc->rfchange_inprogress = false;
1966 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1967
1968 rtl_pci_enable_aspm(hw);
1969 }
1970
1971 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1972 struct ieee80211_hw *hw)
1973 {
1974 struct rtl_priv *rtlpriv = rtl_priv(hw);
1975 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1976 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1977 struct pci_dev *bridge_pdev = pdev->bus->self;
1978 u16 venderid;
1979 u16 deviceid;
1980 u8 revisionid;
1981 u16 irqline;
1982 u8 tmp;
1983
1984 venderid = pdev->vendor;
1985 deviceid = pdev->device;
1986 pci_read_config_byte(pdev, 0x8, &revisionid);
1987 pci_read_config_word(pdev, 0x3C, &irqline);
1988
1989 if (deviceid == RTL_PCI_8192_DID ||
1990 deviceid == RTL_PCI_0044_DID ||
1991 deviceid == RTL_PCI_0047_DID ||
1992 deviceid == RTL_PCI_8192SE_DID ||
1993 deviceid == RTL_PCI_8174_DID ||
1994 deviceid == RTL_PCI_8173_DID ||
1995 deviceid == RTL_PCI_8172_DID ||
1996 deviceid == RTL_PCI_8171_DID) {
1997 switch (revisionid) {
1998 case RTL_PCI_REVISION_ID_8192PCIE:
1999 RT_TRACE(COMP_INIT, DBG_DMESG,
2000 ("8192E is found but not supported now-"
2001 "vid/did=%x/%x\n", venderid, deviceid));
2002 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
2003 return false;
2004 break;
2005 case RTL_PCI_REVISION_ID_8192SE:
2006 RT_TRACE(COMP_INIT, DBG_DMESG,
2007 ("8192SE is found - "
2008 "vid/did=%x/%x\n", venderid, deviceid));
2009 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
2010 break;
2011 default:
2012 RT_TRACE(COMP_ERR, DBG_WARNING,
2013 ("Err: Unknown device - "
2014 "vid/did=%x/%x\n", venderid, deviceid));
2015 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
2016 break;
2017
2018 }
2019 }else if(deviceid == RTL_PCI_8723AE_DID) {
2020 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
2021 RT_TRACE(COMP_INIT, DBG_DMESG,
2022 ("8723AE PCI-E is found - "
2023 "vid/did=%x/%x\n", venderid, deviceid));
2024 } else if (deviceid == RTL_PCI_8192CET_DID ||
2025 deviceid == RTL_PCI_8192CE_DID ||
2026 deviceid == RTL_PCI_8191CE_DID ||
2027 deviceid == RTL_PCI_8188CE_DID) {
2028 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
2029 RT_TRACE(COMP_INIT, DBG_DMESG,
2030 ("8192C PCI-E is found - "
2031 "vid/did=%x/%x\n", venderid, deviceid));
2032 } else if (deviceid == RTL_PCI_8192DE_DID ||
2033 deviceid == RTL_PCI_8192DE_DID2) {
2034 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
2035 RT_TRACE(COMP_INIT, DBG_DMESG,
2036 ("8192D PCI-E is found - "
2037 "vid/did=%x/%x\n", venderid, deviceid));
2038 }else if(deviceid == RTL_PCI_8188EE_DID){
2039 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
2040 RT_TRACE(COMP_INIT,DBG_LOUD,
2041 ("Find adapter, Hardware type is 8188EE\n"));
2042 }else if (deviceid == RTL_PCI_8723BE_DID){
2043 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
2044 RT_TRACE(COMP_INIT,DBG_LOUD,
2045 ("Find adapter, Hardware type is 8723BE\n"));
2046 }else if (deviceid == RTL_PCI_8192EE_DID){
2047 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
2048 RT_TRACE(COMP_INIT,DBG_LOUD,
2049 ("Find adapter, Hardware type is 8192EE\n"));
2050 }else if (deviceid == RTL_PCI_8821AE_DID) {
2051 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
2052 RT_TRACE(COMP_INIT,DBG_LOUD,
2053 ("Find adapter, Hardware type is 8821AE\n"));
2054 }else if (deviceid == RTL_PCI_8812AE_DID) {
2055 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
2056 RT_TRACE(COMP_INIT,DBG_LOUD,
2057 ("Find adapter, Hardware type is 8812AE\n"));
2058 }else {
2059 RT_TRACE(COMP_ERR, DBG_WARNING,
2060 ("Err: Unknown device -"
2061 " vid/did=%x/%x\n", venderid, deviceid));
2062
2063 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
2064 }
2065
2066 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
2067 if (revisionid == 0 || revisionid == 1) {
2068 if (revisionid == 0) {
2069 RT_TRACE(COMP_INIT, DBG_LOUD,
2070 ("Find 92DE MAC0.\n"));
2071 rtlhal->interfaceindex = 0;
2072 } else if (revisionid == 1) {
2073 RT_TRACE(COMP_INIT, DBG_LOUD,
2074 ("Find 92DE MAC1.\n"));
2075 rtlhal->interfaceindex = 1;
2076 }
2077 } else {
2078 RT_TRACE(COMP_INIT, DBG_LOUD, ("Unknown device - "
2079 "VendorID/DeviceID=%x/%x, Revision=%x\n",
2080 venderid, deviceid, revisionid));
2081 rtlhal->interfaceindex = 0;
2082 }
2083 }
2084
2085 /* 92ee use new trx flow */
2086 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
2087 rtlpriv->use_new_trx_flow = true;
2088 else
2089 rtlpriv->use_new_trx_flow = false;
2090
2091 /*find bus info */
2092 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2093 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2094 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2095
2096 /*find bridge info */
2097 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2098 /* some ARM have no bridge_pdev and will crash here
2099 * so we should check if bridge_pdev is NULL */
2100 if (bridge_pdev) {
2101 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2102 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2103 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2104 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2105 RT_TRACE(COMP_INIT, DBG_DMESG,
2106 ("Pci Bridge Vendor is found index: %d\n",
2107 tmp));
2108 break;
2109 }
2110 }
2111 }
2112
2113 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2114 PCI_BRIDGE_VENDOR_UNKNOWN) {
2115 pcipriv->ndis_adapter.pcibridge_busnum =
2116 bridge_pdev->bus->number;
2117 pcipriv->ndis_adapter.pcibridge_devnum =
2118 PCI_SLOT(bridge_pdev->devfn);
2119 pcipriv->ndis_adapter.pcibridge_funcnum =
2120 PCI_FUNC(bridge_pdev->devfn);
2121 pcipriv->ndis_adapter.pcicfg_addrport =
2122 (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
2123 (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
2124 (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
2125 /*<delete in kernel start>*/
2126 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
2127 /*<delete in kernel end>*/
2128 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2129 pci_pcie_cap(bridge_pdev);
2130 /*<delete in kernel start>*/
2131 #else
2132 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2133 _rtl_pci_get_pciehdr_offset(hw);
2134 #endif
2135 /*<delete in kernel end>*/
2136 pcipriv->ndis_adapter.num4bytes =
2137 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2138
2139 rtl_pci_get_linkcontrol_field(hw);
2140
2141 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2142 PCI_BRIDGE_VENDOR_AMD) {
2143 pcipriv->ndis_adapter.amd_l1_patch =
2144 rtl_pci_get_amd_l1_patch(hw);
2145 }
2146 }
2147
2148 RT_TRACE(COMP_INIT, DBG_DMESG,
2149 ("pcidev busnumber:devnumber:funcnumber:"
2150 "vendor:link_ctl %d:%d:%d:%x:%x\n",
2151 pcipriv->ndis_adapter.busnumber,
2152 pcipriv->ndis_adapter.devnumber,
2153 pcipriv->ndis_adapter.funcnumber,
2154 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
2155
2156 RT_TRACE(COMP_INIT, DBG_DMESG,
2157 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
2158 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2159 pcipriv->ndis_adapter.pcibridge_busnum,
2160 pcipriv->ndis_adapter.pcibridge_devnum,
2161 pcipriv->ndis_adapter.pcibridge_funcnum,
2162 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2163 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2164 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2165 pcipriv->ndis_adapter.amd_l1_patch));
2166
2167 rtl_pci_parse_configuration(pdev, hw);
2168 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2169 return true;
2170 }
2171
2172 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2173 {
2174 struct rtl_priv *rtlpriv = rtl_priv(hw);
2175 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2176 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2177 int ret;
2178 ret = pci_enable_msi(rtlpci->pdev);
2179 if (ret < 0)
2180 return ret;
2181
2182 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2183 IRQF_SHARED, KBUILD_MODNAME, hw);
2184 if (ret < 0) {
2185 pci_disable_msi(rtlpci->pdev);
2186 return ret;
2187 }
2188
2189 rtlpci->using_msi = true;
2190
2191 RT_TRACE(COMP_INIT|COMP_INTR, DBG_DMESG, ("MSI Interrupt Mode!\n"));
2192 return 0;
2193 }
2194
2195 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2196 {
2197 struct rtl_priv *rtlpriv = rtl_priv(hw);
2198 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2199 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2200 int ret;
2201
2202 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2203 IRQF_SHARED, KBUILD_MODNAME, hw);
2204 if (ret < 0) {
2205 return ret;
2206 }
2207
2208 rtlpci->using_msi = false;
2209 RT_TRACE(COMP_INIT|COMP_INTR, DBG_DMESG,
2210 ("Pin-based Interrupt Mode!\n"));
2211 return 0;
2212 }
2213
2214 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2215 {
2216 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2217 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2218 int ret;
2219 if (rtlpci->msi_support == true) {
2220 ret = rtl_pci_intr_mode_msi(hw);
2221 if (ret < 0)
2222 ret = rtl_pci_intr_mode_legacy(hw);
2223 } else {
2224 ret = rtl_pci_intr_mode_legacy(hw);
2225 }
2226 return ret;
2227 }
2228
2229 /* this is used for other modules get
2230 * hw pointer in rtl_pci_get_hw_pointer */
2231 struct ieee80211_hw *hw_export = NULL;
2232
2233 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0))
2234 int rtl_pci_probe(struct pci_dev *pdev,
2235 const struct pci_device_id *id)
2236
2237 #else
2238 int __devinit rtl_pci_probe(struct pci_dev *pdev,
2239 const struct pci_device_id *id)
2240 #endif
2241 {
2242 struct ieee80211_hw *hw = NULL;
2243
2244 struct rtl_priv *rtlpriv = NULL;
2245 struct rtl_pci_priv *pcipriv = NULL;
2246 struct rtl_pci *rtlpci;
2247 unsigned long pmem_start, pmem_len, pmem_flags;
2248 int err;
2249
2250
2251 err = pci_enable_device(pdev);
2252 if (err) {
2253 RT_ASSERT(false,
2254 ("%s : Cannot enable new PCI device\n",
2255 pci_name(pdev)));
2256 return err;
2257 }
2258
2259 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2260 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2261 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
2262 "for consistent allocations\n"));
2263 pci_disable_device(pdev);
2264 return -ENOMEM;
2265 }
2266 }
2267
2268 pci_set_master(pdev);
2269
2270 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2271 sizeof(struct rtl_priv), &rtl_ops);
2272 if (!hw) {
2273 RT_ASSERT(false,
2274 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
2275 err = -ENOMEM;
2276 goto fail1;
2277 }
2278 hw_export = hw;
2279
2280 SET_IEEE80211_DEV(hw, &pdev->dev);
2281 pci_set_drvdata(pdev, hw);
2282
2283 rtlpriv = hw->priv;
2284 pcipriv = (void *)rtlpriv->priv;
2285 pcipriv->dev.pdev = pdev;
2286
2287 /* init cfg & intf_ops */
2288 rtlpriv->rtlhal.interface = INTF_PCI;
2289 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2290 rtlpriv->intf_ops = &rtl_pci_ops;
2291 rtlpriv->glb_var = &global_var;
2292
2293 /*
2294 *init dbgp flags before all
2295 *other functions, because we will
2296 *use it in other funtions like
2297 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
2298 *you can not use these macro
2299 *before this
2300 */
2301 rtl_dbgp_flag_init(hw);
2302
2303 /* MEM map */
2304 err = pci_request_regions(pdev, KBUILD_MODNAME);
2305 if (err) {
2306 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
2307 return err;
2308 }
2309
2310 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2311 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2312 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2313
2314 /*shared mem start */
2315 rtlpriv->io.pci_mem_start =
2316 (unsigned long)pci_iomap(pdev,
2317 rtlpriv->cfg->bar_id, pmem_len);
2318 if (rtlpriv->io.pci_mem_start == 0) {
2319 RT_ASSERT(false, ("Can't map PCI mem\n"));
2320 goto fail2;
2321 }
2322
2323 RT_TRACE(COMP_INIT, DBG_DMESG,
2324 ("mem mapped space: start: 0x%08lx len:%08lx "
2325 "flags:%08lx, after map:0x%08lx\n",
2326 pmem_start, pmem_len, pmem_flags,
2327 rtlpriv->io.pci_mem_start));
2328
2329 /* Disable Clk Request */
2330 pci_write_config_byte(pdev, 0x81, 0);
2331 /* leave D3 mode */
2332 pci_write_config_byte(pdev, 0x44, 0);
2333 pci_write_config_byte(pdev, 0x04, 0x06);
2334 pci_write_config_byte(pdev, 0x04, 0x07);
2335
2336 /* find adapter */
2337 /* if chip not support, will return false */
2338 if(!_rtl_pci_find_adapter(pdev, hw))
2339 goto fail3;
2340
2341 /* Init IO handler */
2342 _rtl_pci_io_handler_init(&pdev->dev, hw);
2343
2344 /*like read eeprom and so on */
2345 rtlpriv->cfg->ops->read_eeprom_info(hw);
2346
2347 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2348 RT_TRACE(COMP_ERR, DBG_EMERG, ("Can't init_sw_vars.\n"));
2349 goto fail3;
2350 }
2351
2352 rtlpriv->cfg->ops->init_sw_leds(hw);
2353
2354 /*aspm */
2355 rtl_pci_init_aspm(hw);
2356
2357 /* Init mac80211 sw */
2358 err = rtl_init_core(hw);
2359 if (err) {
2360 RT_TRACE(COMP_ERR, DBG_EMERG,
2361 ("Can't allocate sw for mac80211.\n"));
2362 goto fail3;
2363 }
2364
2365 /* Init PCI sw */
2366 err = !rtl_pci_init(hw, pdev);
2367 if (err) {
2368 RT_TRACE(COMP_ERR, DBG_EMERG, ("Failed to init PCI.\n"));
2369 goto fail3;
2370 }
2371
2372 err = ieee80211_register_hw(hw);
2373 if (err) {
2374 RT_TRACE(COMP_ERR, DBG_EMERG,
2375 ("Can't register mac80211 hw.\n"));
2376 goto fail3;
2377 } else {
2378 rtlpriv->mac80211.mac80211_registered = 1;
2379 }
2380 /* the wiphy must have been registed to
2381 * cfg80211 prior to regulatory_hint */
2382 if (regulatory_hint(hw->wiphy, rtlpriv->regd.alpha2)) {
2383 RT_TRACE(COMP_ERR, DBG_WARNING, ("regulatory_hint fail\n"));
2384 }
2385
2386 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
2387 if (err) {
2388 RT_TRACE(COMP_ERR, DBG_EMERG,
2389 ("failed to create sysfs device attributes\n"));
2390 goto fail3;
2391 }
2392 /* add for prov */
2393 rtl_proc_add_one(hw);
2394
2395 /*init rfkill */
2396 rtl_init_rfkill(hw);
2397
2398 rtlpci = rtl_pcidev(pcipriv);
2399
2400 err = rtl_pci_intr_mode_decide(hw);
2401 if (err) {
2402 RT_TRACE(COMP_INIT, DBG_DMESG,
2403 ("%s: failed to register IRQ handler\n",
2404 wiphy_name(hw->wiphy)));
2405 goto fail3;
2406 } else {
2407 rtlpci->irq_alloc = 1;
2408 }
2409
2410 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2411 return 0;
2412
2413 fail3:
2414 pci_set_drvdata(pdev, NULL);
2415 rtl_deinit_core(hw);
2416 ieee80211_free_hw(hw);
2417
2418 if (rtlpriv->io.pci_mem_start != 0)
2419 pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start);
2420
2421 fail2:
2422 pci_release_regions(pdev);
2423
2424 fail1:
2425
2426 pci_disable_device(pdev);
2427
2428 return -ENODEV;
2429
2430 }
2431 //EXPORT_SYMBOL(rtl_pci_probe);
2432
2433 struct ieee80211_hw *rtl_pci_get_hw_pointer(void)
2434 {
2435 return hw_export;
2436 }
2437 //EXPORT_SYMBOL(rtl_pci_get_hw_pointer);
2438
2439 void rtl_pci_disconnect(struct pci_dev *pdev)
2440 {
2441 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2442 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2443 struct rtl_priv *rtlpriv = rtl_priv(hw);
2444 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2445 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2446
2447 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2448
2449 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
2450
2451 /* add for prov */
2452 rtl_proc_remove_one(hw);
2453
2454
2455 /*ieee80211_unregister_hw will call ops_stop */
2456 if (rtlmac->mac80211_registered == 1) {
2457 ieee80211_unregister_hw(hw);
2458 rtlmac->mac80211_registered = 0;
2459 } else {
2460 rtl_deinit_deferred_work(hw);
2461 rtlpriv->intf_ops->adapter_stop(hw);
2462 }
2463
2464 /*deinit rfkill */
2465 rtl_deinit_rfkill(hw);
2466
2467 rtl_pci_deinit(hw);
2468 rtl_deinit_core(hw);
2469 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2470
2471 if (rtlpci->irq_alloc) {
2472 synchronize_irq(rtlpci->pdev->irq);
2473 free_irq(rtlpci->pdev->irq, hw);
2474 rtlpci->irq_alloc = 0;
2475 }
2476
2477 if (rtlpci->using_msi == true)
2478 pci_disable_msi(rtlpci->pdev);
2479
2480 list_del(&rtlpriv->list);
2481 if (rtlpriv->io.pci_mem_start != 0) {
2482 pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start);
2483 pci_release_regions(pdev);
2484 }
2485
2486 pci_disable_device(pdev);
2487
2488 rtl_pci_disable_aspm(hw);
2489
2490 pci_set_drvdata(pdev, NULL);
2491
2492 ieee80211_free_hw(hw);
2493 }
2494 //EXPORT_SYMBOL(rtl_pci_disconnect);
2495
2496 /***************************************
2497 kernel pci power state define:
2498 PCI_D0 ((pci_power_t __force) 0)
2499 PCI_D1 ((pci_power_t __force) 1)
2500 PCI_D2 ((pci_power_t __force) 2)
2501 PCI_D3hot ((pci_power_t __force) 3)
2502 PCI_D3cold ((pci_power_t __force) 4)
2503 PCI_UNKNOWN ((pci_power_t __force) 5)
2504
2505 This function is called when system
2506 goes into suspend state mac80211 will
2507 call rtl_mac_stop() from the mac80211
2508 suspend function first, So there is
2509 no need to call hw_disable here.
2510 ****************************************/
2511 int rtl_pci_suspend(struct device *dev)
2512 {
2513 struct pci_dev *pdev = to_pci_dev(dev);
2514 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2515 struct rtl_priv *rtlpriv = rtl_priv(hw);
2516
2517 rtlpriv->cfg->ops->hw_suspend(hw);
2518 rtl_deinit_rfkill(hw);
2519
2520 return 0;
2521 }
2522 //EXPORT_SYMBOL(rtl_pci_suspend);
2523
2524 int rtl_pci_resume(struct device *dev)
2525 {
2526 struct pci_dev *pdev = to_pci_dev(dev);
2527 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2528 struct rtl_priv *rtlpriv = rtl_priv(hw);
2529
2530 rtlpriv->cfg->ops->hw_resume(hw);
2531 rtl_init_rfkill(hw);
2532
2533 return 0;
2534 }
2535 //EXPORT_SYMBOL(rtl_pci_resume);
2536
2537 struct rtl_intf_ops rtl_pci_ops = {
2538 .read_efuse_byte = read_efuse_byte,
2539 .adapter_start = rtl_pci_start,
2540 .adapter_stop = rtl_pci_stop,
2541 .check_buddy_priv = rtl_pci_check_buddy_priv,
2542 .adapter_tx = rtl_pci_tx,
2543 .flush = rtl_pci_flush,
2544 .reset_trx_ring = rtl_pci_reset_trx_ring,
2545 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2546
2547 .disable_aspm = rtl_pci_disable_aspm,
2548 .enable_aspm = rtl_pci_enable_aspm,
2549 };
Linux with added FPC-III support