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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / drivers / staging / vt6655 / rf.c
blobedb1b2768b17353bc93aed5a82f929b91fb78499
1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 *
20 * File: rf.c
21 *
22 * Purpose: rf function code
23 *
24 * Author: Jerry Chen
25 *
26 * Date: Feb. 19, 2004
27 *
28 * Functions:
29 * IFRFbWriteEmbedded - Embedded write RF register via MAC
30 *
31 * Revision History:
32 *
33 */
34
35 #include "mac.h"
36 #include "srom.h"
37 #include "rf.h"
38 #include "baseband.h"
39
40 /*--------------------- Static Definitions -------------------------*/
41
42 //static int msglevel =MSG_LEVEL_INFO;
43
44 #define BY_AL2230_REG_LEN 23 //24bit
45 #define CB_AL2230_INIT_SEQ 15
46 #define SWITCH_CHANNEL_DELAY_AL2230 200 //us
47 #define AL2230_PWR_IDX_LEN 64
48
49 #define BY_AL7230_REG_LEN 23 //24bit
50 #define CB_AL7230_INIT_SEQ 16
51 #define SWITCH_CHANNEL_DELAY_AL7230 200 //us
52 #define AL7230_PWR_IDX_LEN 64
53
54 /*--------------------- Static Classes ----------------------------*/
55
56 /*--------------------- Static Variables --------------------------*/
57
58 static const unsigned long dwAL2230InitTable[CB_AL2230_INIT_SEQ] = {
59 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
60 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
61 0x01A00200+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
62 0x00FFF300+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
63 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
64 0x0F4DC500+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
65 0x0805B600+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
66 0x0146C700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
67 0x00068800+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
68 0x0403B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
69 0x00DBBA00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
70 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
71 0x0BDFFC00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
72 0x00000D00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
73 0x00580F00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
74 };
75
76 static const unsigned long dwAL2230ChannelTable0[CB_MAX_CHANNEL] = {
77 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
78 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
79 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
80 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
81 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
82 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
83 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
84 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
85 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
86 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
87 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
88 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
89 0x03F7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
90 0x03E7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M
91 };
92
93 static const unsigned long dwAL2230ChannelTable1[CB_MAX_CHANNEL] = {
94 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
95 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
96 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
97 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
98 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
99 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
100 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
101 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
102 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
103 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
104 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
105 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
106 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
107 0x06666100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M
108 };
109
110 static unsigned long dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = {
111 0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
112 0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
113 0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
114 0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
115 0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
116 0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
117 0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
118 0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
119 0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
120 0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
121 0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
122 0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
123 0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
124 0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
125 0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
126 0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
127 0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
128 0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
129 0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
130 0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
131 0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
132 0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
133 0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
134 0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
135 0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
136 0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
137 0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
138 0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
139 0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
140 0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
141 0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
142 0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
143 0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
144 0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
145 0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
146 0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
147 0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
148 0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
149 0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
150 0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
151 0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
152 0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
153 0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
154 0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
155 0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
156 0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
157 0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
158 0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
159 0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
160 0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
161 0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
162 0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
163 0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
164 0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
165 0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
166 0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
167 0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
168 0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
169 0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
170 0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
171 0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
172 0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
173 0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
174 0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
175 };
176
177 //{{ RobertYu:20050104
178 // 40MHz reference frequency
179 // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
180 static const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = {
181 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a
182 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a
183 0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 451FE2
184 0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 5FDFA3
185 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11b/g // Need modify for 11a
186 //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45
187 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
188 0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B55
189 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
190 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 860207
191 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
192 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
193 0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: E0600A
194 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
195 //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
196 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
197 0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
198 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
199 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
200 0x1ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11a: 12BACF
201 };
202
203 static const unsigned long dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = {
204 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g
205 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g
206 0x451FE200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
207 0x5FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
208 0x67F78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11a // Need modify for 11b/g
209 0x853F5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g, RoberYu:20050113
210 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
211 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
212 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
213 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
214 0xE0600A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
215 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
216 0x00147C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
217 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
218 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
219 0x12BACF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11b/g
220 };
221
222 static const unsigned long dwAL7230ChannelTable0[CB_MAX_CHANNEL] = {
223 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
224 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
225 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
226 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
227 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
228 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
229 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
230 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49
231 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49
232 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49
233 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49
234 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49
235 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49
236 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
237
238 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
239 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
240 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
241 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
242 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
243 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
244 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
245 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
246 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
247
248 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
249 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
250
251 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23)
252 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24)
253 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25)
254 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26)
255 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27)
256 0x0FF55000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28)
257 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29)
258 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30)
259 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49
260 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32)
261 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33)
262 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34)
263 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35)
264 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36)
265 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37)
266 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38)
267 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39)
268 0x0FF59000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40)
269
270 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
271 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
272 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
273 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
274 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
275 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
276 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
277 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
278 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
279 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
280 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
281 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
282 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
283 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
284 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
285 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56)
286 };
287
288 static const unsigned long dwAL7230ChannelTable1[CB_MAX_CHANNEL] = {
289 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
290 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
291 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
292 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
293 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
294 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
295 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
296 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
297 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
298 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
299 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
300 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
301 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
302 0x06666100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
303
304 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
305 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
306 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
307 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
308 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
309 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
310 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
311 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
312 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
313
314 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
315 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
316 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23)
317 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24)
318 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25)
319 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26)
320 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27)
321 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28)
322 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29)
323 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30)
324 0x10000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31)
325 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32)
326 0x1AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33)
327 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34)
328 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35)
329 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36)
330 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37)
331 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38)
332 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39)
333 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40)
334 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
335 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
336 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
337 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
338 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
339 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
340 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
341 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
342 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
343 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
344 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
345 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
346 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
347 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
348 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
349 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56)
350 };
351
352 static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = {
353 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
354 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
355 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
356 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
357 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
358 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
359 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
360 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
361 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
362 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
363 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
364 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
365 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
366 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
367
368 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
369 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
370 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
371 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
372 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
373 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
374 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
375 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
376 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
377
378 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
379 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
380 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23)
381 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24)
382 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25)
383 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26)
384 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27)
385 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28)
386 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29)
387 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30)
388 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31)
389 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32)
390 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33)
391 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34)
392 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35)
393 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36)
394 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37)
395 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38)
396 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39)
397 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40)
398 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
399 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
400 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
401 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
402 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
403 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
404 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
405 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
406 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
407 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
408 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
409 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
410 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
411 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
412 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
413 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56)
414 };
415 //}} RobertYu
416
417 /*--------------------- Static Functions --------------------------*/
418
419 /*
420 * Description: AIROHA IFRF chip init function
421 *
422 * Parameters:
423 * In:
424 * dwIoBase - I/O base address
425 * Out:
426 * none
427 *
428 * Return Value: true if succeeded; false if failed.
429 *
430 */
431 static bool s_bAL7230Init(unsigned long dwIoBase)
432 {
433 int ii;
434 bool bResult;
435
436 bResult = true;
437
438 //3-wire control for normal mode
439 VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0);
440
441 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI |
442 SOFTPWRCTL_TXPEINV));
443 BBvPowerSaveModeOFF(dwIoBase); //RobertYu:20050106, have DC value for Calibration
444
445 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
446 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[ii]);
447
448 // PLL On
449 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
450
451 //Calibration
452 MACvTimer0MicroSDelay(dwIoBase, 150);//150us
453 bResult &= IFRFbWriteEmbedded(dwIoBase, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:active, RCK:disable
454 MACvTimer0MicroSDelay(dwIoBase, 30);//30us
455 bResult &= IFRFbWriteEmbedded(dwIoBase, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:disable, RCK:active
456 MACvTimer0MicroSDelay(dwIoBase, 30);//30us
457 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]); //TXDCOC:disable, RCK:disable
458
459 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
460 SOFTPWRCTL_SWPE2 |
461 SOFTPWRCTL_SWPECTI |
462 SOFTPWRCTL_TXPEINV));
463
464 BBvPowerSaveModeON(dwIoBase); // RobertYu:20050106
465
466 // PE1: TX_ON, PE2: RX_ON, PE3: PLLON
467 //3-wire control for power saving mode
468 VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000
469
470 return bResult;
471 }
472
473 // Need to Pull PLLON low when writing channel registers through 3-wire interface
474 static bool s_bAL7230SelectChannel(unsigned long dwIoBase, unsigned char byChannel)
475 {
476 bool bResult;
477
478 bResult = true;
479
480 // PLLON Off
481 MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
482
483 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230ChannelTable0[byChannel - 1]); //Reg0
484 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230ChannelTable1[byChannel - 1]); //Reg1
485 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230ChannelTable2[byChannel - 1]); //Reg4
486
487 // PLLOn On
488 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
489
490 // Set Channel[7] = 0 to tell H/W channel is changing now.
491 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F));
492 MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL7230);
493 // Set Channel[7] = 1 to tell H/W channel change is done.
494 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80));
495
496 return bResult;
497 }
498
499 /*
500 * Description: Select channel with UW2452 chip
501 *
502 * Parameters:
503 * In:
504 * dwIoBase - I/O base address
505 * uChannel - Channel number
506 * Out:
507 * none
508 *
509 * Return Value: true if succeeded; false if failed.
510 *
511 */
512
513 //{{ RobertYu: 20041210
514 /*
515 * Description: UW2452 IFRF chip init function
516 *
517 * Parameters:
518 * In:
519 * dwIoBase - I/O base address
520 * Out:
521 * none
522 *
523 * Return Value: true if succeeded; false if failed.
524 *
525 */
526
527 //}} RobertYu
528 ////////////////////////////////////////////////////////////////////////////////
529
530 /*
531 * Description: VT3226 IFRF chip init function
532 *
533 * Parameters:
534 * In:
535 * dwIoBase - I/O base address
536 * Out:
537 * none
538 *
539 * Return Value: true if succeeded; false if failed.
540 *
541 */
542
543 /*
544 * Description: Select channel with VT3226 chip
545 *
546 * Parameters:
547 * In:
548 * dwIoBase - I/O base address
549 * uChannel - Channel number
550 * Out:
551 * none
552 *
553 * Return Value: true if succeeded; false if failed.
554 *
555 */
556
557 /*--------------------- Export Variables --------------------------*/
558
559 /*--------------------- Export Functions --------------------------*/
560
561 /*
562 * Description: Write to IF/RF, by embedded programming
563 *
564 * Parameters:
565 * In:
566 * dwIoBase - I/O base address
567 * dwData - data to write
568 * Out:
569 * none
570 *
571 * Return Value: true if succeeded; false if failed.
572 *
573 */
574 bool IFRFbWriteEmbedded(unsigned long dwIoBase, unsigned long dwData)
575 {
576 unsigned short ww;
577 unsigned long dwValue;
578
579 VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData);
580
581 // W_MAX_TIMEOUT is the timeout period
582 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
583 VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue);
584 if (dwValue & IFREGCTL_DONE)
585 break;
586 }
587
588 if (ww == W_MAX_TIMEOUT) {
589 // DBG_PORT80_ALWAYS(0x32);
590 return false;
591 }
592 return true;
593 }
594
595 /*
596 * Description: RFMD RF2959 IFRF chip init function
597 *
598 * Parameters:
599 * In:
600 * dwIoBase - I/O base address
601 * Out:
602 * none
603 *
604 * Return Value: true if succeeded; false if failed.
605 *
606 */
607
608 /*
609 * Description: Select channel with RFMD 2959 chip
610 *
611 * Parameters:
612 * In:
613 * dwIoBase - I/O base address
614 * uChannel - Channel number
615 * Out:
616 * none
617 *
618 * Return Value: true if succeeded; false if failed.
619 *
620 */
621
622 /*
623 * Description: AIROHA IFRF chip init function
624 *
625 * Parameters:
626 * In:
627 * dwIoBase - I/O base address
628 * Out:
629 * none
630 *
631 * Return Value: true if succeeded; false if failed.
632 *
633 */
634 static bool RFbAL2230Init(unsigned long dwIoBase)
635 {
636 int ii;
637 bool bResult;
638
639 bResult = true;
640
641 //3-wire control for normal mode
642 VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0);
643
644 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI |
645 SOFTPWRCTL_TXPEINV));
646 //2008-8-21 chester <add>
647 // PLL Off
648
649 MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
650
651 //patch abnormal AL2230 frequency output
652 //2008-8-21 chester <add>
653 IFRFbWriteEmbedded(dwIoBase, (0x07168700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
654
655 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
656 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230InitTable[ii]);
657 //2008-8-21 chester <add>
658 MACvTimer0MicroSDelay(dwIoBase, 30); //delay 30 us
659
660 // PLL On
661 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
662
663 MACvTimer0MicroSDelay(dwIoBase, 150);//150us
664 bResult &= IFRFbWriteEmbedded(dwIoBase, (0x00d80f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
665 MACvTimer0MicroSDelay(dwIoBase, 30);//30us
666 bResult &= IFRFbWriteEmbedded(dwIoBase, (0x00780f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
667 MACvTimer0MicroSDelay(dwIoBase, 30);//30us
668 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]);
669
670 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
671 SOFTPWRCTL_SWPE2 |
672 SOFTPWRCTL_SWPECTI |
673 SOFTPWRCTL_TXPEINV));
674
675 //3-wire control for power saving mode
676 VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000
677
678 return bResult;
679 }
680
681 static bool RFbAL2230SelectChannel(unsigned long dwIoBase, unsigned char byChannel)
682 {
683 bool bResult;
684
685 bResult = true;
686
687 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230ChannelTable0[byChannel - 1]);
688 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230ChannelTable1[byChannel - 1]);
689
690 // Set Channel[7] = 0 to tell H/W channel is changing now.
691 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F));
692 MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL2230);
693 // Set Channel[7] = 1 to tell H/W channel change is done.
694 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80));
695
696 return bResult;
697 }
698
699 /*
700 * Description: UW2451 IFRF chip init function
701 *
702 * Parameters:
703 * In:
704 * dwIoBase - I/O base address
705 * Out:
706 * none
707 *
708 * Return Value: true if succeeded; false if failed.
709 *
710 */
711
712 /*
713 * Description: Select channel with UW2451 chip
714 *
715 * Parameters:
716 * In:
717 * dwIoBase - I/O base address
718 * uChannel - Channel number
719 * Out:
720 * none
721 *
722 * Return Value: true if succeeded; false if failed.
723 *
724 */
725
726 /*
727 * Description: Set sleep mode to UW2451 chip
728 *
729 * Parameters:
730 * In:
731 * dwIoBase - I/O base address
732 * uChannel - Channel number
733 * Out:
734 * none
735 *
736 * Return Value: true if succeeded; false if failed.
737 *
738 */
739
740 /*
741 * Description: RF init function
742 *
743 * Parameters:
744 * In:
745 * byBBType
746 * byRFType
747 * Out:
748 * none
749 *
750 * Return Value: true if succeeded; false if failed.
751 *
752 */
753 bool RFbInit(
754 PSDevice pDevice
755 )
756 {
757 bool bResult = true;
758 switch (pDevice->byRFType) {
759 case RF_AIROHA:
760 case RF_AL2230S:
761 pDevice->byMaxPwrLevel = AL2230_PWR_IDX_LEN;
762 bResult = RFbAL2230Init(pDevice->PortOffset);
763 break;
764 case RF_AIROHA7230:
765 pDevice->byMaxPwrLevel = AL7230_PWR_IDX_LEN;
766 bResult = s_bAL7230Init(pDevice->PortOffset);
767 break;
768 case RF_NOTHING:
769 bResult = true;
770 break;
771 default:
772 bResult = false;
773 break;
774 }
775 return bResult;
776 }
777
778 /*
779 * Description: Select channel
780 *
781 * Parameters:
782 * In:
783 * byRFType
784 * byChannel - Channel number
785 * Out:
786 * none
787 *
788 * Return Value: true if succeeded; false if failed.
789 *
790 */
791 bool RFbSelectChannel(unsigned long dwIoBase, unsigned char byRFType, unsigned char byChannel)
792 {
793 bool bResult = true;
794 switch (byRFType) {
795 case RF_AIROHA:
796 case RF_AL2230S:
797 bResult = RFbAL2230SelectChannel(dwIoBase, byChannel);
798 break;
799 //{{ RobertYu: 20050104
800 case RF_AIROHA7230:
801 bResult = s_bAL7230SelectChannel(dwIoBase, byChannel);
802 break;
803 //}} RobertYu
804 case RF_NOTHING:
805 bResult = true;
806 break;
807 default:
808 bResult = false;
809 break;
810 }
811 return bResult;
812 }
813
814 /*
815 * Description: Write WakeProgSyn
816 *
817 * Parameters:
818 * In:
819 * dwIoBase - I/O base address
820 * uChannel - channel number
821 * bySleepCnt - SleepProgSyn count
822 *
823 * Return Value: None.
824 *
825 */
826 bool RFvWriteWakeProgSyn(unsigned long dwIoBase, unsigned char byRFType, unsigned int uChannel)
827 {
828 int ii;
829 unsigned char byInitCount = 0;
830 unsigned char bySleepCount = 0;
831
832 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0);
833 switch (byRFType) {
834 case RF_AIROHA:
835 case RF_AL2230S:
836
837 if (uChannel > CB_MAX_CHANNEL_24G)
838 return false;
839
840 byInitCount = CB_AL2230_INIT_SEQ + 2; // Init Reg + Channel Reg (2)
841 bySleepCount = 0;
842 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) {
843 return false;
844 }
845
846 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) {
847 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]);
848 }
849 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]);
850 ii++;
851 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]);
852 break;
853
854 //{{ RobertYu: 20050104
855 // Need to check, PLLON need to be low for channel setting
856 case RF_AIROHA7230:
857 byInitCount = CB_AL7230_INIT_SEQ + 3; // Init Reg + Channel Reg (3)
858 bySleepCount = 0;
859 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) {
860 return false;
861 }
862
863 if (uChannel <= CB_MAX_CHANNEL_24G) {
864 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) {
865 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]);
866 }
867 } else {
868 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) {
869 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]);
870 }
871 }
872
873 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]);
874 ii++;
875 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]);
876 ii++;
877 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]);
878 break;
879 //}} RobertYu
880
881 case RF_NOTHING:
882 return true;
883 break;
884
885 default:
886 return false;
887 break;
888 }
889
890 MACvSetMISCFifo(dwIoBase, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(bySleepCount, byInitCount));
891
892 return true;
893 }
894
895 /*
896 * Description: Set Tx power
897 *
898 * Parameters:
899 * In:
900 * dwIoBase - I/O base address
901 * dwRFPowerTable - RF Tx Power Setting
902 * Out:
903 * none
904 *
905 * Return Value: true if succeeded; false if failed.
906 *
907 */
908 bool RFbSetPower(
909 PSDevice pDevice,
910 unsigned int uRATE,
911 unsigned int uCH
912 )
913 {
914 bool bResult = true;
915 unsigned char byPwr = 0;
916 unsigned char byDec = 0;
917 unsigned char byPwrdBm = 0;
918
919 if (pDevice->dwDiagRefCount != 0) {
920 return true;
921 }
922 if ((uCH < 1) || (uCH > CB_MAX_CHANNEL)) {
923 return false;
924 }
925
926 switch (uRATE) {
927 case RATE_1M:
928 case RATE_2M:
929 case RATE_5M:
930 case RATE_11M:
931 byPwr = pDevice->abyCCKPwrTbl[uCH];
932 byPwrdBm = pDevice->abyCCKDefaultPwr[uCH];
933 //PLICE_DEBUG->
934 //byPwr+=5;
935 //PLICE_DEBUG <-
936 break;
937 case RATE_6M:
938 case RATE_9M:
939 case RATE_18M:
940 byPwr = pDevice->abyOFDMPwrTbl[uCH];
941 if (pDevice->byRFType == RF_UW2452) {
942 byDec = byPwr + 14;
943 } else {
944 byDec = byPwr + 10;
945 }
946 if (byDec >= pDevice->byMaxPwrLevel) {
947 byDec = pDevice->byMaxPwrLevel-1;
948 }
949 if (pDevice->byRFType == RF_UW2452) {
950 byPwrdBm = byDec - byPwr;
951 byPwrdBm /= 3;
952 } else {
953 byPwrdBm = byDec - byPwr;
954 byPwrdBm >>= 1;
955 }
956 byPwrdBm += pDevice->abyOFDMDefaultPwr[uCH];
957 byPwr = byDec;
958 //PLICE_DEBUG->
959 //byPwr+=5;
960 //PLICE_DEBUG<-
961 break;
962 case RATE_24M:
963 case RATE_36M:
964 case RATE_48M:
965 case RATE_54M:
966 byPwr = pDevice->abyOFDMPwrTbl[uCH];
967 byPwrdBm = pDevice->abyOFDMDefaultPwr[uCH];
968 //PLICE_DEBUG->
969 //byPwr+=5;
970 //PLICE_DEBUG<-
971 break;
972 }
973
974 if (pDevice->byCurPwr == byPwr) {
975 return true;
976 }
977
978 bResult = RFbRawSetPower(pDevice, byPwr, uRATE);
979 if (bResult) {
980 pDevice->byCurPwr = byPwr;
981 }
982 return bResult;
983 }
984
985 /*
986 * Description: Set Tx power
987 *
988 * Parameters:
989 * In:
990 * dwIoBase - I/O base address
991 * dwRFPowerTable - RF Tx Power Setting
992 * Out:
993 * none
994 *
995 * Return Value: true if succeeded; false if failed.
996 *
997 */
998
999 bool RFbRawSetPower(
1000 PSDevice pDevice,
1001 unsigned char byPwr,
1002 unsigned int uRATE
1003 )
1004 {
1005 bool bResult = true;
1006 unsigned long dwMax7230Pwr = 0;
1007
1008 if (byPwr >= pDevice->byMaxPwrLevel) {
1009 return false;
1010 }
1011 switch (pDevice->byRFType) {
1012 case RF_AIROHA:
1013 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]);
1014 if (uRATE <= RATE_11M) {
1015 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1016 } else {
1017 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1018 }
1019 break;
1020
1021 case RF_AL2230S:
1022 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]);
1023 if (uRATE <= RATE_11M) {
1024 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1025 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1026 } else {
1027 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1028 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1029 }
1030
1031 break;
1032
1033 case RF_AIROHA7230:
1034 // 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value
1035 dwMax7230Pwr = 0x080C0B00 | ((byPwr) << 12) |
1036 (BY_AL7230_REG_LEN << 3) | IFREGCTL_REGW;
1037
1038 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwMax7230Pwr);
1039 break;
1040
1041 default:
1042 break;
1043 }
1044 return bResult;
1045 }
1046
1047 /*+
1048 *
1049 * Routine Description:
1050 * Translate RSSI to dBm
1051 *
1052 * Parameters:
1053 * In:
1054 * pDevice - The adapter to be translated
1055 * byCurrRSSI - RSSI to be translated
1056 * Out:
1057 * pdwdbm - Translated dbm number
1058 *
1059 * Return Value: none
1060 *
1061 -*/
1062 void
1063 RFvRSSITodBm(
1064 PSDevice pDevice,
1065 unsigned char byCurrRSSI,
1066 long *pldBm
1067 )
1068 {
1069 unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
1070 long b = (byCurrRSSI & 0x3F);
1071 long a = 0;
1072 unsigned char abyAIROHARF[4] = {0, 18, 0, 40};
1073
1074 switch (pDevice->byRFType) {
1075 case RF_AIROHA:
1076 case RF_AL2230S:
1077 case RF_AIROHA7230: //RobertYu: 20040104
1078 a = abyAIROHARF[byIdx];
1079 break;
1080 default:
1081 break;
1082 }
1083
1084 *pldBm = -1 * (a + b * 2);
1085 }
1086
1087 ////////////////////////////////////////////////////////////////////////////////
1088 //{{ RobertYu: 20050104
1089
1090 // Post processing for the 11b/g and 11a.
1091 // for save time on changing Reg2,3,5,7,10,12,15
1092 bool RFbAL7230SelectChannelPostProcess(unsigned long dwIoBase, unsigned char byOldChannel, unsigned char byNewChannel)
1093 {
1094 bool bResult;
1095
1096 bResult = true;
1097
1098 // if change between 11 b/g and 11a need to update the following register
1099 // Channel Index 1~14
1100
1101 if ((byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G)) {
1102 // Change from 2.4G to 5G
1103 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[2]); //Reg2
1104 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[3]); //Reg3
1105 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[5]); //Reg5
1106 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[7]); //Reg7
1107 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[10]);//Reg10
1108 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[12]);//Reg12
1109 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[15]);//Reg15
1110 } else if ((byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G)) {
1111 // change from 5G to 2.4G
1112 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[2]); //Reg2
1113 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[3]); //Reg3
1114 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[5]); //Reg5
1115 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[7]); //Reg7
1116 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[10]);//Reg10
1117 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[12]);//Reg12
1118 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[15]);//Reg15
1119 }
1120
1121 return bResult;
1122 }
1123
1124 //}} RobertYu
1125 ////////////////////////////////////////////////////////////////////////////////
Linux with added FPC-III support