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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / drivers / tty / serial / atmel_serial.c
bloba49f10d269b20afb2e8d2a1579af8f8987ed2a16
1 /*
2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * DMA support added by Chip Coldwell.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25 #include <linux/module.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/serial.h>
31 #include <linux/clk.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/atmel_pdc.h>
40 #include <linux/atmel_serial.h>
41 #include <linux/uaccess.h>
42 #include <linux/platform_data/atmel.h>
43 #include <linux/timer.h>
44
45 #include <asm/io.h>
46 #include <asm/ioctls.h>
47
48 #ifdef CONFIG_ARM
49 #include <mach/cpu.h>
50 #include <asm/gpio.h>
51 #endif
52
53 #define PDC_BUFFER_SIZE 512
54 /* Revisit: We should calculate this based on the actual port settings */
55 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
56
57 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
58 #define SUPPORT_SYSRQ
59 #endif
60
61 #include <linux/serial_core.h>
62
63 static void atmel_start_rx(struct uart_port *port);
64 static void atmel_stop_rx(struct uart_port *port);
65
66 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
67
68 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
69 * should coexist with the 8250 driver, such as if we have an external 16C550
70 * UART. */
71 #define SERIAL_ATMEL_MAJOR 204
72 #define MINOR_START 154
73 #define ATMEL_DEVICENAME "ttyAT"
74
75 #else
76
77 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
78 * name, but it is legally reserved for the 8250 driver. */
79 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
80 #define MINOR_START 64
81 #define ATMEL_DEVICENAME "ttyS"
82
83 #endif
84
85 #define ATMEL_ISR_PASS_LIMIT 256
86
87 /* UART registers. CR is write-only, hence no GET macro */
88 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
89 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
90 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
91 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
92 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
93 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
94 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
95 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
96 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
97 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
98 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
99 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
100 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
101 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME)
102 #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
103
104 /* PDC registers */
105 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
106 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
107
108 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
109 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
110 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
111 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
112 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
113
114 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
115 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
116 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
117
118 static int (*atmel_open_hook)(struct uart_port *);
119 static void (*atmel_close_hook)(struct uart_port *);
120
121 struct atmel_dma_buffer {
122 unsigned char *buf;
123 dma_addr_t dma_addr;
124 unsigned int dma_size;
125 unsigned int ofs;
126 };
127
128 struct atmel_uart_char {
129 u16 status;
130 u16 ch;
131 };
132
133 #define ATMEL_SERIAL_RINGSIZE 1024
134
135 /*
136 * We wrap our port structure around the generic uart_port.
137 */
138 struct atmel_uart_port {
139 struct uart_port uart; /* uart */
140 struct clk *clk; /* uart clock */
141 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
142 u32 backup_imr; /* IMR saved during suspend */
143 int break_active; /* break being received */
144
145 bool use_dma_rx; /* enable DMA receiver */
146 bool use_pdc_rx; /* enable PDC receiver */
147 short pdc_rx_idx; /* current PDC RX buffer */
148 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
149
150 bool use_dma_tx; /* enable DMA transmitter */
151 bool use_pdc_tx; /* enable PDC transmitter */
152 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
153
154 spinlock_t lock_tx; /* port lock */
155 spinlock_t lock_rx; /* port lock */
156 struct dma_chan *chan_tx;
157 struct dma_chan *chan_rx;
158 struct dma_async_tx_descriptor *desc_tx;
159 struct dma_async_tx_descriptor *desc_rx;
160 dma_cookie_t cookie_tx;
161 dma_cookie_t cookie_rx;
162 struct scatterlist sg_tx;
163 struct scatterlist sg_rx;
164 struct tasklet_struct tasklet;
165 unsigned int irq_status;
166 unsigned int irq_status_prev;
167
168 struct circ_buf rx_ring;
169
170 struct serial_rs485 rs485; /* rs485 settings */
171 unsigned int tx_done_mask;
172 bool is_usart; /* usart or uart */
173 struct timer_list uart_timer; /* uart timer */
174 int (*prepare_rx)(struct uart_port *port);
175 int (*prepare_tx)(struct uart_port *port);
176 void (*schedule_rx)(struct uart_port *port);
177 void (*schedule_tx)(struct uart_port *port);
178 void (*release_rx)(struct uart_port *port);
179 void (*release_tx)(struct uart_port *port);
180 };
181
182 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
183 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
184
185 #ifdef SUPPORT_SYSRQ
186 static struct console atmel_console;
187 #endif
188
189 #if defined(CONFIG_OF)
190 static const struct of_device_id atmel_serial_dt_ids[] = {
191 { .compatible = "atmel,at91rm9200-usart" },
192 { .compatible = "atmel,at91sam9260-usart" },
193 { /* sentinel */ }
194 };
195
196 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
197 #endif
198
199 static inline struct atmel_uart_port *
200 to_atmel_uart_port(struct uart_port *uart)
201 {
202 return container_of(uart, struct atmel_uart_port, uart);
203 }
204
205 #ifdef CONFIG_SERIAL_ATMEL_PDC
206 static bool atmel_use_pdc_rx(struct uart_port *port)
207 {
208 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
209
210 return atmel_port->use_pdc_rx;
211 }
212
213 static bool atmel_use_pdc_tx(struct uart_port *port)
214 {
215 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
216
217 return atmel_port->use_pdc_tx;
218 }
219 #else
220 static bool atmel_use_pdc_rx(struct uart_port *port)
221 {
222 return false;
223 }
224
225 static bool atmel_use_pdc_tx(struct uart_port *port)
226 {
227 return false;
228 }
229 #endif
230
231 static bool atmel_use_dma_tx(struct uart_port *port)
232 {
233 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
234
235 return atmel_port->use_dma_tx;
236 }
237
238 static bool atmel_use_dma_rx(struct uart_port *port)
239 {
240 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
241
242 return atmel_port->use_dma_rx;
243 }
244
245 /* Enable or disable the rs485 support */
246 void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
247 {
248 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
249 unsigned int mode;
250 unsigned long flags;
251
252 spin_lock_irqsave(&port->lock, flags);
253
254 /* Disable interrupts */
255 UART_PUT_IDR(port, atmel_port->tx_done_mask);
256
257 mode = UART_GET_MR(port);
258
259 /* Resetting serial mode to RS232 (0x0) */
260 mode &= ~ATMEL_US_USMODE;
261
262 atmel_port->rs485 = *rs485conf;
263
264 if (rs485conf->flags & SER_RS485_ENABLED) {
265 dev_dbg(port->dev, "Setting UART to RS485\n");
266 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
267 if ((rs485conf->delay_rts_after_send) > 0)
268 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
269 mode |= ATMEL_US_USMODE_RS485;
270 } else {
271 dev_dbg(port->dev, "Setting UART to RS232\n");
272 if (atmel_use_pdc_tx(port))
273 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
274 ATMEL_US_TXBUFE;
275 else
276 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
277 }
278 UART_PUT_MR(port, mode);
279
280 /* Enable interrupts */
281 UART_PUT_IER(port, atmel_port->tx_done_mask);
282
283 spin_unlock_irqrestore(&port->lock, flags);
284
285 }
286
287 /*
288 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
289 */
290 static u_int atmel_tx_empty(struct uart_port *port)
291 {
292 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
293 }
294
295 /*
296 * Set state of the modem control output lines
297 */
298 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
299 {
300 unsigned int control = 0;
301 unsigned int mode;
302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
303
304 #ifdef CONFIG_ARCH_AT91RM9200
305 if (cpu_is_at91rm9200()) {
306 /*
307 * AT91RM9200 Errata #39: RTS0 is not internally connected
308 * to PA21. We need to drive the pin manually.
309 */
310 if (port->mapbase == AT91RM9200_BASE_US0) {
311 if (mctrl & TIOCM_RTS)
312 at91_set_gpio_value(AT91_PIN_PA21, 0);
313 else
314 at91_set_gpio_value(AT91_PIN_PA21, 1);
315 }
316 }
317 #endif
318
319 if (mctrl & TIOCM_RTS)
320 control |= ATMEL_US_RTSEN;
321 else
322 control |= ATMEL_US_RTSDIS;
323
324 if (mctrl & TIOCM_DTR)
325 control |= ATMEL_US_DTREN;
326 else
327 control |= ATMEL_US_DTRDIS;
328
329 UART_PUT_CR(port, control);
330
331 /* Local loopback mode? */
332 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
333 if (mctrl & TIOCM_LOOP)
334 mode |= ATMEL_US_CHMODE_LOC_LOOP;
335 else
336 mode |= ATMEL_US_CHMODE_NORMAL;
337
338 /* Resetting serial mode to RS232 (0x0) */
339 mode &= ~ATMEL_US_USMODE;
340
341 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
342 dev_dbg(port->dev, "Setting UART to RS485\n");
343 if ((atmel_port->rs485.delay_rts_after_send) > 0)
344 UART_PUT_TTGR(port,
345 atmel_port->rs485.delay_rts_after_send);
346 mode |= ATMEL_US_USMODE_RS485;
347 } else {
348 dev_dbg(port->dev, "Setting UART to RS232\n");
349 }
350 UART_PUT_MR(port, mode);
351 }
352
353 /*
354 * Get state of the modem control input lines
355 */
356 static u_int atmel_get_mctrl(struct uart_port *port)
357 {
358 unsigned int status, ret = 0;
359
360 status = UART_GET_CSR(port);
361
362 /*
363 * The control signals are active low.
364 */
365 if (!(status & ATMEL_US_DCD))
366 ret |= TIOCM_CD;
367 if (!(status & ATMEL_US_CTS))
368 ret |= TIOCM_CTS;
369 if (!(status & ATMEL_US_DSR))
370 ret |= TIOCM_DSR;
371 if (!(status & ATMEL_US_RI))
372 ret |= TIOCM_RI;
373
374 return ret;
375 }
376
377 /*
378 * Stop transmitting.
379 */
380 static void atmel_stop_tx(struct uart_port *port)
381 {
382 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
383
384 if (atmel_use_pdc_tx(port)) {
385 /* disable PDC transmit */
386 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
387 }
388 /* Disable interrupts */
389 UART_PUT_IDR(port, atmel_port->tx_done_mask);
390
391 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
392 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
393 atmel_start_rx(port);
394 }
395
396 /*
397 * Start transmitting.
398 */
399 static void atmel_start_tx(struct uart_port *port)
400 {
401 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
402
403 if (atmel_use_pdc_tx(port)) {
404 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
405 /* The transmitter is already running. Yes, we
406 really need this.*/
407 return;
408
409 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
410 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
411 atmel_stop_rx(port);
412
413 /* re-enable PDC transmit */
414 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
415 }
416 /* Enable interrupts */
417 UART_PUT_IER(port, atmel_port->tx_done_mask);
418 }
419
420 /*
421 * start receiving - port is in process of being opened.
422 */
423 static void atmel_start_rx(struct uart_port *port)
424 {
425 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
426
427 UART_PUT_CR(port, ATMEL_US_RXEN);
428
429 if (atmel_use_pdc_rx(port)) {
430 /* enable PDC controller */
431 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
432 port->read_status_mask);
433 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
434 } else {
435 UART_PUT_IER(port, ATMEL_US_RXRDY);
436 }
437 }
438
439 /*
440 * Stop receiving - port is in process of being closed.
441 */
442 static void atmel_stop_rx(struct uart_port *port)
443 {
444 UART_PUT_CR(port, ATMEL_US_RXDIS);
445
446 if (atmel_use_pdc_rx(port)) {
447 /* disable PDC receive */
448 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
449 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
450 port->read_status_mask);
451 } else {
452 UART_PUT_IDR(port, ATMEL_US_RXRDY);
453 }
454 }
455
456 /*
457 * Enable modem status interrupts
458 */
459 static void atmel_enable_ms(struct uart_port *port)
460 {
461 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
462 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
463 }
464
465 /*
466 * Control the transmission of a break signal
467 */
468 static void atmel_break_ctl(struct uart_port *port, int break_state)
469 {
470 if (break_state != 0)
471 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
472 else
473 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
474 }
475
476 /*
477 * Stores the incoming character in the ring buffer
478 */
479 static void
480 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
481 unsigned int ch)
482 {
483 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
484 struct circ_buf *ring = &atmel_port->rx_ring;
485 struct atmel_uart_char *c;
486
487 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
488 /* Buffer overflow, ignore char */
489 return;
490
491 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
492 c->status = status;
493 c->ch = ch;
494
495 /* Make sure the character is stored before we update head. */
496 smp_wmb();
497
498 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
499 }
500
501 /*
502 * Deal with parity, framing and overrun errors.
503 */
504 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
505 {
506 /* clear error */
507 UART_PUT_CR(port, ATMEL_US_RSTSTA);
508
509 if (status & ATMEL_US_RXBRK) {
510 /* ignore side-effect */
511 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
512 port->icount.brk++;
513 }
514 if (status & ATMEL_US_PARE)
515 port->icount.parity++;
516 if (status & ATMEL_US_FRAME)
517 port->icount.frame++;
518 if (status & ATMEL_US_OVRE)
519 port->icount.overrun++;
520 }
521
522 /*
523 * Characters received (called from interrupt handler)
524 */
525 static void atmel_rx_chars(struct uart_port *port)
526 {
527 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
528 unsigned int status, ch;
529
530 status = UART_GET_CSR(port);
531 while (status & ATMEL_US_RXRDY) {
532 ch = UART_GET_CHAR(port);
533
534 /*
535 * note that the error handling code is
536 * out of the main execution path
537 */
538 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
539 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
540 || atmel_port->break_active)) {
541
542 /* clear error */
543 UART_PUT_CR(port, ATMEL_US_RSTSTA);
544
545 if (status & ATMEL_US_RXBRK
546 && !atmel_port->break_active) {
547 atmel_port->break_active = 1;
548 UART_PUT_IER(port, ATMEL_US_RXBRK);
549 } else {
550 /*
551 * This is either the end-of-break
552 * condition or we've received at
553 * least one character without RXBRK
554 * being set. In both cases, the next
555 * RXBRK will indicate start-of-break.
556 */
557 UART_PUT_IDR(port, ATMEL_US_RXBRK);
558 status &= ~ATMEL_US_RXBRK;
559 atmel_port->break_active = 0;
560 }
561 }
562
563 atmel_buffer_rx_char(port, status, ch);
564 status = UART_GET_CSR(port);
565 }
566
567 tasklet_schedule(&atmel_port->tasklet);
568 }
569
570 /*
571 * Transmit characters (called from tasklet with TXRDY interrupt
572 * disabled)
573 */
574 static void atmel_tx_chars(struct uart_port *port)
575 {
576 struct circ_buf *xmit = &port->state->xmit;
577 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
578
579 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
580 UART_PUT_CHAR(port, port->x_char);
581 port->icount.tx++;
582 port->x_char = 0;
583 }
584 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
585 return;
586
587 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
588 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
589 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
590 port->icount.tx++;
591 if (uart_circ_empty(xmit))
592 break;
593 }
594
595 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
596 uart_write_wakeup(port);
597
598 if (!uart_circ_empty(xmit))
599 /* Enable interrupts */
600 UART_PUT_IER(port, atmel_port->tx_done_mask);
601 }
602
603 static void atmel_complete_tx_dma(void *arg)
604 {
605 struct atmel_uart_port *atmel_port = arg;
606 struct uart_port *port = &atmel_port->uart;
607 struct circ_buf *xmit = &port->state->xmit;
608 struct dma_chan *chan = atmel_port->chan_tx;
609 unsigned long flags;
610
611 spin_lock_irqsave(&port->lock, flags);
612
613 if (chan)
614 dmaengine_terminate_all(chan);
615 xmit->tail += sg_dma_len(&atmel_port->sg_tx);
616 xmit->tail &= UART_XMIT_SIZE - 1;
617
618 port->icount.tx += sg_dma_len(&atmel_port->sg_tx);
619
620 spin_lock_irq(&atmel_port->lock_tx);
621 async_tx_ack(atmel_port->desc_tx);
622 atmel_port->cookie_tx = -EINVAL;
623 atmel_port->desc_tx = NULL;
624 spin_unlock_irq(&atmel_port->lock_tx);
625
626 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
627 uart_write_wakeup(port);
628
629 /* Do we really need this? */
630 if (!uart_circ_empty(xmit))
631 tasklet_schedule(&atmel_port->tasklet);
632
633 spin_unlock_irqrestore(&port->lock, flags);
634 }
635
636 static void atmel_release_tx_dma(struct uart_port *port)
637 {
638 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
639 struct dma_chan *chan = atmel_port->chan_tx;
640
641 if (chan) {
642 dmaengine_terminate_all(chan);
643 dma_release_channel(chan);
644 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
645 DMA_MEM_TO_DEV);
646 }
647
648 atmel_port->desc_tx = NULL;
649 atmel_port->chan_tx = NULL;
650 atmel_port->cookie_tx = -EINVAL;
651 }
652
653 /*
654 * Called from tasklet with TXRDY interrupt is disabled.
655 */
656 static void atmel_tx_dma(struct uart_port *port)
657 {
658 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
659 struct circ_buf *xmit = &port->state->xmit;
660 struct dma_chan *chan = atmel_port->chan_tx;
661 struct dma_async_tx_descriptor *desc;
662 struct scatterlist *sg = &atmel_port->sg_tx;
663
664 /* Make sure we have an idle channel */
665 if (atmel_port->desc_tx != NULL)
666 return;
667
668 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
669 /*
670 * DMA is idle now.
671 * Port xmit buffer is already mapped,
672 * and it is one page... Just adjust
673 * offsets and lengths. Since it is a circular buffer,
674 * we have to transmit till the end, and then the rest.
675 * Take the port lock to get a
676 * consistent xmit buffer state.
677 */
678 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
679 sg_dma_address(sg) = (sg_dma_address(sg) &
680 ~(UART_XMIT_SIZE - 1))
681 + sg->offset;
682 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head,
683 xmit->tail,
684 UART_XMIT_SIZE);
685 BUG_ON(!sg_dma_len(sg));
686
687 desc = dmaengine_prep_slave_sg(chan,
688 sg,
689 1,
690 DMA_MEM_TO_DEV,
691 DMA_PREP_INTERRUPT |
692 DMA_CTRL_ACK);
693 if (!desc) {
694 dev_err(port->dev, "Failed to send via dma!\n");
695 return;
696 }
697
698 dma_sync_sg_for_device(port->dev, sg, 1, DMA_MEM_TO_DEV);
699
700 atmel_port->desc_tx = desc;
701 desc->callback = atmel_complete_tx_dma;
702 desc->callback_param = atmel_port;
703 atmel_port->cookie_tx = dmaengine_submit(desc);
704
705 } else {
706 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
707 /* DMA done, stop TX, start RX for RS485 */
708 atmel_start_rx(port);
709 }
710 }
711
712 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
713 uart_write_wakeup(port);
714 }
715
716 static int atmel_prepare_tx_dma(struct uart_port *port)
717 {
718 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
719 dma_cap_mask_t mask;
720 struct dma_slave_config config;
721 int ret, nent;
722
723 dma_cap_zero(mask);
724 dma_cap_set(DMA_SLAVE, mask);
725
726 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
727 if (atmel_port->chan_tx == NULL)
728 goto chan_err;
729 dev_info(port->dev, "using %s for tx DMA transfers\n",
730 dma_chan_name(atmel_port->chan_tx));
731
732 spin_lock_init(&atmel_port->lock_tx);
733 sg_init_table(&atmel_port->sg_tx, 1);
734 /* UART circular tx buffer is an aligned page. */
735 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
736 sg_set_page(&atmel_port->sg_tx,
737 virt_to_page(port->state->xmit.buf),
738 UART_XMIT_SIZE,
739 (int)port->state->xmit.buf & ~PAGE_MASK);
740 nent = dma_map_sg(port->dev,
741 &atmel_port->sg_tx,
742 1,
743 DMA_MEM_TO_DEV);
744
745 if (!nent) {
746 dev_dbg(port->dev, "need to release resource of dma\n");
747 goto chan_err;
748 } else {
749 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
750 sg_dma_len(&atmel_port->sg_tx),
751 port->state->xmit.buf,
752 sg_dma_address(&atmel_port->sg_tx));
753 }
754
755 /* Configure the slave DMA */
756 memset(&config, 0, sizeof(config));
757 config.direction = DMA_MEM_TO_DEV;
758 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
759 config.dst_addr = port->mapbase + ATMEL_US_THR;
760
761 ret = dmaengine_device_control(atmel_port->chan_tx,
762 DMA_SLAVE_CONFIG,
763 (unsigned long)&config);
764 if (ret) {
765 dev_err(port->dev, "DMA tx slave configuration failed\n");
766 goto chan_err;
767 }
768
769 return 0;
770
771 chan_err:
772 dev_err(port->dev, "TX channel not available, switch to pio\n");
773 atmel_port->use_dma_tx = 0;
774 if (atmel_port->chan_tx)
775 atmel_release_tx_dma(port);
776 return -EINVAL;
777 }
778
779 static void atmel_flip_buffer_rx_dma(struct uart_port *port,
780 char *buf, size_t count)
781 {
782 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
783 struct tty_port *tport = &port->state->port;
784
785 dma_sync_sg_for_cpu(port->dev,
786 &atmel_port->sg_rx,
787 1,
788 DMA_DEV_TO_MEM);
789
790 tty_insert_flip_string(tport, buf, count);
791
792 dma_sync_sg_for_device(port->dev,
793 &atmel_port->sg_rx,
794 1,
795 DMA_DEV_TO_MEM);
796 /*
797 * Drop the lock here since it might end up calling
798 * uart_start(), which takes the lock.
799 */
800 spin_unlock(&port->lock);
801 tty_flip_buffer_push(tport);
802 spin_lock(&port->lock);
803 }
804
805 static void atmel_complete_rx_dma(void *arg)
806 {
807 struct uart_port *port = arg;
808 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
809
810 tasklet_schedule(&atmel_port->tasklet);
811 }
812
813 static void atmel_release_rx_dma(struct uart_port *port)
814 {
815 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
816 struct dma_chan *chan = atmel_port->chan_rx;
817
818 if (chan) {
819 dmaengine_terminate_all(chan);
820 dma_release_channel(chan);
821 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
822 DMA_DEV_TO_MEM);
823 }
824
825 atmel_port->desc_rx = NULL;
826 atmel_port->chan_rx = NULL;
827 atmel_port->cookie_rx = -EINVAL;
828 }
829
830 static void atmel_rx_from_dma(struct uart_port *port)
831 {
832 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
833 struct circ_buf *ring = &atmel_port->rx_ring;
834 struct dma_chan *chan = atmel_port->chan_rx;
835 struct dma_tx_state state;
836 enum dma_status dmastat;
837 size_t pending, count;
838
839
840 /* Reset the UART timeout early so that we don't miss one */
841 UART_PUT_CR(port, ATMEL_US_STTTO);
842 dmastat = dmaengine_tx_status(chan,
843 atmel_port->cookie_rx,
844 &state);
845 /* Restart a new tasklet if DMA status is error */
846 if (dmastat == DMA_ERROR) {
847 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
848 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
849 tasklet_schedule(&atmel_port->tasklet);
850 return;
851 }
852 /* current transfer size should no larger than dma buffer */
853 pending = sg_dma_len(&atmel_port->sg_rx) - state.residue;
854 BUG_ON(pending > sg_dma_len(&atmel_port->sg_rx));
855
856 /*
857 * This will take the chars we have so far,
858 * ring->head will record the transfer size, only new bytes come
859 * will insert into the framework.
860 */
861 if (pending > ring->head) {
862 count = pending - ring->head;
863
864 atmel_flip_buffer_rx_dma(port, ring->buf + ring->head, count);
865
866 ring->head += count;
867 if (ring->head == sg_dma_len(&atmel_port->sg_rx))
868 ring->head = 0;
869
870 port->icount.rx += count;
871 }
872
873 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
874 }
875
876 static int atmel_prepare_rx_dma(struct uart_port *port)
877 {
878 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
879 struct dma_async_tx_descriptor *desc;
880 dma_cap_mask_t mask;
881 struct dma_slave_config config;
882 struct circ_buf *ring;
883 int ret, nent;
884
885 ring = &atmel_port->rx_ring;
886
887 dma_cap_zero(mask);
888 dma_cap_set(DMA_CYCLIC, mask);
889
890 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
891 if (atmel_port->chan_rx == NULL)
892 goto chan_err;
893 dev_info(port->dev, "using %s for rx DMA transfers\n",
894 dma_chan_name(atmel_port->chan_rx));
895
896 spin_lock_init(&atmel_port->lock_rx);
897 sg_init_table(&atmel_port->sg_rx, 1);
898 /* UART circular rx buffer is an aligned page. */
899 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
900 sg_set_page(&atmel_port->sg_rx,
901 virt_to_page(ring->buf),
902 ATMEL_SERIAL_RINGSIZE,
903 (int)ring->buf & ~PAGE_MASK);
904 nent = dma_map_sg(port->dev,
905 &atmel_port->sg_rx,
906 1,
907 DMA_DEV_TO_MEM);
908
909 if (!nent) {
910 dev_dbg(port->dev, "need to release resource of dma\n");
911 goto chan_err;
912 } else {
913 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
914 sg_dma_len(&atmel_port->sg_rx),
915 ring->buf,
916 sg_dma_address(&atmel_port->sg_rx));
917 }
918
919 /* Configure the slave DMA */
920 memset(&config, 0, sizeof(config));
921 config.direction = DMA_DEV_TO_MEM;
922 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
923 config.src_addr = port->mapbase + ATMEL_US_RHR;
924
925 ret = dmaengine_device_control(atmel_port->chan_rx,
926 DMA_SLAVE_CONFIG,
927 (unsigned long)&config);
928 if (ret) {
929 dev_err(port->dev, "DMA rx slave configuration failed\n");
930 goto chan_err;
931 }
932 /*
933 * Prepare a cyclic dma transfer, assign 2 descriptors,
934 * each one is half ring buffer size
935 */
936 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
937 sg_dma_address(&atmel_port->sg_rx),
938 sg_dma_len(&atmel_port->sg_rx),
939 sg_dma_len(&atmel_port->sg_rx)/2,
940 DMA_DEV_TO_MEM,
941 DMA_PREP_INTERRUPT);
942 desc->callback = atmel_complete_rx_dma;
943 desc->callback_param = port;
944 atmel_port->desc_rx = desc;
945 atmel_port->cookie_rx = dmaengine_submit(desc);
946
947 return 0;
948
949 chan_err:
950 dev_err(port->dev, "RX channel not available, switch to pio\n");
951 atmel_port->use_dma_rx = 0;
952 if (atmel_port->chan_rx)
953 atmel_release_rx_dma(port);
954 return -EINVAL;
955 }
956
957 static void atmel_uart_timer_callback(unsigned long data)
958 {
959 struct uart_port *port = (void *)data;
960 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
961
962 tasklet_schedule(&atmel_port->tasklet);
963 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
964 }
965
966 /*
967 * receive interrupt handler.
968 */
969 static void
970 atmel_handle_receive(struct uart_port *port, unsigned int pending)
971 {
972 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
973
974 if (atmel_use_pdc_rx(port)) {
975 /*
976 * PDC receive. Just schedule the tasklet and let it
977 * figure out the details.
978 *
979 * TODO: We're not handling error flags correctly at
980 * the moment.
981 */
982 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
983 UART_PUT_IDR(port, (ATMEL_US_ENDRX
984 | ATMEL_US_TIMEOUT));
985 tasklet_schedule(&atmel_port->tasklet);
986 }
987
988 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
989 ATMEL_US_FRAME | ATMEL_US_PARE))
990 atmel_pdc_rxerr(port, pending);
991 }
992
993 if (atmel_use_dma_rx(port)) {
994 if (pending & ATMEL_US_TIMEOUT) {
995 UART_PUT_IDR(port, ATMEL_US_TIMEOUT);
996 tasklet_schedule(&atmel_port->tasklet);
997 }
998 }
999
1000 /* Interrupt receive */
1001 if (pending & ATMEL_US_RXRDY)
1002 atmel_rx_chars(port);
1003 else if (pending & ATMEL_US_RXBRK) {
1004 /*
1005 * End of break detected. If it came along with a
1006 * character, atmel_rx_chars will handle it.
1007 */
1008 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1009 UART_PUT_IDR(port, ATMEL_US_RXBRK);
1010 atmel_port->break_active = 0;
1011 }
1012 }
1013
1014 /*
1015 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1016 */
1017 static void
1018 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1019 {
1020 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1021
1022 if (pending & atmel_port->tx_done_mask) {
1023 /* Either PDC or interrupt transmission */
1024 UART_PUT_IDR(port, atmel_port->tx_done_mask);
1025 tasklet_schedule(&atmel_port->tasklet);
1026 }
1027 }
1028
1029 /*
1030 * status flags interrupt handler.
1031 */
1032 static void
1033 atmel_handle_status(struct uart_port *port, unsigned int pending,
1034 unsigned int status)
1035 {
1036 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1037
1038 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1039 | ATMEL_US_CTSIC)) {
1040 atmel_port->irq_status = status;
1041 tasklet_schedule(&atmel_port->tasklet);
1042 }
1043 }
1044
1045 /*
1046 * Interrupt handler
1047 */
1048 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1049 {
1050 struct uart_port *port = dev_id;
1051 unsigned int status, pending, pass_counter = 0;
1052
1053 do {
1054 status = UART_GET_CSR(port);
1055 pending = status & UART_GET_IMR(port);
1056 if (!pending)
1057 break;
1058
1059 atmel_handle_receive(port, pending);
1060 atmel_handle_status(port, pending, status);
1061 atmel_handle_transmit(port, pending);
1062 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1063
1064 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1065 }
1066
1067 static void atmel_release_tx_pdc(struct uart_port *port)
1068 {
1069 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1070 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1071
1072 dma_unmap_single(port->dev,
1073 pdc->dma_addr,
1074 pdc->dma_size,
1075 DMA_TO_DEVICE);
1076 }
1077
1078 /*
1079 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1080 */
1081 static void atmel_tx_pdc(struct uart_port *port)
1082 {
1083 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1084 struct circ_buf *xmit = &port->state->xmit;
1085 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1086 int count;
1087
1088 /* nothing left to transmit? */
1089 if (UART_GET_TCR(port))
1090 return;
1091
1092 xmit->tail += pdc->ofs;
1093 xmit->tail &= UART_XMIT_SIZE - 1;
1094
1095 port->icount.tx += pdc->ofs;
1096 pdc->ofs = 0;
1097
1098 /* more to transmit - setup next transfer */
1099
1100 /* disable PDC transmit */
1101 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1102
1103 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1104 dma_sync_single_for_device(port->dev,
1105 pdc->dma_addr,
1106 pdc->dma_size,
1107 DMA_TO_DEVICE);
1108
1109 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1110 pdc->ofs = count;
1111
1112 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
1113 UART_PUT_TCR(port, count);
1114 /* re-enable PDC transmit */
1115 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1116 /* Enable interrupts */
1117 UART_PUT_IER(port, atmel_port->tx_done_mask);
1118 } else {
1119 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
1120 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1121 /* DMA done, stop TX, start RX for RS485 */
1122 atmel_start_rx(port);
1123 }
1124 }
1125
1126 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1127 uart_write_wakeup(port);
1128 }
1129
1130 static int atmel_prepare_tx_pdc(struct uart_port *port)
1131 {
1132 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1133 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1134 struct circ_buf *xmit = &port->state->xmit;
1135
1136 pdc->buf = xmit->buf;
1137 pdc->dma_addr = dma_map_single(port->dev,
1138 pdc->buf,
1139 UART_XMIT_SIZE,
1140 DMA_TO_DEVICE);
1141 pdc->dma_size = UART_XMIT_SIZE;
1142 pdc->ofs = 0;
1143
1144 return 0;
1145 }
1146
1147 static void atmel_rx_from_ring(struct uart_port *port)
1148 {
1149 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1150 struct circ_buf *ring = &atmel_port->rx_ring;
1151 unsigned int flg;
1152 unsigned int status;
1153
1154 while (ring->head != ring->tail) {
1155 struct atmel_uart_char c;
1156
1157 /* Make sure c is loaded after head. */
1158 smp_rmb();
1159
1160 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1161
1162 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1163
1164 port->icount.rx++;
1165 status = c.status;
1166 flg = TTY_NORMAL;
1167
1168 /*
1169 * note that the error handling code is
1170 * out of the main execution path
1171 */
1172 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1173 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1174 if (status & ATMEL_US_RXBRK) {
1175 /* ignore side-effect */
1176 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1177
1178 port->icount.brk++;
1179 if (uart_handle_break(port))
1180 continue;
1181 }
1182 if (status & ATMEL_US_PARE)
1183 port->icount.parity++;
1184 if (status & ATMEL_US_FRAME)
1185 port->icount.frame++;
1186 if (status & ATMEL_US_OVRE)
1187 port->icount.overrun++;
1188
1189 status &= port->read_status_mask;
1190
1191 if (status & ATMEL_US_RXBRK)
1192 flg = TTY_BREAK;
1193 else if (status & ATMEL_US_PARE)
1194 flg = TTY_PARITY;
1195 else if (status & ATMEL_US_FRAME)
1196 flg = TTY_FRAME;
1197 }
1198
1199
1200 if (uart_handle_sysrq_char(port, c.ch))
1201 continue;
1202
1203 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1204 }
1205
1206 /*
1207 * Drop the lock here since it might end up calling
1208 * uart_start(), which takes the lock.
1209 */
1210 spin_unlock(&port->lock);
1211 tty_flip_buffer_push(&port->state->port);
1212 spin_lock(&port->lock);
1213 }
1214
1215 static void atmel_release_rx_pdc(struct uart_port *port)
1216 {
1217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1218 int i;
1219
1220 for (i = 0; i < 2; i++) {
1221 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1222
1223 dma_unmap_single(port->dev,
1224 pdc->dma_addr,
1225 pdc->dma_size,
1226 DMA_FROM_DEVICE);
1227 kfree(pdc->buf);
1228 }
1229 }
1230
1231 static void atmel_rx_from_pdc(struct uart_port *port)
1232 {
1233 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1234 struct tty_port *tport = &port->state->port;
1235 struct atmel_dma_buffer *pdc;
1236 int rx_idx = atmel_port->pdc_rx_idx;
1237 unsigned int head;
1238 unsigned int tail;
1239 unsigned int count;
1240
1241 do {
1242 /* Reset the UART timeout early so that we don't miss one */
1243 UART_PUT_CR(port, ATMEL_US_STTTO);
1244
1245 pdc = &atmel_port->pdc_rx[rx_idx];
1246 head = UART_GET_RPR(port) - pdc->dma_addr;
1247 tail = pdc->ofs;
1248
1249 /* If the PDC has switched buffers, RPR won't contain
1250 * any address within the current buffer. Since head
1251 * is unsigned, we just need a one-way comparison to
1252 * find out.
1253 *
1254 * In this case, we just need to consume the entire
1255 * buffer and resubmit it for DMA. This will clear the
1256 * ENDRX bit as well, so that we can safely re-enable
1257 * all interrupts below.
1258 */
1259 head = min(head, pdc->dma_size);
1260
1261 if (likely(head != tail)) {
1262 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1263 pdc->dma_size, DMA_FROM_DEVICE);
1264
1265 /*
1266 * head will only wrap around when we recycle
1267 * the DMA buffer, and when that happens, we
1268 * explicitly set tail to 0. So head will
1269 * always be greater than tail.
1270 */
1271 count = head - tail;
1272
1273 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1274 count);
1275
1276 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1277 pdc->dma_size, DMA_FROM_DEVICE);
1278
1279 port->icount.rx += count;
1280 pdc->ofs = head;
1281 }
1282
1283 /*
1284 * If the current buffer is full, we need to check if
1285 * the next one contains any additional data.
1286 */
1287 if (head >= pdc->dma_size) {
1288 pdc->ofs = 0;
1289 UART_PUT_RNPR(port, pdc->dma_addr);
1290 UART_PUT_RNCR(port, pdc->dma_size);
1291
1292 rx_idx = !rx_idx;
1293 atmel_port->pdc_rx_idx = rx_idx;
1294 }
1295 } while (head >= pdc->dma_size);
1296
1297 /*
1298 * Drop the lock here since it might end up calling
1299 * uart_start(), which takes the lock.
1300 */
1301 spin_unlock(&port->lock);
1302 tty_flip_buffer_push(tport);
1303 spin_lock(&port->lock);
1304
1305 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1306 }
1307
1308 static int atmel_prepare_rx_pdc(struct uart_port *port)
1309 {
1310 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1311 int i;
1312
1313 for (i = 0; i < 2; i++) {
1314 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1315
1316 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1317 if (pdc->buf == NULL) {
1318 if (i != 0) {
1319 dma_unmap_single(port->dev,
1320 atmel_port->pdc_rx[0].dma_addr,
1321 PDC_BUFFER_SIZE,
1322 DMA_FROM_DEVICE);
1323 kfree(atmel_port->pdc_rx[0].buf);
1324 }
1325 atmel_port->use_pdc_rx = 0;
1326 return -ENOMEM;
1327 }
1328 pdc->dma_addr = dma_map_single(port->dev,
1329 pdc->buf,
1330 PDC_BUFFER_SIZE,
1331 DMA_FROM_DEVICE);
1332 pdc->dma_size = PDC_BUFFER_SIZE;
1333 pdc->ofs = 0;
1334 }
1335
1336 atmel_port->pdc_rx_idx = 0;
1337
1338 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
1339 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
1340
1341 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
1342 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
1343
1344 return 0;
1345 }
1346
1347 /*
1348 * tasklet handling tty stuff outside the interrupt handler.
1349 */
1350 static void atmel_tasklet_func(unsigned long data)
1351 {
1352 struct uart_port *port = (struct uart_port *)data;
1353 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1354 unsigned int status;
1355 unsigned int status_change;
1356
1357 /* The interrupt handler does not take the lock */
1358 spin_lock(&port->lock);
1359
1360 atmel_port->schedule_tx(port);
1361
1362 status = atmel_port->irq_status;
1363 status_change = status ^ atmel_port->irq_status_prev;
1364
1365 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1366 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1367 /* TODO: All reads to CSR will clear these interrupts! */
1368 if (status_change & ATMEL_US_RI)
1369 port->icount.rng++;
1370 if (status_change & ATMEL_US_DSR)
1371 port->icount.dsr++;
1372 if (status_change & ATMEL_US_DCD)
1373 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1374 if (status_change & ATMEL_US_CTS)
1375 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1376
1377 wake_up_interruptible(&port->state->port.delta_msr_wait);
1378
1379 atmel_port->irq_status_prev = status;
1380 }
1381
1382 atmel_port->schedule_rx(port);
1383
1384 spin_unlock(&port->lock);
1385 }
1386
1387 static int atmel_init_property(struct atmel_uart_port *atmel_port,
1388 struct platform_device *pdev)
1389 {
1390 struct device_node *np = pdev->dev.of_node;
1391 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1392
1393 if (np) {
1394 /* DMA/PDC usage specification */
1395 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1396 if (of_get_property(np, "dmas", NULL)) {
1397 atmel_port->use_dma_rx = true;
1398 atmel_port->use_pdc_rx = false;
1399 } else {
1400 atmel_port->use_dma_rx = false;
1401 atmel_port->use_pdc_rx = true;
1402 }
1403 } else {
1404 atmel_port->use_dma_rx = false;
1405 atmel_port->use_pdc_rx = false;
1406 }
1407
1408 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1409 if (of_get_property(np, "dmas", NULL)) {
1410 atmel_port->use_dma_tx = true;
1411 atmel_port->use_pdc_tx = false;
1412 } else {
1413 atmel_port->use_dma_tx = false;
1414 atmel_port->use_pdc_tx = true;
1415 }
1416 } else {
1417 atmel_port->use_dma_tx = false;
1418 atmel_port->use_pdc_tx = false;
1419 }
1420
1421 } else {
1422 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1423 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1424 atmel_port->use_dma_rx = false;
1425 atmel_port->use_dma_tx = false;
1426 }
1427
1428 return 0;
1429 }
1430
1431 static void atmel_init_rs485(struct atmel_uart_port *atmel_port,
1432 struct platform_device *pdev)
1433 {
1434 struct device_node *np = pdev->dev.of_node;
1435 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1436
1437 if (np) {
1438 u32 rs485_delay[2];
1439 /* rs485 properties */
1440 if (of_property_read_u32_array(np, "rs485-rts-delay",
1441 rs485_delay, 2) == 0) {
1442 struct serial_rs485 *rs485conf = &atmel_port->rs485;
1443
1444 rs485conf->delay_rts_before_send = rs485_delay[0];
1445 rs485conf->delay_rts_after_send = rs485_delay[1];
1446 rs485conf->flags = 0;
1447
1448 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1449 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1450
1451 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1452 NULL))
1453 rs485conf->flags |= SER_RS485_ENABLED;
1454 }
1455 } else {
1456 atmel_port->rs485 = pdata->rs485;
1457 }
1458
1459 }
1460
1461 static void atmel_set_ops(struct uart_port *port)
1462 {
1463 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1464
1465 if (atmel_use_dma_rx(port)) {
1466 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1467 atmel_port->schedule_rx = &atmel_rx_from_dma;
1468 atmel_port->release_rx = &atmel_release_rx_dma;
1469 } else if (atmel_use_pdc_rx(port)) {
1470 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1471 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1472 atmel_port->release_rx = &atmel_release_rx_pdc;
1473 } else {
1474 atmel_port->prepare_rx = NULL;
1475 atmel_port->schedule_rx = &atmel_rx_from_ring;
1476 atmel_port->release_rx = NULL;
1477 }
1478
1479 if (atmel_use_dma_tx(port)) {
1480 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1481 atmel_port->schedule_tx = &atmel_tx_dma;
1482 atmel_port->release_tx = &atmel_release_tx_dma;
1483 } else if (atmel_use_pdc_tx(port)) {
1484 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1485 atmel_port->schedule_tx = &atmel_tx_pdc;
1486 atmel_port->release_tx = &atmel_release_tx_pdc;
1487 } else {
1488 atmel_port->prepare_tx = NULL;
1489 atmel_port->schedule_tx = &atmel_tx_chars;
1490 atmel_port->release_tx = NULL;
1491 }
1492 }
1493
1494 /*
1495 * Get ip name usart or uart
1496 */
1497 static void atmel_get_ip_name(struct uart_port *port)
1498 {
1499 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1500 int name = UART_GET_IP_NAME(port);
1501 u32 version;
1502 int usart, uart;
1503 /* usart and uart ascii */
1504 usart = 0x55534152;
1505 uart = 0x44424755;
1506
1507 atmel_port->is_usart = false;
1508
1509 if (name == usart) {
1510 dev_dbg(port->dev, "This is usart\n");
1511 atmel_port->is_usart = true;
1512 } else if (name == uart) {
1513 dev_dbg(port->dev, "This is uart\n");
1514 atmel_port->is_usart = false;
1515 } else {
1516 /* fallback for older SoCs: use version field */
1517 version = UART_GET_IP_VERSION(port);
1518 switch (version) {
1519 case 0x302:
1520 case 0x10213:
1521 dev_dbg(port->dev, "This version is usart\n");
1522 atmel_port->is_usart = true;
1523 break;
1524 case 0x203:
1525 case 0x10202:
1526 dev_dbg(port->dev, "This version is uart\n");
1527 atmel_port->is_usart = false;
1528 break;
1529 default:
1530 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1531 }
1532 }
1533 }
1534
1535 /*
1536 * Perform initialization and enable port for reception
1537 */
1538 static int atmel_startup(struct uart_port *port)
1539 {
1540 struct platform_device *pdev = to_platform_device(port->dev);
1541 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1542 struct tty_struct *tty = port->state->port.tty;
1543 int retval;
1544
1545 /*
1546 * Ensure that no interrupts are enabled otherwise when
1547 * request_irq() is called we could get stuck trying to
1548 * handle an unexpected interrupt
1549 */
1550 UART_PUT_IDR(port, -1);
1551
1552 /*
1553 * Allocate the IRQ
1554 */
1555 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
1556 tty ? tty->name : "atmel_serial", port);
1557 if (retval) {
1558 printk("atmel_serial: atmel_startup - Can't get irq\n");
1559 return retval;
1560 }
1561
1562 /*
1563 * Initialize DMA (if necessary)
1564 */
1565 atmel_init_property(atmel_port, pdev);
1566
1567 if (atmel_port->prepare_rx) {
1568 retval = atmel_port->prepare_rx(port);
1569 if (retval < 0)
1570 atmel_set_ops(port);
1571 }
1572
1573 if (atmel_port->prepare_tx) {
1574 retval = atmel_port->prepare_tx(port);
1575 if (retval < 0)
1576 atmel_set_ops(port);
1577 }
1578 /*
1579 * If there is a specific "open" function (to register
1580 * control line interrupts)
1581 */
1582 if (atmel_open_hook) {
1583 retval = atmel_open_hook(port);
1584 if (retval) {
1585 free_irq(port->irq, port);
1586 return retval;
1587 }
1588 }
1589
1590 /* Save current CSR for comparison in atmel_tasklet_func() */
1591 atmel_port->irq_status_prev = UART_GET_CSR(port);
1592 atmel_port->irq_status = atmel_port->irq_status_prev;
1593
1594 /*
1595 * Finally, enable the serial port
1596 */
1597 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1598 /* enable xmit & rcvr */
1599 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1600
1601 setup_timer(&atmel_port->uart_timer,
1602 atmel_uart_timer_callback,
1603 (unsigned long)port);
1604
1605 if (atmel_use_pdc_rx(port)) {
1606 /* set UART timeout */
1607 if (!atmel_port->is_usart) {
1608 mod_timer(&atmel_port->uart_timer,
1609 jiffies + uart_poll_timeout(port));
1610 /* set USART timeout */
1611 } else {
1612 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1613 UART_PUT_CR(port, ATMEL_US_STTTO);
1614
1615 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1616 }
1617 /* enable PDC controller */
1618 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
1619 } else if (atmel_use_dma_rx(port)) {
1620 /* set UART timeout */
1621 if (!atmel_port->is_usart) {
1622 mod_timer(&atmel_port->uart_timer,
1623 jiffies + uart_poll_timeout(port));
1624 /* set USART timeout */
1625 } else {
1626 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1627 UART_PUT_CR(port, ATMEL_US_STTTO);
1628
1629 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1630 }
1631 } else {
1632 /* enable receive only */
1633 UART_PUT_IER(port, ATMEL_US_RXRDY);
1634 }
1635
1636 return 0;
1637 }
1638
1639 /*
1640 * Disable the port
1641 */
1642 static void atmel_shutdown(struct uart_port *port)
1643 {
1644 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1645
1646 /*
1647 * Prevent any tasklets being scheduled during
1648 * cleanup
1649 */
1650 del_timer_sync(&atmel_port->uart_timer);
1651
1652 /*
1653 * Clear out any scheduled tasklets before
1654 * we destroy the buffers
1655 */
1656 tasklet_kill(&atmel_port->tasklet);
1657
1658 /*
1659 * Ensure everything is stopped and
1660 * disable all interrupts, port and break condition.
1661 */
1662 atmel_stop_rx(port);
1663 atmel_stop_tx(port);
1664
1665 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1666 UART_PUT_IDR(port, -1);
1667
1668
1669 /*
1670 * Shut-down the DMA.
1671 */
1672 if (atmel_port->release_rx)
1673 atmel_port->release_rx(port);
1674 if (atmel_port->release_tx)
1675 atmel_port->release_tx(port);
1676
1677 /*
1678 * Reset ring buffer pointers
1679 */
1680 atmel_port->rx_ring.head = 0;
1681 atmel_port->rx_ring.tail = 0;
1682
1683 /*
1684 * Free the interrupt
1685 */
1686 free_irq(port->irq, port);
1687
1688 /*
1689 * If there is a specific "close" function (to unregister
1690 * control line interrupts)
1691 */
1692 if (atmel_close_hook)
1693 atmel_close_hook(port);
1694 }
1695
1696 /*
1697 * Flush any TX data submitted for DMA. Called when the TX circular
1698 * buffer is reset.
1699 */
1700 static void atmel_flush_buffer(struct uart_port *port)
1701 {
1702 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1703
1704 if (atmel_use_pdc_tx(port)) {
1705 UART_PUT_TCR(port, 0);
1706 atmel_port->pdc_tx.ofs = 0;
1707 }
1708 }
1709
1710 /*
1711 * Power / Clock management.
1712 */
1713 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1714 unsigned int oldstate)
1715 {
1716 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1717
1718 switch (state) {
1719 case 0:
1720 /*
1721 * Enable the peripheral clock for this serial port.
1722 * This is called on uart_open() or a resume event.
1723 */
1724 clk_prepare_enable(atmel_port->clk);
1725
1726 /* re-enable interrupts if we disabled some on suspend */
1727 UART_PUT_IER(port, atmel_port->backup_imr);
1728 break;
1729 case 3:
1730 /* Back up the interrupt mask and disable all interrupts */
1731 atmel_port->backup_imr = UART_GET_IMR(port);
1732 UART_PUT_IDR(port, -1);
1733
1734 /*
1735 * Disable the peripheral clock for this serial port.
1736 * This is called on uart_close() or a suspend event.
1737 */
1738 clk_disable_unprepare(atmel_port->clk);
1739 break;
1740 default:
1741 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1742 }
1743 }
1744
1745 /*
1746 * Change the port parameters
1747 */
1748 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1749 struct ktermios *old)
1750 {
1751 unsigned long flags;
1752 unsigned int mode, imr, quot, baud;
1753 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1754
1755 /* Get current mode register */
1756 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
1757 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1758 | ATMEL_US_USMODE);
1759
1760 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1761 quot = uart_get_divisor(port, baud);
1762
1763 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
1764 quot /= 8;
1765 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1766 }
1767
1768 /* byte size */
1769 switch (termios->c_cflag & CSIZE) {
1770 case CS5:
1771 mode |= ATMEL_US_CHRL_5;
1772 break;
1773 case CS6:
1774 mode |= ATMEL_US_CHRL_6;
1775 break;
1776 case CS7:
1777 mode |= ATMEL_US_CHRL_7;
1778 break;
1779 default:
1780 mode |= ATMEL_US_CHRL_8;
1781 break;
1782 }
1783
1784 /* stop bits */
1785 if (termios->c_cflag & CSTOPB)
1786 mode |= ATMEL_US_NBSTOP_2;
1787
1788 /* parity */
1789 if (termios->c_cflag & PARENB) {
1790 /* Mark or Space parity */
1791 if (termios->c_cflag & CMSPAR) {
1792 if (termios->c_cflag & PARODD)
1793 mode |= ATMEL_US_PAR_MARK;
1794 else
1795 mode |= ATMEL_US_PAR_SPACE;
1796 } else if (termios->c_cflag & PARODD)
1797 mode |= ATMEL_US_PAR_ODD;
1798 else
1799 mode |= ATMEL_US_PAR_EVEN;
1800 } else
1801 mode |= ATMEL_US_PAR_NONE;
1802
1803 /* hardware handshake (RTS/CTS) */
1804 if (termios->c_cflag & CRTSCTS)
1805 mode |= ATMEL_US_USMODE_HWHS;
1806 else
1807 mode |= ATMEL_US_USMODE_NORMAL;
1808
1809 spin_lock_irqsave(&port->lock, flags);
1810
1811 port->read_status_mask = ATMEL_US_OVRE;
1812 if (termios->c_iflag & INPCK)
1813 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1814 if (termios->c_iflag & (BRKINT | PARMRK))
1815 port->read_status_mask |= ATMEL_US_RXBRK;
1816
1817 if (atmel_use_pdc_rx(port))
1818 /* need to enable error interrupts */
1819 UART_PUT_IER(port, port->read_status_mask);
1820
1821 /*
1822 * Characters to ignore
1823 */
1824 port->ignore_status_mask = 0;
1825 if (termios->c_iflag & IGNPAR)
1826 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1827 if (termios->c_iflag & IGNBRK) {
1828 port->ignore_status_mask |= ATMEL_US_RXBRK;
1829 /*
1830 * If we're ignoring parity and break indicators,
1831 * ignore overruns too (for real raw support).
1832 */
1833 if (termios->c_iflag & IGNPAR)
1834 port->ignore_status_mask |= ATMEL_US_OVRE;
1835 }
1836 /* TODO: Ignore all characters if CREAD is set.*/
1837
1838 /* update the per-port timeout */
1839 uart_update_timeout(port, termios->c_cflag, baud);
1840
1841 /*
1842 * save/disable interrupts. The tty layer will ensure that the
1843 * transmitter is empty if requested by the caller, so there's
1844 * no need to wait for it here.
1845 */
1846 imr = UART_GET_IMR(port);
1847 UART_PUT_IDR(port, -1);
1848
1849 /* disable receiver and transmitter */
1850 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1851
1852 /* Resetting serial mode to RS232 (0x0) */
1853 mode &= ~ATMEL_US_USMODE;
1854
1855 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
1856 dev_dbg(port->dev, "Setting UART to RS485\n");
1857 if ((atmel_port->rs485.delay_rts_after_send) > 0)
1858 UART_PUT_TTGR(port,
1859 atmel_port->rs485.delay_rts_after_send);
1860 mode |= ATMEL_US_USMODE_RS485;
1861 } else {
1862 dev_dbg(port->dev, "Setting UART to RS232\n");
1863 }
1864
1865 /* set the parity, stop bits and data size */
1866 UART_PUT_MR(port, mode);
1867
1868 /* set the baud rate */
1869 UART_PUT_BRGR(port, quot);
1870 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1871 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1872
1873 /* restore interrupts */
1874 UART_PUT_IER(port, imr);
1875
1876 /* CTS flow-control and modem-status interrupts */
1877 if (UART_ENABLE_MS(port, termios->c_cflag))
1878 port->ops->enable_ms(port);
1879
1880 spin_unlock_irqrestore(&port->lock, flags);
1881 }
1882
1883 static void atmel_set_ldisc(struct uart_port *port, int new)
1884 {
1885 if (new == N_PPS) {
1886 port->flags |= UPF_HARDPPS_CD;
1887 atmel_enable_ms(port);
1888 } else {
1889 port->flags &= ~UPF_HARDPPS_CD;
1890 }
1891 }
1892
1893 /*
1894 * Return string describing the specified port
1895 */
1896 static const char *atmel_type(struct uart_port *port)
1897 {
1898 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1899 }
1900
1901 /*
1902 * Release the memory region(s) being used by 'port'.
1903 */
1904 static void atmel_release_port(struct uart_port *port)
1905 {
1906 struct platform_device *pdev = to_platform_device(port->dev);
1907 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1908
1909 release_mem_region(port->mapbase, size);
1910
1911 if (port->flags & UPF_IOREMAP) {
1912 iounmap(port->membase);
1913 port->membase = NULL;
1914 }
1915 }
1916
1917 /*
1918 * Request the memory region(s) being used by 'port'.
1919 */
1920 static int atmel_request_port(struct uart_port *port)
1921 {
1922 struct platform_device *pdev = to_platform_device(port->dev);
1923 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1924
1925 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
1926 return -EBUSY;
1927
1928 if (port->flags & UPF_IOREMAP) {
1929 port->membase = ioremap(port->mapbase, size);
1930 if (port->membase == NULL) {
1931 release_mem_region(port->mapbase, size);
1932 return -ENOMEM;
1933 }
1934 }
1935
1936 return 0;
1937 }
1938
1939 /*
1940 * Configure/autoconfigure the port.
1941 */
1942 static void atmel_config_port(struct uart_port *port, int flags)
1943 {
1944 if (flags & UART_CONFIG_TYPE) {
1945 port->type = PORT_ATMEL;
1946 atmel_request_port(port);
1947 }
1948 }
1949
1950 /*
1951 * Verify the new serial_struct (for TIOCSSERIAL).
1952 */
1953 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1954 {
1955 int ret = 0;
1956 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1957 ret = -EINVAL;
1958 if (port->irq != ser->irq)
1959 ret = -EINVAL;
1960 if (ser->io_type != SERIAL_IO_MEM)
1961 ret = -EINVAL;
1962 if (port->uartclk / 16 != ser->baud_base)
1963 ret = -EINVAL;
1964 if ((void *)port->mapbase != ser->iomem_base)
1965 ret = -EINVAL;
1966 if (port->iobase != ser->port)
1967 ret = -EINVAL;
1968 if (ser->hub6 != 0)
1969 ret = -EINVAL;
1970 return ret;
1971 }
1972
1973 #ifdef CONFIG_CONSOLE_POLL
1974 static int atmel_poll_get_char(struct uart_port *port)
1975 {
1976 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
1977 cpu_relax();
1978
1979 return UART_GET_CHAR(port);
1980 }
1981
1982 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
1983 {
1984 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1985 cpu_relax();
1986
1987 UART_PUT_CHAR(port, ch);
1988 }
1989 #endif
1990
1991 static int
1992 atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1993 {
1994 struct serial_rs485 rs485conf;
1995
1996 switch (cmd) {
1997 case TIOCSRS485:
1998 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1999 sizeof(rs485conf)))
2000 return -EFAULT;
2001
2002 atmel_config_rs485(port, &rs485conf);
2003 break;
2004
2005 case TIOCGRS485:
2006 if (copy_to_user((struct serial_rs485 *) arg,
2007 &(to_atmel_uart_port(port)->rs485),
2008 sizeof(rs485conf)))
2009 return -EFAULT;
2010 break;
2011
2012 default:
2013 return -ENOIOCTLCMD;
2014 }
2015 return 0;
2016 }
2017
2018
2019
2020 static struct uart_ops atmel_pops = {
2021 .tx_empty = atmel_tx_empty,
2022 .set_mctrl = atmel_set_mctrl,
2023 .get_mctrl = atmel_get_mctrl,
2024 .stop_tx = atmel_stop_tx,
2025 .start_tx = atmel_start_tx,
2026 .stop_rx = atmel_stop_rx,
2027 .enable_ms = atmel_enable_ms,
2028 .break_ctl = atmel_break_ctl,
2029 .startup = atmel_startup,
2030 .shutdown = atmel_shutdown,
2031 .flush_buffer = atmel_flush_buffer,
2032 .set_termios = atmel_set_termios,
2033 .set_ldisc = atmel_set_ldisc,
2034 .type = atmel_type,
2035 .release_port = atmel_release_port,
2036 .request_port = atmel_request_port,
2037 .config_port = atmel_config_port,
2038 .verify_port = atmel_verify_port,
2039 .pm = atmel_serial_pm,
2040 .ioctl = atmel_ioctl,
2041 #ifdef CONFIG_CONSOLE_POLL
2042 .poll_get_char = atmel_poll_get_char,
2043 .poll_put_char = atmel_poll_put_char,
2044 #endif
2045 };
2046
2047 /*
2048 * Configure the port from the platform device resource info.
2049 */
2050 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2051 struct platform_device *pdev)
2052 {
2053 int ret;
2054 struct uart_port *port = &atmel_port->uart;
2055 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2056
2057 if (!atmel_init_property(atmel_port, pdev))
2058 atmel_set_ops(port);
2059
2060 atmel_init_rs485(atmel_port, pdev);
2061
2062 port->iotype = UPIO_MEM;
2063 port->flags = UPF_BOOT_AUTOCONF;
2064 port->ops = &atmel_pops;
2065 port->fifosize = 1;
2066 port->dev = &pdev->dev;
2067 port->mapbase = pdev->resource[0].start;
2068 port->irq = pdev->resource[1].start;
2069
2070 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2071 (unsigned long)port);
2072
2073 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2074
2075 if (pdata && pdata->regs) {
2076 /* Already mapped by setup code */
2077 port->membase = pdata->regs;
2078 } else {
2079 port->flags |= UPF_IOREMAP;
2080 port->membase = NULL;
2081 }
2082
2083 /* for console, the clock could already be configured */
2084 if (!atmel_port->clk) {
2085 atmel_port->clk = clk_get(&pdev->dev, "usart");
2086 if (IS_ERR(atmel_port->clk)) {
2087 ret = PTR_ERR(atmel_port->clk);
2088 atmel_port->clk = NULL;
2089 return ret;
2090 }
2091 ret = clk_prepare_enable(atmel_port->clk);
2092 if (ret) {
2093 clk_put(atmel_port->clk);
2094 atmel_port->clk = NULL;
2095 return ret;
2096 }
2097 port->uartclk = clk_get_rate(atmel_port->clk);
2098 clk_disable_unprepare(atmel_port->clk);
2099 /* only enable clock when USART is in use */
2100 }
2101
2102 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2103 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
2104 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2105 else if (atmel_use_pdc_tx(port)) {
2106 port->fifosize = PDC_BUFFER_SIZE;
2107 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2108 } else {
2109 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2110 }
2111
2112 return 0;
2113 }
2114
2115 struct platform_device *atmel_default_console_device; /* the serial console device */
2116
2117 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2118 static void atmel_console_putchar(struct uart_port *port, int ch)
2119 {
2120 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
2121 cpu_relax();
2122 UART_PUT_CHAR(port, ch);
2123 }
2124
2125 /*
2126 * Interrupts are disabled on entering
2127 */
2128 static void atmel_console_write(struct console *co, const char *s, u_int count)
2129 {
2130 struct uart_port *port = &atmel_ports[co->index].uart;
2131 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2132 unsigned int status, imr;
2133 unsigned int pdc_tx;
2134
2135 /*
2136 * First, save IMR and then disable interrupts
2137 */
2138 imr = UART_GET_IMR(port);
2139 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2140
2141 /* Store PDC transmit status and disable it */
2142 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
2143 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
2144
2145 uart_console_write(port, s, count, atmel_console_putchar);
2146
2147 /*
2148 * Finally, wait for transmitter to become empty
2149 * and restore IMR
2150 */
2151 do {
2152 status = UART_GET_CSR(port);
2153 } while (!(status & ATMEL_US_TXRDY));
2154
2155 /* Restore PDC transmit status */
2156 if (pdc_tx)
2157 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
2158
2159 /* set interrupts back the way they were */
2160 UART_PUT_IER(port, imr);
2161 }
2162
2163 /*
2164 * If the port was already initialised (eg, by a boot loader),
2165 * try to determine the current setup.
2166 */
2167 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2168 int *parity, int *bits)
2169 {
2170 unsigned int mr, quot;
2171
2172 /*
2173 * If the baud rate generator isn't running, the port wasn't
2174 * initialized by the boot loader.
2175 */
2176 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
2177 if (!quot)
2178 return;
2179
2180 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
2181 if (mr == ATMEL_US_CHRL_8)
2182 *bits = 8;
2183 else
2184 *bits = 7;
2185
2186 mr = UART_GET_MR(port) & ATMEL_US_PAR;
2187 if (mr == ATMEL_US_PAR_EVEN)
2188 *parity = 'e';
2189 else if (mr == ATMEL_US_PAR_ODD)
2190 *parity = 'o';
2191
2192 /*
2193 * The serial core only rounds down when matching this to a
2194 * supported baud rate. Make sure we don't end up slightly
2195 * lower than one of those, as it would make us fall through
2196 * to a much lower baud rate than we really want.
2197 */
2198 *baud = port->uartclk / (16 * (quot - 1));
2199 }
2200
2201 static int __init atmel_console_setup(struct console *co, char *options)
2202 {
2203 int ret;
2204 struct uart_port *port = &atmel_ports[co->index].uart;
2205 int baud = 115200;
2206 int bits = 8;
2207 int parity = 'n';
2208 int flow = 'n';
2209
2210 if (port->membase == NULL) {
2211 /* Port not initialized yet - delay setup */
2212 return -ENODEV;
2213 }
2214
2215 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2216 if (ret)
2217 return ret;
2218
2219 UART_PUT_IDR(port, -1);
2220 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2221 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
2222
2223 if (options)
2224 uart_parse_options(options, &baud, &parity, &bits, &flow);
2225 else
2226 atmel_console_get_options(port, &baud, &parity, &bits);
2227
2228 return uart_set_options(port, co, baud, parity, bits, flow);
2229 }
2230
2231 static struct uart_driver atmel_uart;
2232
2233 static struct console atmel_console = {
2234 .name = ATMEL_DEVICENAME,
2235 .write = atmel_console_write,
2236 .device = uart_console_device,
2237 .setup = atmel_console_setup,
2238 .flags = CON_PRINTBUFFER,
2239 .index = -1,
2240 .data = &atmel_uart,
2241 };
2242
2243 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2244
2245 /*
2246 * Early console initialization (before VM subsystem initialized).
2247 */
2248 static int __init atmel_console_init(void)
2249 {
2250 int ret;
2251 if (atmel_default_console_device) {
2252 struct atmel_uart_data *pdata =
2253 dev_get_platdata(&atmel_default_console_device->dev);
2254 int id = pdata->num;
2255 struct atmel_uart_port *port = &atmel_ports[id];
2256
2257 port->backup_imr = 0;
2258 port->uart.line = id;
2259
2260 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2261 ret = atmel_init_port(port, atmel_default_console_device);
2262 if (ret)
2263 return ret;
2264 register_console(&atmel_console);
2265 }
2266
2267 return 0;
2268 }
2269
2270 console_initcall(atmel_console_init);
2271
2272 /*
2273 * Late console initialization.
2274 */
2275 static int __init atmel_late_console_init(void)
2276 {
2277 if (atmel_default_console_device
2278 && !(atmel_console.flags & CON_ENABLED))
2279 register_console(&atmel_console);
2280
2281 return 0;
2282 }
2283
2284 core_initcall(atmel_late_console_init);
2285
2286 static inline bool atmel_is_console_port(struct uart_port *port)
2287 {
2288 return port->cons && port->cons->index == port->line;
2289 }
2290
2291 #else
2292 #define ATMEL_CONSOLE_DEVICE NULL
2293
2294 static inline bool atmel_is_console_port(struct uart_port *port)
2295 {
2296 return false;
2297 }
2298 #endif
2299
2300 static struct uart_driver atmel_uart = {
2301 .owner = THIS_MODULE,
2302 .driver_name = "atmel_serial",
2303 .dev_name = ATMEL_DEVICENAME,
2304 .major = SERIAL_ATMEL_MAJOR,
2305 .minor = MINOR_START,
2306 .nr = ATMEL_MAX_UART,
2307 .cons = ATMEL_CONSOLE_DEVICE,
2308 };
2309
2310 #ifdef CONFIG_PM
2311 static bool atmel_serial_clk_will_stop(void)
2312 {
2313 #ifdef CONFIG_ARCH_AT91
2314 return at91_suspend_entering_slow_clock();
2315 #else
2316 return false;
2317 #endif
2318 }
2319
2320 static int atmel_serial_suspend(struct platform_device *pdev,
2321 pm_message_t state)
2322 {
2323 struct uart_port *port = platform_get_drvdata(pdev);
2324 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2325
2326 if (atmel_is_console_port(port) && console_suspend_enabled) {
2327 /* Drain the TX shifter */
2328 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
2329 cpu_relax();
2330 }
2331
2332 /* we can not wake up if we're running on slow clock */
2333 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2334 if (atmel_serial_clk_will_stop())
2335 device_set_wakeup_enable(&pdev->dev, 0);
2336
2337 uart_suspend_port(&atmel_uart, port);
2338
2339 return 0;
2340 }
2341
2342 static int atmel_serial_resume(struct platform_device *pdev)
2343 {
2344 struct uart_port *port = platform_get_drvdata(pdev);
2345 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2346
2347 uart_resume_port(&atmel_uart, port);
2348 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2349
2350 return 0;
2351 }
2352 #else
2353 #define atmel_serial_suspend NULL
2354 #define atmel_serial_resume NULL
2355 #endif
2356
2357 static int atmel_serial_probe(struct platform_device *pdev)
2358 {
2359 struct atmel_uart_port *port;
2360 struct device_node *np = pdev->dev.of_node;
2361 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2362 void *data;
2363 int ret = -ENODEV;
2364
2365 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2366
2367 if (np)
2368 ret = of_alias_get_id(np, "serial");
2369 else
2370 if (pdata)
2371 ret = pdata->num;
2372
2373 if (ret < 0)
2374 /* port id not found in platform data nor device-tree aliases:
2375 * auto-enumerate it */
2376 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2377
2378 if (ret >= ATMEL_MAX_UART) {
2379 ret = -ENODEV;
2380 goto err;
2381 }
2382
2383 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2384 /* port already in use */
2385 ret = -EBUSY;
2386 goto err;
2387 }
2388
2389 port = &atmel_ports[ret];
2390 port->backup_imr = 0;
2391 port->uart.line = ret;
2392
2393 ret = atmel_init_port(port, pdev);
2394 if (ret)
2395 goto err;
2396
2397 if (!atmel_use_pdc_rx(&port->uart)) {
2398 ret = -ENOMEM;
2399 data = kmalloc(sizeof(struct atmel_uart_char)
2400 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2401 if (!data)
2402 goto err_alloc_ring;
2403 port->rx_ring.buf = data;
2404 }
2405
2406 ret = uart_add_one_port(&atmel_uart, &port->uart);
2407 if (ret)
2408 goto err_add_port;
2409
2410 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2411 if (atmel_is_console_port(&port->uart)
2412 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2413 /*
2414 * The serial core enabled the clock for us, so undo
2415 * the clk_prepare_enable() in atmel_console_setup()
2416 */
2417 clk_disable_unprepare(port->clk);
2418 }
2419 #endif
2420
2421 device_init_wakeup(&pdev->dev, 1);
2422 platform_set_drvdata(pdev, port);
2423
2424 if (port->rs485.flags & SER_RS485_ENABLED) {
2425 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
2426 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
2427 }
2428
2429 /*
2430 * Get port name of usart or uart
2431 */
2432 atmel_get_ip_name(&port->uart);
2433
2434 return 0;
2435
2436 err_add_port:
2437 kfree(port->rx_ring.buf);
2438 port->rx_ring.buf = NULL;
2439 err_alloc_ring:
2440 if (!atmel_is_console_port(&port->uart)) {
2441 clk_put(port->clk);
2442 port->clk = NULL;
2443 }
2444 err:
2445 return ret;
2446 }
2447
2448 static int atmel_serial_remove(struct platform_device *pdev)
2449 {
2450 struct uart_port *port = platform_get_drvdata(pdev);
2451 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2452 int ret = 0;
2453
2454 tasklet_kill(&atmel_port->tasklet);
2455
2456 device_init_wakeup(&pdev->dev, 0);
2457
2458 ret = uart_remove_one_port(&atmel_uart, port);
2459
2460 kfree(atmel_port->rx_ring.buf);
2461
2462 /* "port" is allocated statically, so we shouldn't free it */
2463
2464 clear_bit(port->line, atmel_ports_in_use);
2465
2466 clk_put(atmel_port->clk);
2467
2468 return ret;
2469 }
2470
2471 static struct platform_driver atmel_serial_driver = {
2472 .probe = atmel_serial_probe,
2473 .remove = atmel_serial_remove,
2474 .suspend = atmel_serial_suspend,
2475 .resume = atmel_serial_resume,
2476 .driver = {
2477 .name = "atmel_usart",
2478 .owner = THIS_MODULE,
2479 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2480 },
2481 };
2482
2483 static int __init atmel_serial_init(void)
2484 {
2485 int ret;
2486
2487 ret = uart_register_driver(&atmel_uart);
2488 if (ret)
2489 return ret;
2490
2491 ret = platform_driver_register(&atmel_serial_driver);
2492 if (ret)
2493 uart_unregister_driver(&atmel_uart);
2494
2495 return ret;
2496 }
2497
2498 static void __exit atmel_serial_exit(void)
2499 {
2500 platform_driver_unregister(&atmel_serial_driver);
2501 uart_unregister_driver(&atmel_uart);
2502 }
2503
2504 module_init(atmel_serial_init);
2505 module_exit(atmel_serial_exit);
2506
2507 MODULE_AUTHOR("Rick Bronson");
2508 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
2509 MODULE_LICENSE("GPL");
2510 MODULE_ALIAS("platform:atmel_usart");
Linux with added FPC-III support