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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / drivers / tty / serial / serial-tegra.c
blobd5c2a287b7e760728d0c38e58d08fb2361c670ee
1 /*
2 * serial_tegra.c
3 *
4 * High-speed serial driver for NVIDIA Tegra SoCs
5 *
6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include <linux/clk.h>
24 #include <linux/debugfs.h>
25 #include <linux/delay.h>
26 #include <linux/dmaengine.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmapool.h>
29 #include <linux/err.h>
30 #include <linux/io.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/pagemap.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/serial.h>
39 #include <linux/serial_8250.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial_reg.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/termios.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47
48 #define TEGRA_UART_TYPE "TEGRA_UART"
49 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
50 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
51
52 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
53 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
54 #define TEGRA_UART_IER_EORD 0x20
55 #define TEGRA_UART_MCR_RTS_EN 0x40
56 #define TEGRA_UART_MCR_CTS_EN 0x20
57 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
58 UART_LSR_PE | UART_LSR_FE)
59 #define TEGRA_UART_IRDA_CSR 0x08
60 #define TEGRA_UART_SIR_ENABLED 0x80
61
62 #define TEGRA_UART_TX_PIO 1
63 #define TEGRA_UART_TX_DMA 2
64 #define TEGRA_UART_MIN_DMA 16
65 #define TEGRA_UART_FIFO_SIZE 32
66
67 /*
68 * Tx fifo trigger level setting in tegra uart is in
69 * reverse way then conventional uart.
70 */
71 #define TEGRA_UART_TX_TRIG_16B 0x00
72 #define TEGRA_UART_TX_TRIG_8B 0x10
73 #define TEGRA_UART_TX_TRIG_4B 0x20
74 #define TEGRA_UART_TX_TRIG_1B 0x30
75
76 #define TEGRA_UART_MAXIMUM 5
77
78 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
79 #define TEGRA_UART_DEFAULT_BAUD 115200
80 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
81
82 /* Tx transfer mode */
83 #define TEGRA_TX_PIO 1
84 #define TEGRA_TX_DMA 2
85
86 /**
87 * tegra_uart_chip_data: SOC specific data.
88 *
89 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
90 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
91 * Tegra30 does not allow this.
92 * @support_clk_src_div: Clock source support the clock divider.
93 */
94 struct tegra_uart_chip_data {
95 bool tx_fifo_full_status;
96 bool allow_txfifo_reset_fifo_mode;
97 bool support_clk_src_div;
98 };
99
100 struct tegra_uart_port {
101 struct uart_port uport;
102 const struct tegra_uart_chip_data *cdata;
103
104 struct clk *uart_clk;
105 struct reset_control *rst;
106 unsigned int current_baud;
107
108 /* Register shadow */
109 unsigned long fcr_shadow;
110 unsigned long mcr_shadow;
111 unsigned long lcr_shadow;
112 unsigned long ier_shadow;
113 bool rts_active;
114
115 int tx_in_progress;
116 unsigned int tx_bytes;
117
118 bool enable_modem_interrupt;
119
120 bool rx_timeout;
121 int rx_in_progress;
122 int symb_bit;
123
124 struct dma_chan *rx_dma_chan;
125 struct dma_chan *tx_dma_chan;
126 dma_addr_t rx_dma_buf_phys;
127 dma_addr_t tx_dma_buf_phys;
128 unsigned char *rx_dma_buf_virt;
129 unsigned char *tx_dma_buf_virt;
130 struct dma_async_tx_descriptor *tx_dma_desc;
131 struct dma_async_tx_descriptor *rx_dma_desc;
132 dma_cookie_t tx_cookie;
133 dma_cookie_t rx_cookie;
134 int tx_bytes_requested;
135 int rx_bytes_requested;
136 };
137
138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
140
141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
142 unsigned long reg)
143 {
144 return readl(tup->uport.membase + (reg << tup->uport.regshift));
145 }
146
147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
148 unsigned long reg)
149 {
150 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
151 }
152
153 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
154 {
155 return container_of(u, struct tegra_uart_port, uport);
156 }
157
158 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
159 {
160 struct tegra_uart_port *tup = to_tegra_uport(u);
161
162 /*
163 * RI - Ring detector is active
164 * CD/DCD/CAR - Carrier detect is always active. For some reason
165 * linux has different names for carrier detect.
166 * DSR - Data Set ready is active as the hardware doesn't support it.
167 * Don't know if the linux support this yet?
168 * CTS - Clear to send. Always set to active, as the hardware handles
169 * CTS automatically.
170 */
171 if (tup->enable_modem_interrupt)
172 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
173 return TIOCM_CTS;
174 }
175
176 static void set_rts(struct tegra_uart_port *tup, bool active)
177 {
178 unsigned long mcr;
179
180 mcr = tup->mcr_shadow;
181 if (active)
182 mcr |= TEGRA_UART_MCR_RTS_EN;
183 else
184 mcr &= ~TEGRA_UART_MCR_RTS_EN;
185 if (mcr != tup->mcr_shadow) {
186 tegra_uart_write(tup, mcr, UART_MCR);
187 tup->mcr_shadow = mcr;
188 }
189 return;
190 }
191
192 static void set_dtr(struct tegra_uart_port *tup, bool active)
193 {
194 unsigned long mcr;
195
196 mcr = tup->mcr_shadow;
197 if (active)
198 mcr |= UART_MCR_DTR;
199 else
200 mcr &= ~UART_MCR_DTR;
201 if (mcr != tup->mcr_shadow) {
202 tegra_uart_write(tup, mcr, UART_MCR);
203 tup->mcr_shadow = mcr;
204 }
205 return;
206 }
207
208 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
209 {
210 struct tegra_uart_port *tup = to_tegra_uport(u);
211 unsigned long mcr;
212 int dtr_enable;
213
214 mcr = tup->mcr_shadow;
215 tup->rts_active = !!(mctrl & TIOCM_RTS);
216 set_rts(tup, tup->rts_active);
217
218 dtr_enable = !!(mctrl & TIOCM_DTR);
219 set_dtr(tup, dtr_enable);
220 return;
221 }
222
223 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
224 {
225 struct tegra_uart_port *tup = to_tegra_uport(u);
226 unsigned long lcr;
227
228 lcr = tup->lcr_shadow;
229 if (break_ctl)
230 lcr |= UART_LCR_SBC;
231 else
232 lcr &= ~UART_LCR_SBC;
233 tegra_uart_write(tup, lcr, UART_LCR);
234 tup->lcr_shadow = lcr;
235 }
236
237 /* Wait for a symbol-time. */
238 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
239 unsigned int syms)
240 {
241 if (tup->current_baud)
242 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
243 tup->current_baud));
244 }
245
246 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
247 {
248 unsigned long fcr = tup->fcr_shadow;
249
250 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
251 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
252 tegra_uart_write(tup, fcr, UART_FCR);
253 } else {
254 fcr &= ~UART_FCR_ENABLE_FIFO;
255 tegra_uart_write(tup, fcr, UART_FCR);
256 udelay(60);
257 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
258 tegra_uart_write(tup, fcr, UART_FCR);
259 fcr |= UART_FCR_ENABLE_FIFO;
260 tegra_uart_write(tup, fcr, UART_FCR);
261 }
262
263 /* Dummy read to ensure the write is posted */
264 tegra_uart_read(tup, UART_SCR);
265
266 /* Wait for the flush to propagate. */
267 tegra_uart_wait_sym_time(tup, 1);
268 }
269
270 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
271 {
272 unsigned long rate;
273 unsigned int divisor;
274 unsigned long lcr;
275 int ret;
276
277 if (tup->current_baud == baud)
278 return 0;
279
280 if (tup->cdata->support_clk_src_div) {
281 rate = baud * 16;
282 ret = clk_set_rate(tup->uart_clk, rate);
283 if (ret < 0) {
284 dev_err(tup->uport.dev,
285 "clk_set_rate() failed for rate %lu\n", rate);
286 return ret;
287 }
288 divisor = 1;
289 } else {
290 rate = clk_get_rate(tup->uart_clk);
291 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
292 }
293
294 lcr = tup->lcr_shadow;
295 lcr |= UART_LCR_DLAB;
296 tegra_uart_write(tup, lcr, UART_LCR);
297
298 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
299 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
300
301 lcr &= ~UART_LCR_DLAB;
302 tegra_uart_write(tup, lcr, UART_LCR);
303
304 /* Dummy read to ensure the write is posted */
305 tegra_uart_read(tup, UART_SCR);
306
307 tup->current_baud = baud;
308
309 /* wait two character intervals at new rate */
310 tegra_uart_wait_sym_time(tup, 2);
311 return 0;
312 }
313
314 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
315 unsigned long lsr)
316 {
317 char flag = TTY_NORMAL;
318
319 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
320 if (lsr & UART_LSR_OE) {
321 /* Overrrun error */
322 flag |= TTY_OVERRUN;
323 tup->uport.icount.overrun++;
324 dev_err(tup->uport.dev, "Got overrun errors\n");
325 } else if (lsr & UART_LSR_PE) {
326 /* Parity error */
327 flag |= TTY_PARITY;
328 tup->uport.icount.parity++;
329 dev_err(tup->uport.dev, "Got Parity errors\n");
330 } else if (lsr & UART_LSR_FE) {
331 flag |= TTY_FRAME;
332 tup->uport.icount.frame++;
333 dev_err(tup->uport.dev, "Got frame errors\n");
334 } else if (lsr & UART_LSR_BI) {
335 dev_err(tup->uport.dev, "Got Break\n");
336 tup->uport.icount.brk++;
337 /* If FIFO read error without any data, reset Rx FIFO */
338 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
339 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
340 }
341 }
342 return flag;
343 }
344
345 static int tegra_uart_request_port(struct uart_port *u)
346 {
347 return 0;
348 }
349
350 static void tegra_uart_release_port(struct uart_port *u)
351 {
352 /* Nothing to do here */
353 }
354
355 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
356 {
357 struct circ_buf *xmit = &tup->uport.state->xmit;
358 int i;
359
360 for (i = 0; i < max_bytes; i++) {
361 BUG_ON(uart_circ_empty(xmit));
362 if (tup->cdata->tx_fifo_full_status) {
363 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
364 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
365 break;
366 }
367 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
368 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
369 tup->uport.icount.tx++;
370 }
371 }
372
373 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
374 unsigned int bytes)
375 {
376 if (bytes > TEGRA_UART_MIN_DMA)
377 bytes = TEGRA_UART_MIN_DMA;
378
379 tup->tx_in_progress = TEGRA_UART_TX_PIO;
380 tup->tx_bytes = bytes;
381 tup->ier_shadow |= UART_IER_THRI;
382 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
383 }
384
385 static void tegra_uart_tx_dma_complete(void *args)
386 {
387 struct tegra_uart_port *tup = args;
388 struct circ_buf *xmit = &tup->uport.state->xmit;
389 struct dma_tx_state state;
390 unsigned long flags;
391 int count;
392
393 dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state);
394 count = tup->tx_bytes_requested - state.residue;
395 async_tx_ack(tup->tx_dma_desc);
396 spin_lock_irqsave(&tup->uport.lock, flags);
397 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
398 tup->tx_in_progress = 0;
399 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
400 uart_write_wakeup(&tup->uport);
401 tegra_uart_start_next_tx(tup);
402 spin_unlock_irqrestore(&tup->uport.lock, flags);
403 }
404
405 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
406 unsigned long count)
407 {
408 struct circ_buf *xmit = &tup->uport.state->xmit;
409 dma_addr_t tx_phys_addr;
410
411 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
412 UART_XMIT_SIZE, DMA_TO_DEVICE);
413
414 tup->tx_bytes = count & ~(0xF);
415 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
416 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
417 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
418 DMA_PREP_INTERRUPT);
419 if (!tup->tx_dma_desc) {
420 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
421 return -EIO;
422 }
423
424 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
425 tup->tx_dma_desc->callback_param = tup;
426 tup->tx_in_progress = TEGRA_UART_TX_DMA;
427 tup->tx_bytes_requested = tup->tx_bytes;
428 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
429 dma_async_issue_pending(tup->tx_dma_chan);
430 return 0;
431 }
432
433 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
434 {
435 unsigned long tail;
436 unsigned long count;
437 struct circ_buf *xmit = &tup->uport.state->xmit;
438
439 tail = (unsigned long)&xmit->buf[xmit->tail];
440 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
441 if (!count)
442 return;
443
444 if (count < TEGRA_UART_MIN_DMA)
445 tegra_uart_start_pio_tx(tup, count);
446 else if (BYTES_TO_ALIGN(tail) > 0)
447 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
448 else
449 tegra_uart_start_tx_dma(tup, count);
450 }
451
452 /* Called by serial core driver with u->lock taken. */
453 static void tegra_uart_start_tx(struct uart_port *u)
454 {
455 struct tegra_uart_port *tup = to_tegra_uport(u);
456 struct circ_buf *xmit = &u->state->xmit;
457
458 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
459 tegra_uart_start_next_tx(tup);
460 }
461
462 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
463 {
464 struct tegra_uart_port *tup = to_tegra_uport(u);
465 unsigned int ret = 0;
466 unsigned long flags;
467
468 spin_lock_irqsave(&u->lock, flags);
469 if (!tup->tx_in_progress) {
470 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
471 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
472 ret = TIOCSER_TEMT;
473 }
474 spin_unlock_irqrestore(&u->lock, flags);
475 return ret;
476 }
477
478 static void tegra_uart_stop_tx(struct uart_port *u)
479 {
480 struct tegra_uart_port *tup = to_tegra_uport(u);
481 struct circ_buf *xmit = &tup->uport.state->xmit;
482 struct dma_tx_state state;
483 int count;
484
485 dmaengine_terminate_all(tup->tx_dma_chan);
486 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
487 count = tup->tx_bytes_requested - state.residue;
488 async_tx_ack(tup->tx_dma_desc);
489 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
490 tup->tx_in_progress = 0;
491 return;
492 }
493
494 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
495 {
496 struct circ_buf *xmit = &tup->uport.state->xmit;
497
498 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
499 tup->tx_in_progress = 0;
500 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
501 uart_write_wakeup(&tup->uport);
502 tegra_uart_start_next_tx(tup);
503 return;
504 }
505
506 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
507 struct tty_port *tty)
508 {
509 do {
510 char flag = TTY_NORMAL;
511 unsigned long lsr = 0;
512 unsigned char ch;
513
514 lsr = tegra_uart_read(tup, UART_LSR);
515 if (!(lsr & UART_LSR_DR))
516 break;
517
518 flag = tegra_uart_decode_rx_error(tup, lsr);
519 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
520 tup->uport.icount.rx++;
521
522 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
523 tty_insert_flip_char(tty, ch, flag);
524 } while (1);
525
526 return;
527 }
528
529 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
530 struct tty_port *tty, int count)
531 {
532 int copied;
533
534 tup->uport.icount.rx += count;
535 if (!tty) {
536 dev_err(tup->uport.dev, "No tty port\n");
537 return;
538 }
539 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
540 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
541 copied = tty_insert_flip_string(tty,
542 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
543 if (copied != count) {
544 WARN_ON(1);
545 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
546 }
547 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
548 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
549 }
550
551 static void tegra_uart_rx_dma_complete(void *args)
552 {
553 struct tegra_uart_port *tup = args;
554 struct uart_port *u = &tup->uport;
555 int count = tup->rx_bytes_requested;
556 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
557 struct tty_port *port = &u->state->port;
558 unsigned long flags;
559
560 async_tx_ack(tup->rx_dma_desc);
561 spin_lock_irqsave(&u->lock, flags);
562
563 /* Deactivate flow control to stop sender */
564 if (tup->rts_active)
565 set_rts(tup, false);
566
567 /* If we are here, DMA is stopped */
568 if (count)
569 tegra_uart_copy_rx_to_tty(tup, port, count);
570
571 tegra_uart_handle_rx_pio(tup, port);
572 if (tty) {
573 spin_unlock_irqrestore(&u->lock, flags);
574 tty_flip_buffer_push(port);
575 spin_lock_irqsave(&u->lock, flags);
576 tty_kref_put(tty);
577 }
578 tegra_uart_start_rx_dma(tup);
579
580 /* Activate flow control to start transfer */
581 if (tup->rts_active)
582 set_rts(tup, true);
583
584 spin_unlock_irqrestore(&u->lock, flags);
585 }
586
587 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup,
588 unsigned long *flags)
589 {
590 struct dma_tx_state state;
591 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
592 struct tty_port *port = &tup->uport.state->port;
593 struct uart_port *u = &tup->uport;
594 int count;
595
596 /* Deactivate flow control to stop sender */
597 if (tup->rts_active)
598 set_rts(tup, false);
599
600 dmaengine_terminate_all(tup->rx_dma_chan);
601 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
602 count = tup->rx_bytes_requested - state.residue;
603
604 /* If we are here, DMA is stopped */
605 if (count)
606 tegra_uart_copy_rx_to_tty(tup, port, count);
607
608 tegra_uart_handle_rx_pio(tup, port);
609 if (tty) {
610 spin_unlock_irqrestore(&u->lock, *flags);
611 tty_flip_buffer_push(port);
612 spin_lock_irqsave(&u->lock, *flags);
613 tty_kref_put(tty);
614 }
615 tegra_uart_start_rx_dma(tup);
616
617 if (tup->rts_active)
618 set_rts(tup, true);
619 }
620
621 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
622 {
623 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
624
625 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
626 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
627 DMA_PREP_INTERRUPT);
628 if (!tup->rx_dma_desc) {
629 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
630 return -EIO;
631 }
632
633 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
634 tup->rx_dma_desc->callback_param = tup;
635 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
636 count, DMA_TO_DEVICE);
637 tup->rx_bytes_requested = count;
638 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
639 dma_async_issue_pending(tup->rx_dma_chan);
640 return 0;
641 }
642
643 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
644 {
645 struct tegra_uart_port *tup = to_tegra_uport(u);
646 unsigned long msr;
647
648 msr = tegra_uart_read(tup, UART_MSR);
649 if (!(msr & UART_MSR_ANY_DELTA))
650 return;
651
652 if (msr & UART_MSR_TERI)
653 tup->uport.icount.rng++;
654 if (msr & UART_MSR_DDSR)
655 tup->uport.icount.dsr++;
656 /* We may only get DDCD when HW init and reset */
657 if (msr & UART_MSR_DDCD)
658 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
659 /* Will start/stop_tx accordingly */
660 if (msr & UART_MSR_DCTS)
661 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
662 return;
663 }
664
665 static irqreturn_t tegra_uart_isr(int irq, void *data)
666 {
667 struct tegra_uart_port *tup = data;
668 struct uart_port *u = &tup->uport;
669 unsigned long iir;
670 unsigned long ier;
671 bool is_rx_int = false;
672 unsigned long flags;
673
674 spin_lock_irqsave(&u->lock, flags);
675 while (1) {
676 iir = tegra_uart_read(tup, UART_IIR);
677 if (iir & UART_IIR_NO_INT) {
678 if (is_rx_int) {
679 tegra_uart_handle_rx_dma(tup, &flags);
680 if (tup->rx_in_progress) {
681 ier = tup->ier_shadow;
682 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
683 TEGRA_UART_IER_EORD);
684 tup->ier_shadow = ier;
685 tegra_uart_write(tup, ier, UART_IER);
686 }
687 }
688 spin_unlock_irqrestore(&u->lock, flags);
689 return IRQ_HANDLED;
690 }
691
692 switch ((iir >> 1) & 0x7) {
693 case 0: /* Modem signal change interrupt */
694 tegra_uart_handle_modem_signal_change(u);
695 break;
696
697 case 1: /* Transmit interrupt only triggered when using PIO */
698 tup->ier_shadow &= ~UART_IER_THRI;
699 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
700 tegra_uart_handle_tx_pio(tup);
701 break;
702
703 case 4: /* End of data */
704 case 6: /* Rx timeout */
705 case 2: /* Receive */
706 if (!is_rx_int) {
707 is_rx_int = true;
708 /* Disable Rx interrupts */
709 ier = tup->ier_shadow;
710 ier |= UART_IER_RDI;
711 tegra_uart_write(tup, ier, UART_IER);
712 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
713 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
714 tup->ier_shadow = ier;
715 tegra_uart_write(tup, ier, UART_IER);
716 }
717 break;
718
719 case 3: /* Receive error */
720 tegra_uart_decode_rx_error(tup,
721 tegra_uart_read(tup, UART_LSR));
722 break;
723
724 case 5: /* break nothing to handle */
725 case 7: /* break nothing to handle */
726 break;
727 }
728 }
729 }
730
731 static void tegra_uart_stop_rx(struct uart_port *u)
732 {
733 struct tegra_uart_port *tup = to_tegra_uport(u);
734 struct tty_struct *tty;
735 struct tty_port *port = &u->state->port;
736 struct dma_tx_state state;
737 unsigned long ier;
738 int count;
739
740 if (tup->rts_active)
741 set_rts(tup, false);
742
743 if (!tup->rx_in_progress)
744 return;
745
746 tty = tty_port_tty_get(&tup->uport.state->port);
747
748 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
749
750 ier = tup->ier_shadow;
751 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
752 TEGRA_UART_IER_EORD);
753 tup->ier_shadow = ier;
754 tegra_uart_write(tup, ier, UART_IER);
755 tup->rx_in_progress = 0;
756 if (tup->rx_dma_chan) {
757 dmaengine_terminate_all(tup->rx_dma_chan);
758 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
759 async_tx_ack(tup->rx_dma_desc);
760 count = tup->rx_bytes_requested - state.residue;
761 tegra_uart_copy_rx_to_tty(tup, port, count);
762 tegra_uart_handle_rx_pio(tup, port);
763 } else {
764 tegra_uart_handle_rx_pio(tup, port);
765 }
766 if (tty) {
767 tty_flip_buffer_push(port);
768 tty_kref_put(tty);
769 }
770 return;
771 }
772
773 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
774 {
775 unsigned long flags;
776 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
777 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
778 unsigned long wait_time;
779 unsigned long lsr;
780 unsigned long msr;
781 unsigned long mcr;
782
783 /* Disable interrupts */
784 tegra_uart_write(tup, 0, UART_IER);
785
786 lsr = tegra_uart_read(tup, UART_LSR);
787 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
788 msr = tegra_uart_read(tup, UART_MSR);
789 mcr = tegra_uart_read(tup, UART_MCR);
790 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
791 dev_err(tup->uport.dev,
792 "Tx Fifo not empty, CTS disabled, waiting\n");
793
794 /* Wait for Tx fifo to be empty */
795 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
796 wait_time = min(fifo_empty_time, 100lu);
797 udelay(wait_time);
798 fifo_empty_time -= wait_time;
799 if (!fifo_empty_time) {
800 msr = tegra_uart_read(tup, UART_MSR);
801 mcr = tegra_uart_read(tup, UART_MCR);
802 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
803 (msr & UART_MSR_CTS))
804 dev_err(tup->uport.dev,
805 "Slave not ready\n");
806 break;
807 }
808 lsr = tegra_uart_read(tup, UART_LSR);
809 }
810 }
811
812 spin_lock_irqsave(&tup->uport.lock, flags);
813 /* Reset the Rx and Tx FIFOs */
814 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
815 tup->current_baud = 0;
816 spin_unlock_irqrestore(&tup->uport.lock, flags);
817
818 clk_disable_unprepare(tup->uart_clk);
819 }
820
821 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
822 {
823 int ret;
824
825 tup->fcr_shadow = 0;
826 tup->mcr_shadow = 0;
827 tup->lcr_shadow = 0;
828 tup->ier_shadow = 0;
829 tup->current_baud = 0;
830
831 clk_prepare_enable(tup->uart_clk);
832
833 /* Reset the UART controller to clear all previous status.*/
834 reset_control_assert(tup->rst);
835 udelay(10);
836 reset_control_deassert(tup->rst);
837
838 tup->rx_in_progress = 0;
839 tup->tx_in_progress = 0;
840
841 /*
842 * Set the trigger level
843 *
844 * For PIO mode:
845 *
846 * For receive, this will interrupt the CPU after that many number of
847 * bytes are received, for the remaining bytes the receive timeout
848 * interrupt is received. Rx high watermark is set to 4.
849 *
850 * For transmit, if the trasnmit interrupt is enabled, this will
851 * interrupt the CPU when the number of entries in the FIFO reaches the
852 * low watermark. Tx low watermark is set to 16 bytes.
853 *
854 * For DMA mode:
855 *
856 * Set the Tx trigger to 16. This should match the DMA burst size that
857 * programmed in the DMA registers.
858 */
859 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
860 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
861 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
862 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
863
864 /*
865 * Initialize the UART with default configuration
866 * (115200, N, 8, 1) so that the receive DMA buffer may be
867 * enqueued
868 */
869 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
870 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
871 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
872 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
873
874 ret = tegra_uart_start_rx_dma(tup);
875 if (ret < 0) {
876 dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
877 return ret;
878 }
879 tup->rx_in_progress = 1;
880
881 /*
882 * Enable IE_RXS for the receive status interrupts like line errros.
883 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
884 *
885 * If using DMA mode, enable EORD instead of receive interrupt which
886 * will interrupt after the UART is done with the receive instead of
887 * the interrupt when the FIFO "threshold" is reached.
888 *
889 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
890 * the DATA is sitting in the FIFO and couldn't be transferred to the
891 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
892 * triggered when there is a pause of the incomming data stream for 4
893 * characters long.
894 *
895 * For pauses in the data which is not aligned to 4 bytes, we get
896 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
897 * then the EORD.
898 */
899 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD;
900 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
901 return 0;
902 }
903
904 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
905 bool dma_to_memory)
906 {
907 struct dma_chan *dma_chan;
908 unsigned char *dma_buf;
909 dma_addr_t dma_phys;
910 int ret;
911 struct dma_slave_config dma_sconfig;
912
913 dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
914 dma_to_memory ? "rx" : "tx");
915 if (IS_ERR(dma_chan)) {
916 ret = PTR_ERR(dma_chan);
917 dev_err(tup->uport.dev,
918 "DMA channel alloc failed: %d\n", ret);
919 return ret;
920 }
921
922 if (dma_to_memory) {
923 dma_buf = dma_alloc_coherent(tup->uport.dev,
924 TEGRA_UART_RX_DMA_BUFFER_SIZE,
925 &dma_phys, GFP_KERNEL);
926 if (!dma_buf) {
927 dev_err(tup->uport.dev,
928 "Not able to allocate the dma buffer\n");
929 dma_release_channel(dma_chan);
930 return -ENOMEM;
931 }
932 } else {
933 dma_phys = dma_map_single(tup->uport.dev,
934 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
935 DMA_TO_DEVICE);
936 dma_buf = tup->uport.state->xmit.buf;
937 }
938
939 if (dma_to_memory) {
940 dma_sconfig.src_addr = tup->uport.mapbase;
941 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
942 dma_sconfig.src_maxburst = 4;
943 } else {
944 dma_sconfig.dst_addr = tup->uport.mapbase;
945 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
946 dma_sconfig.dst_maxburst = 16;
947 }
948
949 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
950 if (ret < 0) {
951 dev_err(tup->uport.dev,
952 "Dma slave config failed, err = %d\n", ret);
953 goto scrub;
954 }
955
956 if (dma_to_memory) {
957 tup->rx_dma_chan = dma_chan;
958 tup->rx_dma_buf_virt = dma_buf;
959 tup->rx_dma_buf_phys = dma_phys;
960 } else {
961 tup->tx_dma_chan = dma_chan;
962 tup->tx_dma_buf_virt = dma_buf;
963 tup->tx_dma_buf_phys = dma_phys;
964 }
965 return 0;
966
967 scrub:
968 dma_release_channel(dma_chan);
969 return ret;
970 }
971
972 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
973 bool dma_to_memory)
974 {
975 struct dma_chan *dma_chan;
976
977 if (dma_to_memory) {
978 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
979 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
980 dma_chan = tup->rx_dma_chan;
981 tup->rx_dma_chan = NULL;
982 tup->rx_dma_buf_phys = 0;
983 tup->rx_dma_buf_virt = NULL;
984 } else {
985 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
986 UART_XMIT_SIZE, DMA_TO_DEVICE);
987 dma_chan = tup->tx_dma_chan;
988 tup->tx_dma_chan = NULL;
989 tup->tx_dma_buf_phys = 0;
990 tup->tx_dma_buf_virt = NULL;
991 }
992 dma_release_channel(dma_chan);
993 }
994
995 static int tegra_uart_startup(struct uart_port *u)
996 {
997 struct tegra_uart_port *tup = to_tegra_uport(u);
998 int ret;
999
1000 ret = tegra_uart_dma_channel_allocate(tup, false);
1001 if (ret < 0) {
1002 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
1003 return ret;
1004 }
1005
1006 ret = tegra_uart_dma_channel_allocate(tup, true);
1007 if (ret < 0) {
1008 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1009 goto fail_rx_dma;
1010 }
1011
1012 ret = tegra_uart_hw_init(tup);
1013 if (ret < 0) {
1014 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1015 goto fail_hw_init;
1016 }
1017
1018 ret = request_irq(u->irq, tegra_uart_isr, 0,
1019 dev_name(u->dev), tup);
1020 if (ret < 0) {
1021 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1022 goto fail_hw_init;
1023 }
1024 return 0;
1025
1026 fail_hw_init:
1027 tegra_uart_dma_channel_free(tup, true);
1028 fail_rx_dma:
1029 tegra_uart_dma_channel_free(tup, false);
1030 return ret;
1031 }
1032
1033 static void tegra_uart_shutdown(struct uart_port *u)
1034 {
1035 struct tegra_uart_port *tup = to_tegra_uport(u);
1036
1037 tegra_uart_hw_deinit(tup);
1038
1039 tup->rx_in_progress = 0;
1040 tup->tx_in_progress = 0;
1041
1042 tegra_uart_dma_channel_free(tup, true);
1043 tegra_uart_dma_channel_free(tup, false);
1044 free_irq(u->irq, tup);
1045 }
1046
1047 static void tegra_uart_enable_ms(struct uart_port *u)
1048 {
1049 struct tegra_uart_port *tup = to_tegra_uport(u);
1050
1051 if (tup->enable_modem_interrupt) {
1052 tup->ier_shadow |= UART_IER_MSI;
1053 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1054 }
1055 }
1056
1057 static void tegra_uart_set_termios(struct uart_port *u,
1058 struct ktermios *termios, struct ktermios *oldtermios)
1059 {
1060 struct tegra_uart_port *tup = to_tegra_uport(u);
1061 unsigned int baud;
1062 unsigned long flags;
1063 unsigned int lcr;
1064 int symb_bit = 1;
1065 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1066 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1067 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1068
1069 max_divider *= 16;
1070 spin_lock_irqsave(&u->lock, flags);
1071
1072 /* Changing configuration, it is safe to stop any rx now */
1073 if (tup->rts_active)
1074 set_rts(tup, false);
1075
1076 /* Clear all interrupts as configuration is going to be change */
1077 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1078 tegra_uart_read(tup, UART_IER);
1079 tegra_uart_write(tup, 0, UART_IER);
1080 tegra_uart_read(tup, UART_IER);
1081
1082 /* Parity */
1083 lcr = tup->lcr_shadow;
1084 lcr &= ~UART_LCR_PARITY;
1085
1086 /* CMSPAR isn't supported by this driver */
1087 termios->c_cflag &= ~CMSPAR;
1088
1089 if ((termios->c_cflag & PARENB) == PARENB) {
1090 symb_bit++;
1091 if (termios->c_cflag & PARODD) {
1092 lcr |= UART_LCR_PARITY;
1093 lcr &= ~UART_LCR_EPAR;
1094 lcr &= ~UART_LCR_SPAR;
1095 } else {
1096 lcr |= UART_LCR_PARITY;
1097 lcr |= UART_LCR_EPAR;
1098 lcr &= ~UART_LCR_SPAR;
1099 }
1100 }
1101
1102 lcr &= ~UART_LCR_WLEN8;
1103 switch (termios->c_cflag & CSIZE) {
1104 case CS5:
1105 lcr |= UART_LCR_WLEN5;
1106 symb_bit += 5;
1107 break;
1108 case CS6:
1109 lcr |= UART_LCR_WLEN6;
1110 symb_bit += 6;
1111 break;
1112 case CS7:
1113 lcr |= UART_LCR_WLEN7;
1114 symb_bit += 7;
1115 break;
1116 default:
1117 lcr |= UART_LCR_WLEN8;
1118 symb_bit += 8;
1119 break;
1120 }
1121
1122 /* Stop bits */
1123 if (termios->c_cflag & CSTOPB) {
1124 lcr |= UART_LCR_STOP;
1125 symb_bit += 2;
1126 } else {
1127 lcr &= ~UART_LCR_STOP;
1128 symb_bit++;
1129 }
1130
1131 tegra_uart_write(tup, lcr, UART_LCR);
1132 tup->lcr_shadow = lcr;
1133 tup->symb_bit = symb_bit;
1134
1135 /* Baud rate. */
1136 baud = uart_get_baud_rate(u, termios, oldtermios,
1137 parent_clk_rate/max_divider,
1138 parent_clk_rate/16);
1139 spin_unlock_irqrestore(&u->lock, flags);
1140 tegra_set_baudrate(tup, baud);
1141 if (tty_termios_baud_rate(termios))
1142 tty_termios_encode_baud_rate(termios, baud, baud);
1143 spin_lock_irqsave(&u->lock, flags);
1144
1145 /* Flow control */
1146 if (termios->c_cflag & CRTSCTS) {
1147 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1148 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1149 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1150 /* if top layer has asked to set rts active then do so here */
1151 if (tup->rts_active)
1152 set_rts(tup, true);
1153 } else {
1154 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1155 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1156 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1157 }
1158
1159 /* update the port timeout based on new settings */
1160 uart_update_timeout(u, termios->c_cflag, baud);
1161
1162 /* Make sure all write has completed */
1163 tegra_uart_read(tup, UART_IER);
1164
1165 /* Reenable interrupt */
1166 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1167 tegra_uart_read(tup, UART_IER);
1168
1169 spin_unlock_irqrestore(&u->lock, flags);
1170 return;
1171 }
1172
1173 /*
1174 * Flush any TX data submitted for DMA and PIO. Called when the
1175 * TX circular buffer is reset.
1176 */
1177 static void tegra_uart_flush_buffer(struct uart_port *u)
1178 {
1179 struct tegra_uart_port *tup = to_tegra_uport(u);
1180
1181 tup->tx_bytes = 0;
1182 if (tup->tx_dma_chan)
1183 dmaengine_terminate_all(tup->tx_dma_chan);
1184 return;
1185 }
1186
1187 static const char *tegra_uart_type(struct uart_port *u)
1188 {
1189 return TEGRA_UART_TYPE;
1190 }
1191
1192 static struct uart_ops tegra_uart_ops = {
1193 .tx_empty = tegra_uart_tx_empty,
1194 .set_mctrl = tegra_uart_set_mctrl,
1195 .get_mctrl = tegra_uart_get_mctrl,
1196 .stop_tx = tegra_uart_stop_tx,
1197 .start_tx = tegra_uart_start_tx,
1198 .stop_rx = tegra_uart_stop_rx,
1199 .flush_buffer = tegra_uart_flush_buffer,
1200 .enable_ms = tegra_uart_enable_ms,
1201 .break_ctl = tegra_uart_break_ctl,
1202 .startup = tegra_uart_startup,
1203 .shutdown = tegra_uart_shutdown,
1204 .set_termios = tegra_uart_set_termios,
1205 .type = tegra_uart_type,
1206 .request_port = tegra_uart_request_port,
1207 .release_port = tegra_uart_release_port,
1208 };
1209
1210 static struct uart_driver tegra_uart_driver = {
1211 .owner = THIS_MODULE,
1212 .driver_name = "tegra_hsuart",
1213 .dev_name = "ttyTHS",
1214 .cons = NULL,
1215 .nr = TEGRA_UART_MAXIMUM,
1216 };
1217
1218 static int tegra_uart_parse_dt(struct platform_device *pdev,
1219 struct tegra_uart_port *tup)
1220 {
1221 struct device_node *np = pdev->dev.of_node;
1222 int port;
1223
1224 port = of_alias_get_id(np, "serial");
1225 if (port < 0) {
1226 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1227 return port;
1228 }
1229 tup->uport.line = port;
1230
1231 tup->enable_modem_interrupt = of_property_read_bool(np,
1232 "nvidia,enable-modem-interrupt");
1233 return 0;
1234 }
1235
1236 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1237 .tx_fifo_full_status = false,
1238 .allow_txfifo_reset_fifo_mode = true,
1239 .support_clk_src_div = false,
1240 };
1241
1242 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1243 .tx_fifo_full_status = true,
1244 .allow_txfifo_reset_fifo_mode = false,
1245 .support_clk_src_div = true,
1246 };
1247
1248 static struct of_device_id tegra_uart_of_match[] = {
1249 {
1250 .compatible = "nvidia,tegra30-hsuart",
1251 .data = &tegra30_uart_chip_data,
1252 }, {
1253 .compatible = "nvidia,tegra20-hsuart",
1254 .data = &tegra20_uart_chip_data,
1255 }, {
1256 },
1257 };
1258 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1259
1260 static int tegra_uart_probe(struct platform_device *pdev)
1261 {
1262 struct tegra_uart_port *tup;
1263 struct uart_port *u;
1264 struct resource *resource;
1265 int ret;
1266 const struct tegra_uart_chip_data *cdata;
1267 const struct of_device_id *match;
1268
1269 match = of_match_device(tegra_uart_of_match, &pdev->dev);
1270 if (!match) {
1271 dev_err(&pdev->dev, "Error: No device match found\n");
1272 return -ENODEV;
1273 }
1274 cdata = match->data;
1275
1276 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1277 if (!tup) {
1278 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1279 return -ENOMEM;
1280 }
1281
1282 ret = tegra_uart_parse_dt(pdev, tup);
1283 if (ret < 0)
1284 return ret;
1285
1286 u = &tup->uport;
1287 u->dev = &pdev->dev;
1288 u->ops = &tegra_uart_ops;
1289 u->type = PORT_TEGRA;
1290 u->fifosize = 32;
1291 tup->cdata = cdata;
1292
1293 platform_set_drvdata(pdev, tup);
1294 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1295 if (!resource) {
1296 dev_err(&pdev->dev, "No IO memory resource\n");
1297 return -ENODEV;
1298 }
1299
1300 u->mapbase = resource->start;
1301 u->membase = devm_ioremap_resource(&pdev->dev, resource);
1302 if (IS_ERR(u->membase))
1303 return PTR_ERR(u->membase);
1304
1305 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1306 if (IS_ERR(tup->uart_clk)) {
1307 dev_err(&pdev->dev, "Couldn't get the clock\n");
1308 return PTR_ERR(tup->uart_clk);
1309 }
1310
1311 tup->rst = devm_reset_control_get(&pdev->dev, "serial");
1312 if (IS_ERR(tup->rst)) {
1313 dev_err(&pdev->dev, "Couldn't get the reset\n");
1314 return PTR_ERR(tup->rst);
1315 }
1316
1317 u->iotype = UPIO_MEM32;
1318 u->irq = platform_get_irq(pdev, 0);
1319 u->regshift = 2;
1320 ret = uart_add_one_port(&tegra_uart_driver, u);
1321 if (ret < 0) {
1322 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1323 return ret;
1324 }
1325 return ret;
1326 }
1327
1328 static int tegra_uart_remove(struct platform_device *pdev)
1329 {
1330 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1331 struct uart_port *u = &tup->uport;
1332
1333 uart_remove_one_port(&tegra_uart_driver, u);
1334 return 0;
1335 }
1336
1337 #ifdef CONFIG_PM_SLEEP
1338 static int tegra_uart_suspend(struct device *dev)
1339 {
1340 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1341 struct uart_port *u = &tup->uport;
1342
1343 return uart_suspend_port(&tegra_uart_driver, u);
1344 }
1345
1346 static int tegra_uart_resume(struct device *dev)
1347 {
1348 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1349 struct uart_port *u = &tup->uport;
1350
1351 return uart_resume_port(&tegra_uart_driver, u);
1352 }
1353 #endif
1354
1355 static const struct dev_pm_ops tegra_uart_pm_ops = {
1356 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1357 };
1358
1359 static struct platform_driver tegra_uart_platform_driver = {
1360 .probe = tegra_uart_probe,
1361 .remove = tegra_uart_remove,
1362 .driver = {
1363 .name = "serial-tegra",
1364 .of_match_table = tegra_uart_of_match,
1365 .pm = &tegra_uart_pm_ops,
1366 },
1367 };
1368
1369 static int __init tegra_uart_init(void)
1370 {
1371 int ret;
1372
1373 ret = uart_register_driver(&tegra_uart_driver);
1374 if (ret < 0) {
1375 pr_err("Could not register %s driver\n",
1376 tegra_uart_driver.driver_name);
1377 return ret;
1378 }
1379
1380 ret = platform_driver_register(&tegra_uart_platform_driver);
1381 if (ret < 0) {
1382 pr_err("Uart platform driver register failed, e = %d\n", ret);
1383 uart_unregister_driver(&tegra_uart_driver);
1384 return ret;
1385 }
1386 return 0;
1387 }
1388
1389 static void __exit tegra_uart_exit(void)
1390 {
1391 pr_info("Unloading tegra uart driver\n");
1392 platform_driver_unregister(&tegra_uart_platform_driver);
1393 uart_unregister_driver(&tegra_uart_driver);
1394 }
1395
1396 module_init(tegra_uart_init);
1397 module_exit(tegra_uart_exit);
1398
1399 MODULE_ALIAS("platform:serial-tegra");
1400 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1401 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1402 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support