arch/sparc/kernel/setup_64.c

   1 /*
   2  *  linux/arch/sparc64/kernel/setup.c
   3  *
   4  *  Copyright (C) 1995,1996  David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997       Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/errno.h>
   9 #include <linux/sched.h>
  10 #include <linux/kernel.h>
  11 #include <linux/mm.h>
  12 #include <linux/stddef.h>
  13 #include <linux/unistd.h>
  14 #include <linux/ptrace.h>
  15 #include <asm/smp.h>
  16 #include <linux/user.h>
  17 #include <linux/screen_info.h>
  18 #include <linux/delay.h>
  19 #include <linux/fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/syscalls.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/major.h>
  24 #include <linux/string.h>
  25 #include <linux/init.h>
  26 #include <linux/inet.h>
  27 #include <linux/console.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/cpu.h>
  31 #include <linux/initrd.h>
  32 #include <linux/module.h>
  33 #include <linux/start_kernel.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/processor.h>
  37 #include <asm/oplib.h>
  38 #include <asm/page.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/idprom.h>
  41 #include <asm/head.h>
  42 #include <asm/starfire.h>
  43 #include <asm/mmu_context.h>
  44 #include <asm/timer.h>
  45 #include <asm/sections.h>
  46 #include <asm/setup.h>
  47 #include <asm/mmu.h>
  48 #include <asm/ns87303.h>
  49 #include <asm/btext.h>
  50 #include <asm/elf.h>
  51 #include <asm/mdesc.h>
  52 #include <asm/cacheflush.h>
  53
  54 #ifdef CONFIG_IP_PNP
  55 #include <net/ipconfig.h>
  56 #endif
  57
  58 #include "entry.h"
  59 #include "kernel.h"
  60
  61 /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
  62  * operations in asm/ns87303.h
  63  */
  64 DEFINE_SPINLOCK(ns87303_lock);
  65 EXPORT_SYMBOL(ns87303_lock);
  66
  67 struct screen_info screen_info = {
  68         0, 0,                   /* orig-x, orig-y */
  69         0,                      /* unused */
  70         0,                      /* orig-video-page */
  71         0,                      /* orig-video-mode */
  72         128,                    /* orig-video-cols */
  73         0, 0, 0,                /* unused, ega_bx, unused */
  74         54,                     /* orig-video-lines */
  75         0,                      /* orig-video-isVGA */
  76         16                      /* orig-video-points */
  77 };
  78
  79 static void
  80 prom_console_write(struct console *con, const char *s, unsigned int n)
  81 {
  82         prom_write(s, n);
  83 }
  84
  85 /* Exported for mm/init.c:paging_init. */
  86 unsigned long cmdline_memory_size = 0;
  87
  88 static struct console prom_early_console = {
  89         .name =         "earlyprom",
  90         .write =        prom_console_write,
  91         .flags =        CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
  92         .index =        -1,
  93 };
  94
  95 /*
  96  * Process kernel command line switches that are specific to the
  97  * SPARC or that require special low-level processing.
  98  */
  99 static void __init process_switch(char c)
 100 {
 101         switch (c) {
 102         case 'd':
 103         case 's':
 104                 break;
 105         case 'h':
 106                 prom_printf("boot_flags_init: Halt!\n");
 107                 prom_halt();
 108                 break;
 109         case 'p':
 110                 prom_early_console.flags &= ~CON_BOOT;
 111                 break;
 112         case 'P':
 113                 /* Force UltraSPARC-III P-Cache on. */
 114                 if (tlb_type != cheetah) {
 115                         printk("BOOT: Ignoring P-Cache force option.\n");
 116                         break;
 117                 }
 118                 cheetah_pcache_forced_on = 1;
 119                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
 120                 cheetah_enable_pcache();
 121                 break;
 122
 123         default:
 124                 printk("Unknown boot switch (-%c)\n", c);
 125                 break;
 126         }
 127 }
 128
 129 static void __init boot_flags_init(char *commands)
 130 {
 131         while (*commands) {
 132                 /* Move to the start of the next "argument". */
 133                 while (*commands && *commands == ' ')
 134                         commands++;
 135
 136                 /* Process any command switches, otherwise skip it. */
 137                 if (*commands == '\0')
 138                         break;
 139                 if (*commands == '-') {
 140                         commands++;
 141                         while (*commands && *commands != ' ')
 142                                 process_switch(*commands++);
 143                         continue;
 144                 }
 145                 if (!strncmp(commands, "mem=", 4))
 146                         cmdline_memory_size = memparse(commands + 4, &commands);
 147
 148                 while (*commands && *commands != ' ')
 149                         commands++;
 150         }
 151 }
 152
 153 extern unsigned short root_flags;
 154 extern unsigned short root_dev;
 155 extern unsigned short ram_flags;
 156 #define RAMDISK_IMAGE_START_MASK        0x07FF
 157 #define RAMDISK_PROMPT_FLAG             0x8000
 158 #define RAMDISK_LOAD_FLAG               0x4000
 159
 160 extern int root_mountflags;
 161
 162 char reboot_command[COMMAND_LINE_SIZE];
 163
 164 static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
 165
 166 static void __init per_cpu_patch(void)
 167 {
 168         struct cpuid_patch_entry *p;
 169         unsigned long ver;
 170         int is_jbus;
 171
 172         if (tlb_type == spitfire && !this_is_starfire)
 173                 return;
 174
 175         is_jbus = 0;
 176         if (tlb_type != hypervisor) {
 177                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 178                 is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
 179                            (ver >> 32UL) == __SERRANO_ID);
 180         }
 181
 182         p = &__cpuid_patch;
 183         while (p < &__cpuid_patch_end) {
 184                 unsigned long addr = p->addr;
 185                 unsigned int *insns;
 186
 187                 switch (tlb_type) {
 188                 case spitfire:
 189                         insns = &p->starfire[0];
 190                         break;
 191                 case cheetah:
 192                 case cheetah_plus:
 193                         if (is_jbus)
 194                                 insns = &p->cheetah_jbus[0];
 195                         else
 196                                 insns = &p->cheetah_safari[0];
 197                         break;
 198                 case hypervisor:
 199                         insns = &p->sun4v[0];
 200                         break;
 201                 default:
 202                         prom_printf("Unknown cpu type, halting.\n");
 203                         prom_halt();
 204                 }
 205
 206                 *(unsigned int *) (addr +  0) = insns[0];
 207                 wmb();
 208                 __asm__ __volatile__("flush     %0" : : "r" (addr +  0));
 209
 210                 *(unsigned int *) (addr +  4) = insns[1];
 211                 wmb();
 212                 __asm__ __volatile__("flush     %0" : : "r" (addr +  4));
 213
 214                 *(unsigned int *) (addr +  8) = insns[2];
 215                 wmb();
 216                 __asm__ __volatile__("flush     %0" : : "r" (addr +  8));
 217
 218                 *(unsigned int *) (addr + 12) = insns[3];
 219                 wmb();
 220                 __asm__ __volatile__("flush     %0" : : "r" (addr + 12));
 221
 222                 p++;
 223         }
 224 }
 225
 226 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
 227                              struct sun4v_1insn_patch_entry *end)
 228 {
 229         while (start < end) {
 230                 unsigned long addr = start->addr;
 231
 232                 *(unsigned int *) (addr +  0) = start->insn;
 233                 wmb();
 234                 __asm__ __volatile__("flush     %0" : : "r" (addr +  0));
 235
 236                 start++;
 237         }
 238 }
 239
 240 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
 241                              struct sun4v_2insn_patch_entry *end)
 242 {
 243         while (start < end) {
 244                 unsigned long addr = start->addr;
 245
 246                 *(unsigned int *) (addr +  0) = start->insns[0];
 247                 wmb();
 248                 __asm__ __volatile__("flush     %0" : : "r" (addr +  0));
 249
 250                 *(unsigned int *) (addr +  4) = start->insns[1];
 251                 wmb();
 252                 __asm__ __volatile__("flush     %0" : : "r" (addr +  4));
 253
 254                 start++;
 255         }
 256 }
 257
 258 void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
 259                              struct sun4v_2insn_patch_entry *end)
 260 {
 261         while (start < end) {
 262                 unsigned long addr = start->addr;
 263
 264                 *(unsigned int *) (addr +  0) = start->insns[0];
 265                 wmb();
 266                 __asm__ __volatile__("flush     %0" : : "r" (addr +  0));
 267
 268                 *(unsigned int *) (addr +  4) = start->insns[1];
 269                 wmb();
 270                 __asm__ __volatile__("flush     %0" : : "r" (addr +  4));
 271
 272                 start++;
 273         }
 274 }
 275
 276 static void __init sun4v_patch(void)
 277 {
 278         extern void sun4v_hvapi_init(void);
 279
 280         if (tlb_type != hypervisor)
 281                 return;
 282
 283         sun4v_patch_1insn_range(&__sun4v_1insn_patch,
 284                                 &__sun4v_1insn_patch_end);
 285
 286         sun4v_patch_2insn_range(&__sun4v_2insn_patch,
 287                                 &__sun4v_2insn_patch_end);
 288         if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7)
 289                 sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
 290                                          &__sun_m7_2insn_patch_end);
 291
 292         sun4v_hvapi_init();
 293 }
 294
 295 static void __init popc_patch(void)
 296 {
 297         struct popc_3insn_patch_entry *p3;
 298         struct popc_6insn_patch_entry *p6;
 299
 300         p3 = &__popc_3insn_patch;
 301         while (p3 < &__popc_3insn_patch_end) {
 302                 unsigned long i, addr = p3->addr;
 303
 304                 for (i = 0; i < 3; i++) {
 305                         *(unsigned int *) (addr +  (i * 4)) = p3->insns[i];
 306                         wmb();
 307                         __asm__ __volatile__("flush     %0"
 308                                              : : "r" (addr +  (i * 4)));
 309                 }
 310
 311                 p3++;
 312         }
 313
 314         p6 = &__popc_6insn_patch;
 315         while (p6 < &__popc_6insn_patch_end) {
 316                 unsigned long i, addr = p6->addr;
 317
 318                 for (i = 0; i < 6; i++) {
 319                         *(unsigned int *) (addr +  (i * 4)) = p6->insns[i];
 320                         wmb();
 321                         __asm__ __volatile__("flush     %0"
 322                                              : : "r" (addr +  (i * 4)));
 323                 }
 324
 325                 p6++;
 326         }
 327 }
 328
 329 static void __init pause_patch(void)
 330 {
 331         struct pause_patch_entry *p;
 332
 333         p = &__pause_3insn_patch;
 334         while (p < &__pause_3insn_patch_end) {
 335                 unsigned long i, addr = p->addr;
 336
 337                 for (i = 0; i < 3; i++) {
 338                         *(unsigned int *) (addr +  (i * 4)) = p->insns[i];
 339                         wmb();
 340                         __asm__ __volatile__("flush     %0"
 341                                              : : "r" (addr +  (i * 4)));
 342                 }
 343
 344                 p++;
 345         }
 346 }
 347
 348 void __init start_early_boot(void)
 349 {
 350         int cpu;
 351
 352         check_if_starfire();
 353         per_cpu_patch();
 354         sun4v_patch();
 355
 356         cpu = hard_smp_processor_id();
 357         if (cpu >= NR_CPUS) {
 358                 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
 359                             cpu, NR_CPUS);
 360                 prom_halt();
 361         }
 362         current_thread_info()->cpu = cpu;
 363
 364         prom_init_report();
 365         start_kernel();
 366 }
 367
 368 /* On Ultra, we support all of the v8 capabilities. */
 369 unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
 370                                    HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
 371                                    HWCAP_SPARC_V9);
 372 EXPORT_SYMBOL(sparc64_elf_hwcap);
 373
 374 static const char *hwcaps[] = {
 375         "flush", "stbar", "swap", "muldiv", "v9",
 376         "ultra3", "blkinit", "n2",
 377
 378         /* These strings are as they appear in the machine description
 379          * 'hwcap-list' property for cpu nodes.
 380          */
 381         "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
 382         "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
 383         "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
 384         "adp",
 385 };
 386
 387 static const char *crypto_hwcaps[] = {
 388         "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
 389         "sha512", "mpmul", "montmul", "montsqr", "crc32c",
 390 };
 391
 392 void cpucap_info(struct seq_file *m)
 393 {
 394         unsigned long caps = sparc64_elf_hwcap;
 395         int i, printed = 0;
 396
 397         seq_puts(m, "cpucaps\t\t: ");
 398         for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
 399                 unsigned long bit = 1UL << i;
 400                 if (hwcaps[i] && (caps & bit)) {
 401                         seq_printf(m, "%s%s",
 402                                    printed ? "," : "", hwcaps[i]);
 403                         printed++;
 404                 }
 405         }
 406         if (caps & HWCAP_SPARC_CRYPTO) {
 407                 unsigned long cfr;
 408
 409                 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
 410                 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
 411                         unsigned long bit = 1UL << i;
 412                         if (cfr & bit) {
 413                                 seq_printf(m, "%s%s",
 414                                            printed ? "," : "", crypto_hwcaps[i]);
 415                                 printed++;
 416                         }
 417                 }
 418         }
 419         seq_putc(m, '\n');
 420 }
 421
 422 static void __init report_one_hwcap(int *printed, const char *name)
 423 {
 424         if ((*printed) == 0)
 425                 printk(KERN_INFO "CPU CAPS: [");
 426         printk(KERN_CONT "%s%s",
 427                (*printed) ? "," : "", name);
 428         if (++(*printed) == 8) {
 429                 printk(KERN_CONT "]\n");
 430                 *printed = 0;
 431         }
 432 }
 433
 434 static void __init report_crypto_hwcaps(int *printed)
 435 {
 436         unsigned long cfr;
 437         int i;
 438
 439         __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
 440
 441         for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
 442                 unsigned long bit = 1UL << i;
 443                 if (cfr & bit)
 444                         report_one_hwcap(printed, crypto_hwcaps[i]);
 445         }
 446 }
 447
 448 static void __init report_hwcaps(unsigned long caps)
 449 {
 450         int i, printed = 0;
 451
 452         for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
 453                 unsigned long bit = 1UL << i;
 454                 if (hwcaps[i] && (caps & bit))
 455                         report_one_hwcap(&printed, hwcaps[i]);
 456         }
 457         if (caps & HWCAP_SPARC_CRYPTO)
 458                 report_crypto_hwcaps(&printed);
 459         if (printed != 0)
 460                 printk(KERN_CONT "]\n");
 461 }
 462
 463 static unsigned long __init mdesc_cpu_hwcap_list(void)
 464 {
 465         struct mdesc_handle *hp;
 466         unsigned long caps = 0;
 467         const char *prop;
 468         int len;
 469         u64 pn;
 470
 471         hp = mdesc_grab();
 472         if (!hp)
 473                 return 0;
 474
 475         pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
 476         if (pn == MDESC_NODE_NULL)
 477                 goto out;
 478
 479         prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
 480         if (!prop)
 481                 goto out;
 482
 483         while (len) {
 484                 int i, plen;
 485
 486                 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
 487                         unsigned long bit = 1UL << i;
 488
 489                         if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
 490                                 caps |= bit;
 491                                 break;
 492                         }
 493                 }
 494                 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
 495                         if (!strcmp(prop, crypto_hwcaps[i]))
 496                                 caps |= HWCAP_SPARC_CRYPTO;
 497                 }
 498
 499                 plen = strlen(prop) + 1;
 500                 prop += plen;
 501                 len -= plen;
 502         }
 503
 504 out:
 505         mdesc_release(hp);
 506         return caps;
 507 }
 508
 509 /* This yields a mask that user programs can use to figure out what
 510  * instruction set this cpu supports.
 511  */
 512 static void __init init_sparc64_elf_hwcap(void)
 513 {
 514         unsigned long cap = sparc64_elf_hwcap;
 515         unsigned long mdesc_caps;
 516
 517         if (tlb_type == cheetah || tlb_type == cheetah_plus)
 518                 cap |= HWCAP_SPARC_ULTRA3;
 519         else if (tlb_type == hypervisor) {
 520                 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
 521                     sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
 522                     sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
 523                     sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
 524                     sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
 525                     sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
 526                     sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
 527                     sun4v_chip_type == SUN4V_CHIP_SPARC64X)
 528                         cap |= HWCAP_SPARC_BLKINIT;
 529                 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
 530                     sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
 531                     sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
 532                     sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
 533                     sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
 534                     sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
 535                     sun4v_chip_type == SUN4V_CHIP_SPARC64X)
 536                         cap |= HWCAP_SPARC_N2;
 537         }
 538
 539         cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
 540
 541         mdesc_caps = mdesc_cpu_hwcap_list();
 542         if (!mdesc_caps) {
 543                 if (tlb_type == spitfire)
 544                         cap |= AV_SPARC_VIS;
 545                 if (tlb_type == cheetah || tlb_type == cheetah_plus)
 546                         cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
 547                 if (tlb_type == cheetah_plus) {
 548                         unsigned long impl, ver;
 549
 550                         __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
 551                         impl = ((ver >> 32) & 0xffff);
 552                         if (impl == PANTHER_IMPL)
 553                                 cap |= AV_SPARC_POPC;
 554                 }
 555                 if (tlb_type == hypervisor) {
 556                         if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
 557                                 cap |= AV_SPARC_ASI_BLK_INIT;
 558                         if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
 559                             sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
 560                             sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
 561                             sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
 562                             sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
 563                             sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
 564                             sun4v_chip_type == SUN4V_CHIP_SPARC64X)
 565                                 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
 566                                         AV_SPARC_ASI_BLK_INIT |
 567                                         AV_SPARC_POPC);
 568                         if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
 569                             sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
 570                             sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
 571                             sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
 572                             sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
 573                             sun4v_chip_type == SUN4V_CHIP_SPARC64X)
 574                                 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
 575                                         AV_SPARC_FMAF);
 576                 }
 577         }
 578         sparc64_elf_hwcap = cap | mdesc_caps;
 579
 580         report_hwcaps(sparc64_elf_hwcap);
 581
 582         if (sparc64_elf_hwcap & AV_SPARC_POPC)
 583                 popc_patch();
 584         if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
 585                 pause_patch();
 586 }
 587
 588 void __init setup_arch(char **cmdline_p)
 589 {
 590         /* Initialize PROM console and command line. */
 591         *cmdline_p = prom_getbootargs();
 592         strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
 593         parse_early_param();
 594
 595         boot_flags_init(*cmdline_p);
 596 #ifdef CONFIG_EARLYFB
 597         if (btext_find_display())
 598 #endif
 599                 register_console(&prom_early_console);
 600
 601         if (tlb_type == hypervisor)
 602                 printk("ARCH: SUN4V\n");
 603         else
 604                 printk("ARCH: SUN4U\n");
 605
 606 #ifdef CONFIG_DUMMY_CONSOLE
 607         conswitchp = &dummy_con;
 608 #endif
 609
 610         idprom_init();
 611
 612         if (!root_flags)
 613                 root_mountflags &= ~MS_RDONLY;
 614         ROOT_DEV = old_decode_dev(root_dev);
 615 #ifdef CONFIG_BLK_DEV_RAM
 616         rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
 617         rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
 618         rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
 619 #endif
 620
 621         task_thread_info(&init_task)->kregs = &fake_swapper_regs;
 622
 623 #ifdef CONFIG_IP_PNP
 624         if (!ic_set_manually) {
 625                 phandle chosen = prom_finddevice("/chosen");
 626                 u32 cl, sv, gw;
 627
 628                 cl = prom_getintdefault (chosen, "client-ip", 0);
 629                 sv = prom_getintdefault (chosen, "server-ip", 0);
 630                 gw = prom_getintdefault (chosen, "gateway-ip", 0);
 631                 if (cl && sv) {
 632                         ic_myaddr = cl;
 633                         ic_servaddr = sv;
 634                         if (gw)
 635                                 ic_gateway = gw;
 636 #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
 637                         ic_proto_enabled = 0;
 638 #endif
 639                 }
 640         }
 641 #endif
 642
 643         /* Get boot processor trap_block[] setup.  */
 644         init_cur_cpu_trap(current_thread_info());
 645
 646         paging_init();
 647         init_sparc64_elf_hwcap();
 648 }
 649
 650 extern int stop_a_enabled;
 651
 652 void sun_do_break(void)
 653 {
 654         if (!stop_a_enabled)
 655                 return;
 656
 657         prom_printf("\n");
 658         flush_user_windows();
 659
 660         prom_cmdline();
 661 }
 662 EXPORT_SYMBOL(sun_do_break);
 663
 664 int stop_a_enabled = 1;
 665 EXPORT_SYMBOL(stop_a_enabled);