drivers/scsi/pm8001/pm80xx_hwi.h

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions, and the following disclaimer,
  12  *      without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *      substantially similar to the "NO WARRANTY" disclaimer below
  15  *      ("Disclaimer") and any redistribution must be conditioned upon
  16  *      including a substantially similar Disclaimer requirement for further
  17  *      binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *      of any contributors may be used to endorse or promote products derived
  20  *      from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #ifndef _PMC8001_REG_H_
  42 #define _PMC8001_REG_H_
  43
  44 #include <linux/types.h>
  45 #include <scsi/libsas.h>
  46
  47 /* for Request Opcode of IOMB */
  48 #define OPC_INB_ECHO                            1       /* 0x000 */
  49 #define OPC_INB_PHYSTART                        4       /* 0x004 */
  50 #define OPC_INB_PHYSTOP                         5       /* 0x005 */
  51 #define OPC_INB_SSPINIIOSTART                   6       /* 0x006 */
  52 #define OPC_INB_SSPINITMSTART                   7       /* 0x007 */
  53 /* 0x8 RESV IN SPCv */
  54 #define OPC_INB_RSVD                            8       /* 0x008 */
  55 #define OPC_INB_DEV_HANDLE_ACCEPT               9       /* 0x009 */
  56 #define OPC_INB_SSPTGTIOSTART                   10      /* 0x00A */
  57 #define OPC_INB_SSPTGTRSPSTART                  11      /* 0x00B */
  58 /* 0xC, 0xD, 0xE removed in SPCv */
  59 #define OPC_INB_SSP_ABORT                       15      /* 0x00F */
  60 #define OPC_INB_DEREG_DEV_HANDLE                16      /* 0x010 */
  61 #define OPC_INB_GET_DEV_HANDLE                  17      /* 0x011 */
  62 #define OPC_INB_SMP_REQUEST                     18      /* 0x012 */
  63 /* 0x13 SMP_RESPONSE is removed in SPCv */
  64 #define OPC_INB_SMP_ABORT                       20      /* 0x014 */
  65 /* 0x16 RESV IN SPCv */
  66 #define OPC_INB_RSVD1                           22      /* 0x016 */
  67 #define OPC_INB_SATA_HOST_OPSTART               23      /* 0x017 */
  68 #define OPC_INB_SATA_ABORT                      24      /* 0x018 */
  69 #define OPC_INB_LOCAL_PHY_CONTROL               25      /* 0x019 */
  70 /* 0x1A RESV IN SPCv */
  71 #define OPC_INB_RSVD2                           26      /* 0x01A */
  72 #define OPC_INB_FW_FLASH_UPDATE                 32      /* 0x020 */
  73 #define OPC_INB_GPIO                            34      /* 0x022 */
  74 #define OPC_INB_SAS_DIAG_MODE_START_END         35      /* 0x023 */
  75 #define OPC_INB_SAS_DIAG_EXECUTE                36      /* 0x024 */
  76 /* 0x25 RESV IN SPCv */
  77 #define OPC_INB_RSVD3                           37      /* 0x025 */
  78 #define OPC_INB_GET_TIME_STAMP                  38      /* 0x026 */
  79 #define OPC_INB_PORT_CONTROL                    39      /* 0x027 */
  80 #define OPC_INB_GET_NVMD_DATA                   40      /* 0x028 */
  81 #define OPC_INB_SET_NVMD_DATA                   41      /* 0x029 */
  82 #define OPC_INB_SET_DEVICE_STATE                42      /* 0x02A */
  83 #define OPC_INB_GET_DEVICE_STATE                43      /* 0x02B */
  84 #define OPC_INB_SET_DEV_INFO                    44      /* 0x02C */
  85 /* 0x2D RESV IN SPCv */
  86 #define OPC_INB_RSVD4                           45      /* 0x02D */
  87 #define OPC_INB_SGPIO_REGISTER                  46      /* 0x02E */
  88 #define OPC_INB_PCIE_DIAG_EXEC                  47      /* 0x02F */
  89 #define OPC_INB_SET_CONTROLLER_CONFIG           48      /* 0x030 */
  90 #define OPC_INB_GET_CONTROLLER_CONFIG           49      /* 0x031 */
  91 #define OPC_INB_REG_DEV                         50      /* 0x032 */
  92 #define OPC_INB_SAS_HW_EVENT_ACK                51      /* 0x033 */
  93 #define OPC_INB_GET_DEVICE_INFO                 52      /* 0x034 */
  94 #define OPC_INB_GET_PHY_PROFILE                 53      /* 0x035 */
  95 #define OPC_INB_FLASH_OP_EXT                    54      /* 0x036 */
  96 #define OPC_INB_SET_PHY_PROFILE                 55      /* 0x037 */
  97 #define OPC_INB_KEK_MANAGEMENT                  256     /* 0x100 */
  98 #define OPC_INB_DEK_MANAGEMENT                  257     /* 0x101 */
  99 #define OPC_INB_SSP_INI_DIF_ENC_IO              258     /* 0x102 */
 100 #define OPC_INB_SATA_DIF_ENC_IO                 259     /* 0x103 */
 101
 102 /* for Response Opcode of IOMB */
 103 #define OPC_OUB_ECHO                                    1       /* 0x001 */
 104 #define OPC_OUB_RSVD                                    4       /* 0x004 */
 105 #define OPC_OUB_SSP_COMP                                5       /* 0x005 */
 106 #define OPC_OUB_SMP_COMP                                6       /* 0x006 */
 107 #define OPC_OUB_LOCAL_PHY_CNTRL                         7       /* 0x007 */
 108 #define OPC_OUB_RSVD1                                   10      /* 0x00A */
 109 #define OPC_OUB_DEREG_DEV                               11      /* 0x00B */
 110 #define OPC_OUB_GET_DEV_HANDLE                          12      /* 0x00C */
 111 #define OPC_OUB_SATA_COMP                               13      /* 0x00D */
 112 #define OPC_OUB_SATA_EVENT                              14      /* 0x00E */
 113 #define OPC_OUB_SSP_EVENT                               15      /* 0x00F */
 114 #define OPC_OUB_RSVD2                                   16      /* 0x010 */
 115 /* 0x11 - SMP_RECEIVED Notification removed in SPCv*/
 116 #define OPC_OUB_SSP_RECV_EVENT                          18      /* 0x012 */
 117 #define OPC_OUB_RSVD3                                   19      /* 0x013 */
 118 #define OPC_OUB_FW_FLASH_UPDATE                         20      /* 0x014 */
 119 #define OPC_OUB_GPIO_RESPONSE                           22      /* 0x016 */
 120 #define OPC_OUB_GPIO_EVENT                              23      /* 0x017 */
 121 #define OPC_OUB_GENERAL_EVENT                           24      /* 0x018 */
 122 #define OPC_OUB_SSP_ABORT_RSP                           26      /* 0x01A */
 123 #define OPC_OUB_SATA_ABORT_RSP                          27      /* 0x01B */
 124 #define OPC_OUB_SAS_DIAG_MODE_START_END                 28      /* 0x01C */
 125 #define OPC_OUB_SAS_DIAG_EXECUTE                        29      /* 0x01D */
 126 #define OPC_OUB_GET_TIME_STAMP                          30      /* 0x01E */
 127 #define OPC_OUB_RSVD4                                   31      /* 0x01F */
 128 #define OPC_OUB_PORT_CONTROL                            32      /* 0x020 */
 129 #define OPC_OUB_SKIP_ENTRY                              33      /* 0x021 */
 130 #define OPC_OUB_SMP_ABORT_RSP                           34      /* 0x022 */
 131 #define OPC_OUB_GET_NVMD_DATA                           35      /* 0x023 */
 132 #define OPC_OUB_SET_NVMD_DATA                           36      /* 0x024 */
 133 #define OPC_OUB_DEVICE_HANDLE_REMOVAL                   37      /* 0x025 */
 134 #define OPC_OUB_SET_DEVICE_STATE                        38      /* 0x026 */
 135 #define OPC_OUB_GET_DEVICE_STATE                        39      /* 0x027 */
 136 #define OPC_OUB_SET_DEV_INFO                            40      /* 0x028 */
 137 #define OPC_OUB_RSVD5                                   41      /* 0x029 */
 138 #define OPC_OUB_HW_EVENT                                1792    /* 0x700 */
 139 #define OPC_OUB_DEV_HANDLE_ARRIV                        1824    /* 0x720 */
 140 #define OPC_OUB_THERM_HW_EVENT                          1840    /* 0x730 */
 141 #define OPC_OUB_SGPIO_RESP                              2094    /* 0x82E */
 142 #define OPC_OUB_PCIE_DIAG_EXECUTE                       2095    /* 0x82F */
 143 #define OPC_OUB_DEV_REGIST                              2098    /* 0x832 */
 144 #define OPC_OUB_SAS_HW_EVENT_ACK                        2099    /* 0x833 */
 145 #define OPC_OUB_GET_DEVICE_INFO                         2100    /* 0x834 */
 146 /* spcv specific commands */
 147 #define OPC_OUB_PHY_START_RESP                          2052    /* 0x804 */
 148 #define OPC_OUB_PHY_STOP_RESP                           2053    /* 0x805 */
 149 #define OPC_OUB_SET_CONTROLLER_CONFIG                   2096    /* 0x830 */
 150 #define OPC_OUB_GET_CONTROLLER_CONFIG                   2097    /* 0x831 */
 151 #define OPC_OUB_GET_PHY_PROFILE                         2101    /* 0x835 */
 152 #define OPC_OUB_FLASH_OP_EXT                            2102    /* 0x836 */
 153 #define OPC_OUB_SET_PHY_PROFILE                         2103    /* 0x837 */
 154 #define OPC_OUB_KEK_MANAGEMENT_RESP                     2304    /* 0x900 */
 155 #define OPC_OUB_DEK_MANAGEMENT_RESP                     2305    /* 0x901 */
 156 #define OPC_OUB_SSP_COALESCED_COMP_RESP                 2306    /* 0x902 */
 157
 158 /* for phy start*/
 159 #define SSC_DISABLE_15                  (0x01 << 16)
 160 #define SSC_DISABLE_30                  (0x02 << 16)
 161 #define SSC_DISABLE_60                  (0x04 << 16)
 162 #define SAS_ASE                         (0x01 << 15)
 163 #define SPINHOLD_DISABLE                (0x00 << 14)
 164 #define SPINHOLD_ENABLE                 (0x01 << 14)
 165 #define LINKMODE_SAS                    (0x01 << 12)
 166 #define LINKMODE_DSATA                  (0x02 << 12)
 167 #define LINKMODE_AUTO                   (0x03 << 12)
 168 #define LINKRATE_15                     (0x01 << 8)
 169 #define LINKRATE_30                     (0x02 << 8)
 170 #define LINKRATE_60                     (0x06 << 8)
 171 #define LINKRATE_120                    (0x08 << 8)
 172
 173 /* phy_profile */
 174 #define SAS_PHY_ANALOG_SETTINGS_PAGE    0x04
 175 #define PHY_DWORD_LENGTH                0xC
 176
 177 /* Thermal related */
 178 #define THERMAL_ENABLE                  0x1
 179 #define THERMAL_LOG_ENABLE              0x1
 180 #define THERMAL_OP_CODE                 0x6
 181 #define LTEMPHIL                         70
 182 #define RTEMPHIL                        100
 183
 184 /* Encryption info */
 185 #define SCRATCH_PAD3_ENC_DISABLED       0x00000000
 186 #define SCRATCH_PAD3_ENC_DIS_ERR        0x00000001
 187 #define SCRATCH_PAD3_ENC_ENA_ERR        0x00000002
 188 #define SCRATCH_PAD3_ENC_READY          0x00000003
 189 #define SCRATCH_PAD3_ENC_MASK           SCRATCH_PAD3_ENC_READY
 190
 191 #define SCRATCH_PAD3_XTS_ENABLED                (1 << 14)
 192 #define SCRATCH_PAD3_SMA_ENABLED                (1 << 4)
 193 #define SCRATCH_PAD3_SMB_ENABLED                (1 << 5)
 194 #define SCRATCH_PAD3_SMF_ENABLED                0
 195 #define SCRATCH_PAD3_SM_MASK                    0x000000F0
 196 #define SCRATCH_PAD3_ERR_CODE                   0x00FF0000
 197
 198 #define SEC_MODE_SMF                            0x0
 199 #define SEC_MODE_SMA                            0x100
 200 #define SEC_MODE_SMB                            0x200
 201 #define CIPHER_MODE_ECB                         0x00000001
 202 #define CIPHER_MODE_XTS                         0x00000002
 203 #define KEK_MGMT_SUBOP_KEYCARDUPDATE            0x4
 204
 205 /* SAS protocol timer configuration page */
 206 #define SAS_PROTOCOL_TIMER_CONFIG_PAGE  0x04
 207 #define STP_MCT_TMO                     32
 208 #define SSP_MCT_TMO                     32
 209 #define SAS_MAX_OPEN_TIME                               5
 210 #define SMP_MAX_CONN_TIMER              0xFF
 211 #define STP_FRM_TIMER                   0
 212 #define STP_IDLE_TIME                   5 /* 5 us; controller default */
 213 #define SAS_MFD                         0
 214 #define SAS_OPNRJT_RTRY_INTVL           2
 215 #define SAS_DOPNRJT_RTRY_TMO            128
 216 #define SAS_COPNRJT_RTRY_TMO            128
 217
 218 /*
 219   Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second.
 220   Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128
 221   is DOPNRJT_RTRY_TMO
 222 */
 223 #define SAS_DOPNRJT_RTRY_THR            23438
 224 #define SAS_COPNRJT_RTRY_THR            23438
 225 #define SAS_MAX_AIP                     0x200000
 226 #define IT_NEXUS_TIMEOUT       0x7D0
 227 #define PORT_RECOVERY_TIMEOUT  ((IT_NEXUS_TIMEOUT/100) + 30)
 228
 229 struct mpi_msg_hdr {
 230         __le32  header; /* Bits [11:0] - Message operation code */
 231         /* Bits [15:12] - Message Category */
 232         /* Bits [21:16] - Outboundqueue ID for the
 233         operation completion message */
 234         /* Bits [23:22] - Reserved */
 235         /* Bits [28:24] - Buffer Count, indicates how
 236         many buffer are allocated for the massage */
 237         /* Bits [30:29] - Reserved */
 238         /* Bits [31] - Message Valid bit */
 239 } __attribute__((packed, aligned(4)));
 240
 241 /*
 242  * brief the data structure of PHY Start Command
 243  * use to describe enable the phy (128 bytes)
 244  */
 245 struct phy_start_req {
 246         __le32  tag;
 247         __le32  ase_sh_lm_slr_phyid;
 248         struct sas_identify_frame sas_identify; /* 28 Bytes */
 249         __le32 spasti;
 250         u32     reserved[21];
 251 } __attribute__((packed, aligned(4)));
 252
 253 /*
 254  * brief the data structure of PHY Start Command
 255  * use to disable the phy (128 bytes)
 256  */
 257 struct phy_stop_req {
 258         __le32  tag;
 259         __le32  phy_id;
 260         u32     reserved[29];
 261 } __attribute__((packed, aligned(4)));
 262
 263 /* set device bits fis - device to host */
 264 struct set_dev_bits_fis {
 265         u8      fis_type;       /* 0xA1*/
 266         u8      n_i_pmport;
 267         /* b7 : n Bit. Notification bit. If set device needs attention. */
 268         /* b6 : i Bit. Interrupt Bit */
 269         /* b5-b4: reserved2 */
 270         /* b3-b0: PM Port */
 271         u8      status;
 272         u8      error;
 273         u32     _r_a;
 274 } __attribute__ ((packed));
 275 /* PIO setup FIS - device to host */
 276 struct pio_setup_fis {
 277         u8      fis_type;       /* 0x5f */
 278         u8      i_d_pmPort;
 279         /* b7 : reserved */
 280         /* b6 : i bit. Interrupt bit */
 281         /* b5 : d bit. data transfer direction. set to 1 for device to host
 282         xfer */
 283         /* b4 : reserved */
 284         /* b3-b0: PM Port */
 285         u8      status;
 286         u8      error;
 287         u8      lbal;
 288         u8      lbam;
 289         u8      lbah;
 290         u8      device;
 291         u8      lbal_exp;
 292         u8      lbam_exp;
 293         u8      lbah_exp;
 294         u8      _r_a;
 295         u8      sector_count;
 296         u8      sector_count_exp;
 297         u8      _r_b;
 298         u8      e_status;
 299         u8      _r_c[2];
 300         u8      transfer_count;
 301 } __attribute__ ((packed));
 302
 303 /*
 304  * brief the data structure of SATA Completion Response
 305  * use to describe the sata task response (64 bytes)
 306  */
 307 struct sata_completion_resp {
 308         __le32  tag;
 309         __le32  status;
 310         __le32  param;
 311         u32     sata_resp[12];
 312 } __attribute__((packed, aligned(4)));
 313
 314 /*
 315  * brief the data structure of SAS HW Event Notification
 316  * use to alert the host about the hardware event(64 bytes)
 317  */
 318 /* updated outbound struct for spcv */
 319
 320 struct hw_event_resp {
 321         __le32  lr_status_evt_portid;
 322         __le32  evt_param;
 323         __le32  phyid_npip_portstate;
 324         struct sas_identify_frame       sas_identify;
 325         struct dev_to_host_fis  sata_fis;
 326 } __attribute__((packed, aligned(4)));
 327
 328 /*
 329  * brief the data structure for thermal event notification
 330  */
 331
 332 struct thermal_hw_event {
 333         __le32  thermal_event;
 334         __le32  rht_lht;
 335 } __attribute__((packed, aligned(4)));
 336
 337 /*
 338  * brief the data structure of REGISTER DEVICE Command
 339  * use to describe MPI REGISTER DEVICE Command (64 bytes)
 340  */
 341
 342 struct reg_dev_req {
 343         __le32  tag;
 344         __le32  phyid_portid;
 345         __le32  dtype_dlr_mcn_ir_retry;
 346         __le32  firstburstsize_ITNexustimeout;
 347         u8      sas_addr[SAS_ADDR_SIZE];
 348         __le32  upper_device_id;
 349         u32     reserved[24];
 350 } __attribute__((packed, aligned(4)));
 351
 352 /*
 353  * brief the data structure of DEREGISTER DEVICE Command
 354  * use to request spc to remove all internal resources associated
 355  * with the device id (64 bytes)
 356  */
 357
 358 struct dereg_dev_req {
 359         __le32  tag;
 360         __le32  device_id;
 361         u32     reserved[29];
 362 } __attribute__((packed, aligned(4)));
 363
 364 /*
 365  * brief the data structure of DEVICE_REGISTRATION Response
 366  * use to notify the completion of the device registration (64 bytes)
 367  */
 368 struct dev_reg_resp {
 369         __le32  tag;
 370         __le32  status;
 371         __le32  device_id;
 372         u32     reserved[12];
 373 } __attribute__((packed, aligned(4)));
 374
 375 /*
 376  * brief the data structure of Local PHY Control Command
 377  * use to issue PHY CONTROL to local phy (64 bytes)
 378  */
 379 struct local_phy_ctl_req {
 380         __le32  tag;
 381         __le32  phyop_phyid;
 382         u32     reserved1[29];
 383 } __attribute__((packed, aligned(4)));
 384
 385 /**
 386  * brief the data structure of Local Phy Control Response
 387  * use to describe MPI Local Phy Control Response (64 bytes)
 388  */
 389  struct local_phy_ctl_resp {
 390         __le32  tag;
 391         __le32  phyop_phyid;
 392         __le32  status;
 393         u32     reserved[12];
 394 } __attribute__((packed, aligned(4)));
 395
 396 #define OP_BITS 0x0000FF00
 397 #define ID_BITS 0x000000FF
 398
 399 /*
 400  * brief the data structure of PORT Control Command
 401  * use to control port properties (64 bytes)
 402  */
 403
 404 struct port_ctl_req {
 405         __le32  tag;
 406         __le32  portop_portid;
 407         __le32  param0;
 408         __le32  param1;
 409         u32     reserved1[27];
 410 } __attribute__((packed, aligned(4)));
 411
 412 /*
 413  * brief the data structure of HW Event Ack Command
 414  * use to acknowledge receive HW event (64 bytes)
 415  */
 416 struct hw_event_ack_req {
 417         __le32  tag;
 418         __le32  phyid_sea_portid;
 419         __le32  param0;
 420         __le32  param1;
 421         u32     reserved1[27];
 422 } __attribute__((packed, aligned(4)));
 423
 424 /*
 425  * brief the data structure of PHY_START Response Command
 426  * indicates the completion of PHY_START command (64 bytes)
 427  */
 428 struct phy_start_resp {
 429         __le32  tag;
 430         __le32  status;
 431         __le32  phyid;
 432         u32     reserved[12];
 433 } __attribute__((packed, aligned(4)));
 434
 435 /*
 436  * brief the data structure of PHY_STOP Response Command
 437  * indicates the completion of PHY_STOP command (64 bytes)
 438  */
 439 struct phy_stop_resp {
 440         __le32  tag;
 441         __le32  status;
 442         __le32  phyid;
 443         u32     reserved[12];
 444 } __attribute__((packed, aligned(4)));
 445
 446 /*
 447  * brief the data structure of SSP Completion Response
 448  * use to indicate a SSP Completion (n bytes)
 449  */
 450 struct ssp_completion_resp {
 451         __le32  tag;
 452         __le32  status;
 453         __le32  param;
 454         __le32  ssptag_rescv_rescpad;
 455         struct ssp_response_iu ssp_resp_iu;
 456         __le32  residual_count;
 457 } __attribute__((packed, aligned(4)));
 458
 459 #define SSP_RESCV_BIT   0x00010000
 460
 461 /*
 462  * brief the data structure of SATA EVNET response
 463  * use to indicate a SATA Completion (64 bytes)
 464  */
 465 struct sata_event_resp {
 466         __le32 tag;
 467         __le32 event;
 468         __le32 port_id;
 469         __le32 device_id;
 470         u32 reserved;
 471         __le32 event_param0;
 472         __le32 event_param1;
 473         __le32 sata_addr_h32;
 474         __le32 sata_addr_l32;
 475         __le32 e_udt1_udt0_crc;
 476         __le32 e_udt5_udt4_udt3_udt2;
 477         __le32 a_udt1_udt0_crc;
 478         __le32 a_udt5_udt4_udt3_udt2;
 479         __le32 hwdevid_diferr;
 480         __le32 err_framelen_byteoffset;
 481         __le32 err_dataframe;
 482 } __attribute__((packed, aligned(4)));
 483
 484 /*
 485  * brief the data structure of SSP EVNET esponse
 486  * use to indicate a SSP Completion (64 bytes)
 487  */
 488 struct ssp_event_resp {
 489         __le32 tag;
 490         __le32 event;
 491         __le32 port_id;
 492         __le32 device_id;
 493         __le32 ssp_tag;
 494         __le32 event_param0;
 495         __le32 event_param1;
 496         __le32 sas_addr_h32;
 497         __le32 sas_addr_l32;
 498         __le32 e_udt1_udt0_crc;
 499         __le32 e_udt5_udt4_udt3_udt2;
 500         __le32 a_udt1_udt0_crc;
 501         __le32 a_udt5_udt4_udt3_udt2;
 502         __le32 hwdevid_diferr;
 503         __le32 err_framelen_byteoffset;
 504         __le32 err_dataframe;
 505 } __attribute__((packed, aligned(4)));
 506
 507 /**
 508  * brief the data structure of General Event Notification Response
 509  * use to describe MPI General Event Notification Response (64 bytes)
 510  */
 511 struct general_event_resp {
 512         __le32  status;
 513         __le32  inb_IOMB_payload[14];
 514 } __attribute__((packed, aligned(4)));
 515
 516 #define GENERAL_EVENT_PAYLOAD   14
 517 #define OPCODE_BITS     0x00000fff
 518
 519 /*
 520  * brief the data structure of SMP Request Command
 521  * use to describe MPI SMP REQUEST Command (64 bytes)
 522  */
 523 struct smp_req {
 524         __le32  tag;
 525         __le32  device_id;
 526         __le32  len_ip_ir;
 527         /* Bits [0] - Indirect response */
 528         /* Bits [1] - Indirect Payload */
 529         /* Bits [15:2] - Reserved */
 530         /* Bits [23:16] - direct payload Len */
 531         /* Bits [31:24] - Reserved */
 532         u8      smp_req16[16];
 533         union {
 534                 u8      smp_req[32];
 535                 struct {
 536                         __le64 long_req_addr;/* sg dma address, LE */
 537                         __le32 long_req_size;/* LE */
 538                         u32     _r_a;
 539                         __le64 long_resp_addr;/* sg dma address, LE */
 540                         __le32 long_resp_size;/* LE */
 541                         u32     _r_b;
 542                         } long_smp_req;/* sequencer extension */
 543         };
 544         __le32  rsvd[16];
 545 } __attribute__((packed, aligned(4)));
 546 /*
 547  * brief the data structure of SMP Completion Response
 548  * use to describe MPI SMP Completion Response (64 bytes)
 549  */
 550 struct smp_completion_resp {
 551         __le32  tag;
 552         __le32  status;
 553         __le32  param;
 554         u8      _r_a[252];
 555 } __attribute__((packed, aligned(4)));
 556
 557 /*
 558  *brief the data structure of SSP SMP SATA Abort Command
 559  * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
 560  */
 561 struct task_abort_req {
 562         __le32  tag;
 563         __le32  device_id;
 564         __le32  tag_to_abort;
 565         __le32  abort_all;
 566         u32     reserved[27];
 567 } __attribute__((packed, aligned(4)));
 568
 569 /* These flags used for SSP SMP & SATA Abort */
 570 #define ABORT_MASK              0x3
 571 #define ABORT_SINGLE            0x0
 572 #define ABORT_ALL               0x1
 573
 574 /**
 575  * brief the data structure of SSP SATA SMP Abort Response
 576  * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
 577  */
 578 struct task_abort_resp {
 579         __le32  tag;
 580         __le32  status;
 581         __le32  scp;
 582         u32     reserved[12];
 583 } __attribute__((packed, aligned(4)));
 584
 585 /**
 586  * brief the data structure of SAS Diagnostic Start/End Command
 587  * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
 588  */
 589 struct sas_diag_start_end_req {
 590         __le32  tag;
 591         __le32  operation_phyid;
 592         u32     reserved[29];
 593 } __attribute__((packed, aligned(4)));
 594
 595 /**
 596  * brief the data structure of SAS Diagnostic Execute Command
 597  * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
 598  */
 599 struct sas_diag_execute_req {
 600         __le32  tag;
 601         __le32  cmdtype_cmddesc_phyid;
 602         __le32  pat1_pat2;
 603         __le32  threshold;
 604         __le32  codepat_errmsk;
 605         __le32  pmon;
 606         __le32  pERF1CTL;
 607         u32     reserved[24];
 608 } __attribute__((packed, aligned(4)));
 609
 610 #define SAS_DIAG_PARAM_BYTES 24
 611
 612 /*
 613  * brief the data structure of Set Device State Command
 614  * use to describe MPI Set Device State Command (64 bytes)
 615  */
 616 struct set_dev_state_req {
 617         __le32  tag;
 618         __le32  device_id;
 619         __le32  nds;
 620         u32     reserved[28];
 621 } __attribute__((packed, aligned(4)));
 622
 623 /*
 624  * brief the data structure of SATA Start Command
 625  * use to describe MPI SATA IO Start Command (64 bytes)
 626  * Note: This structure is common for normal / encryption I/O
 627  */
 628
 629 struct sata_start_req {
 630         __le32  tag;
 631         __le32  device_id;
 632         __le32  data_len;
 633         __le32  ncqtag_atap_dir_m_dad;
 634         struct host_to_dev_fis  sata_fis;
 635         u32     reserved1;
 636         u32     reserved2;      /* dword 11. rsvd for normal I/O. */
 637                                 /* EPLE Descl for enc I/O */
 638         u32     addr_low;       /* dword 12. rsvd for enc I/O */
 639         u32     addr_high;      /* dword 13. reserved for enc I/O */
 640         __le32  len;            /* dword 14: length for normal I/O. */
 641                                 /* EPLE Desch for enc I/O */
 642         __le32  esgl;           /* dword 15. rsvd for enc I/O */
 643         __le32  atapi_scsi_cdb[4];      /* dword 16-19. rsvd for enc I/O */
 644         /* The below fields are reserved for normal I/O */
 645         __le32  key_index_mode; /* dword 20 */
 646         __le32  sector_cnt_enss;/* dword 21 */
 647         __le32  keytagl;        /* dword 22 */
 648         __le32  keytagh;        /* dword 23 */
 649         __le32  twk_val0;       /* dword 24 */
 650         __le32  twk_val1;       /* dword 25 */
 651         __le32  twk_val2;       /* dword 26 */
 652         __le32  twk_val3;       /* dword 27 */
 653         __le32  enc_addr_low;   /* dword 28. Encryption SGL address high */
 654         __le32  enc_addr_high;  /* dword 29. Encryption SGL address low */
 655         __le32  enc_len;        /* dword 30. Encryption length */
 656         __le32  enc_esgl;       /* dword 31. Encryption esgl bit */
 657 } __attribute__((packed, aligned(4)));
 658
 659 /**
 660  * brief the data structure of SSP INI TM Start Command
 661  * use to describe MPI SSP INI TM Start Command (64 bytes)
 662  */
 663 struct ssp_ini_tm_start_req {
 664         __le32  tag;
 665         __le32  device_id;
 666         __le32  relate_tag;
 667         __le32  tmf;
 668         u8      lun[8];
 669         __le32  ds_ads_m;
 670         u32     reserved[24];
 671 } __attribute__((packed, aligned(4)));
 672
 673 struct ssp_info_unit {
 674         u8      lun[8];/* SCSI Logical Unit Number */
 675         u8      reserved1;/* reserved */
 676         u8      efb_prio_attr;
 677         /* B7 : enabledFirstBurst */
 678         /* B6-3 : taskPriority */
 679         /* B2-0 : taskAttribute */
 680         u8      reserved2;      /* reserved */
 681         u8      additional_cdb_len;
 682         /* B7-2 : additional_cdb_len */
 683         /* B1-0 : reserved */
 684         u8      cdb[16];/* The SCSI CDB up to 16 bytes length */
 685 } __attribute__((packed, aligned(4)));
 686
 687 /**
 688  * brief the data structure of SSP INI IO Start Command
 689  * use to describe MPI SSP INI IO Start Command (64 bytes)
 690  * Note: This structure is common for normal / encryption I/O
 691  */
 692 struct ssp_ini_io_start_req {
 693         __le32  tag;
 694         __le32  device_id;
 695         __le32  data_len;
 696         __le32  dad_dir_m_tlr;
 697         struct ssp_info_unit    ssp_iu;
 698         __le32  addr_low;       /* dword 12: sgl low for normal I/O. */
 699                                 /* epl_descl for encryption I/O */
 700         __le32  addr_high;      /* dword 13: sgl hi for normal I/O */
 701                                 /* dpl_descl for encryption I/O */
 702         __le32  len;            /* dword 14: len for normal I/O. */
 703                                 /* edpl_desch for encryption I/O */
 704         __le32  esgl;           /* dword 15: ESGL bit for normal I/O. */
 705                                 /* user defined tag mask for enc I/O */
 706         /* The below fields are reserved for normal I/O */
 707         u8      udt[12];        /* dword 16-18 */
 708         __le32  sectcnt_ios;    /* dword 19 */
 709         __le32  key_cmode;      /* dword 20 */
 710         __le32  ks_enss;        /* dword 21 */
 711         __le32  keytagl;        /* dword 22 */
 712         __le32  keytagh;        /* dword 23 */
 713         __le32  twk_val0;       /* dword 24 */
 714         __le32  twk_val1;       /* dword 25 */
 715         __le32  twk_val2;       /* dword 26 */
 716         __le32  twk_val3;       /* dword 27 */
 717         __le32  enc_addr_low;   /* dword 28: Encryption sgl addr low */
 718         __le32  enc_addr_high;  /* dword 29: Encryption sgl addr hi */
 719         __le32  enc_len;        /* dword 30: Encryption length */
 720         __le32  enc_esgl;       /* dword 31: ESGL bit for encryption */
 721 } __attribute__((packed, aligned(4)));
 722
 723 /**
 724  * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND
 725  * use to initiate SSP I/O operation with optional DIF/ENC
 726  */
 727 struct ssp_dif_enc_io_req {
 728         __le32  tag;
 729         __le32  device_id;
 730         __le32  data_len;
 731         __le32  dirMTlr;
 732         __le32  sspiu0;
 733         __le32  sspiu1;
 734         __le32  sspiu2;
 735         __le32  sspiu3;
 736         __le32  sspiu4;
 737         __le32  sspiu5;
 738         __le32  sspiu6;
 739         __le32  epl_des;
 740         __le32  dpl_desl_ndplr;
 741         __le32  dpl_desh;
 742         __le32  uum_uuv_bss_difbits;
 743         u8      udt[12];
 744         __le32  sectcnt_ios;
 745         __le32  key_cmode;
 746         __le32  ks_enss;
 747         __le32  keytagl;
 748         __le32  keytagh;
 749         __le32  twk_val0;
 750         __le32  twk_val1;
 751         __le32  twk_val2;
 752         __le32  twk_val3;
 753         __le32  addr_low;
 754         __le32  addr_high;
 755         __le32  len;
 756         __le32  esgl;
 757 } __attribute__((packed, aligned(4)));
 758
 759 /**
 760  * brief the data structure of Firmware download
 761  * use to describe MPI FW DOWNLOAD Command (64 bytes)
 762  */
 763 struct fw_flash_Update_req {
 764         __le32  tag;
 765         __le32  cur_image_offset;
 766         __le32  cur_image_len;
 767         __le32  total_image_len;
 768         u32     reserved0[7];
 769         __le32  sgl_addr_lo;
 770         __le32  sgl_addr_hi;
 771         __le32  len;
 772         __le32  ext_reserved;
 773         u32     reserved1[16];
 774 } __attribute__((packed, aligned(4)));
 775
 776 #define FWFLASH_IOMB_RESERVED_LEN 0x07
 777 /**
 778  * brief the data structure of FW_FLASH_UPDATE Response
 779  * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
 780  *
 781  */
 782  struct fw_flash_Update_resp {
 783         __le32  tag;
 784         __le32  status;
 785         u32     reserved[13];
 786 } __attribute__((packed, aligned(4)));
 787
 788 /**
 789  * brief the data structure of Get NVM Data Command
 790  * use to get data from NVM in HBA(64 bytes)
 791  */
 792 struct get_nvm_data_req {
 793         __le32  tag;
 794         __le32  len_ir_vpdd;
 795         __le32  vpd_offset;
 796         u32     reserved[8];
 797         __le32  resp_addr_lo;
 798         __le32  resp_addr_hi;
 799         __le32  resp_len;
 800         u32     reserved1[17];
 801 } __attribute__((packed, aligned(4)));
 802
 803 struct set_nvm_data_req {
 804         __le32  tag;
 805         __le32  len_ir_vpdd;
 806         __le32  vpd_offset;
 807         u32     reserved[8];
 808         __le32  resp_addr_lo;
 809         __le32  resp_addr_hi;
 810         __le32  resp_len;
 811         u32     reserved1[17];
 812 } __attribute__((packed, aligned(4)));
 813
 814 /**
 815  * brief the data structure for SET CONTROLLER CONFIG COMMAND
 816  * use to modify controller configuration
 817  */
 818 struct set_ctrl_cfg_req {
 819         __le32  tag;
 820         __le32  cfg_pg[14];
 821         u32     reserved[16];
 822 } __attribute__((packed, aligned(4)));
 823
 824 /**
 825  * brief the data structure for GET CONTROLLER CONFIG COMMAND
 826  * use to get controller configuration page
 827  */
 828 struct get_ctrl_cfg_req {
 829         __le32  tag;
 830         __le32  pgcd;
 831         __le32  int_vec;
 832         u32     reserved[28];
 833 } __attribute__((packed, aligned(4)));
 834
 835 /**
 836  * brief the data structure for KEK_MANAGEMENT COMMAND
 837  * use for KEK management
 838  */
 839 struct kek_mgmt_req {
 840         __le32  tag;
 841         __le32  new_curidx_ksop;
 842         u32     reserved;
 843         __le32  kblob[12];
 844         u32     reserved1[16];
 845 } __attribute__((packed, aligned(4)));
 846
 847 /**
 848  * brief the data structure for DEK_MANAGEMENT COMMAND
 849  * use for DEK management
 850  */
 851 struct dek_mgmt_req {
 852         __le32  tag;
 853         __le32  kidx_dsop;
 854         __le32  dekidx;
 855         __le32  addr_l;
 856         __le32  addr_h;
 857         __le32  nent;
 858         __le32  dbf_tblsize;
 859         u32     reserved[24];
 860 } __attribute__((packed, aligned(4)));
 861
 862 /**
 863  * brief the data structure for SET PHY PROFILE COMMAND
 864  * use to retrive phy specific information
 865  */
 866 struct set_phy_profile_req {
 867         __le32  tag;
 868         __le32  ppc_phyid;
 869         u32     reserved[29];
 870 } __attribute__((packed, aligned(4)));
 871
 872 /**
 873  * brief the data structure for GET PHY PROFILE COMMAND
 874  * use to retrive phy specific information
 875  */
 876 struct get_phy_profile_req {
 877         __le32  tag;
 878         __le32  ppc_phyid;
 879         __le32  profile[29];
 880 } __attribute__((packed, aligned(4)));
 881
 882 /**
 883  * brief the data structure for EXT FLASH PARTITION
 884  * use to manage ext flash partition
 885  */
 886 struct ext_flash_partition_req {
 887         __le32  tag;
 888         __le32  cmd;
 889         __le32  offset;
 890         __le32  len;
 891         u32     reserved[7];
 892         __le32  addr_low;
 893         __le32  addr_high;
 894         __le32  len1;
 895         __le32  ext;
 896         u32     reserved1[16];
 897 } __attribute__((packed, aligned(4)));
 898
 899 #define TWI_DEVICE      0x0
 900 #define C_SEEPROM       0x1
 901 #define VPD_FLASH       0x4
 902 #define AAP1_RDUMP      0x5
 903 #define IOP_RDUMP       0x6
 904 #define EXPAN_ROM       0x7
 905
 906 #define IPMode          0x80000000
 907 #define NVMD_TYPE       0x0000000F
 908 #define NVMD_STAT       0x0000FFFF
 909 #define NVMD_LEN        0xFF000000
 910 /**
 911  * brief the data structure of Get NVMD Data Response
 912  * use to describe MPI Get NVMD Data Response (64 bytes)
 913  */
 914 struct get_nvm_data_resp {
 915         __le32          tag;
 916         __le32          ir_tda_bn_dps_das_nvm;
 917         __le32          dlen_status;
 918         __le32          nvm_data[12];
 919 } __attribute__((packed, aligned(4)));
 920
 921 /**
 922  * brief the data structure of SAS Diagnostic Start/End Response
 923  * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
 924  *
 925  */
 926 struct sas_diag_start_end_resp {
 927         __le32          tag;
 928         __le32          status;
 929         u32             reserved[13];
 930 } __attribute__((packed, aligned(4)));
 931
 932 /**
 933  * brief the data structure of SAS Diagnostic Execute Response
 934  * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
 935  *
 936  */
 937 struct sas_diag_execute_resp {
 938         __le32          tag;
 939         __le32          cmdtype_cmddesc_phyid;
 940         __le32          Status;
 941         __le32          ReportData;
 942         u32             reserved[11];
 943 } __attribute__((packed, aligned(4)));
 944
 945 /**
 946  * brief the data structure of Set Device State Response
 947  * use to describe MPI Set Device State Response (64 bytes)
 948  *
 949  */
 950 struct set_dev_state_resp {
 951         __le32          tag;
 952         __le32          status;
 953         __le32          device_id;
 954         __le32          pds_nds;
 955         u32             reserved[11];
 956 } __attribute__((packed, aligned(4)));
 957
 958 /* new outbound structure for spcv - begins */
 959 /**
 960  * brief the data structure for SET CONTROLLER CONFIG COMMAND
 961  * use to modify controller configuration
 962  */
 963 struct set_ctrl_cfg_resp {
 964         __le32 tag;
 965         __le32 status;
 966         __le32 err_qlfr_pgcd;
 967         u32 reserved[12];
 968 } __attribute__((packed, aligned(4)));
 969
 970 struct get_ctrl_cfg_resp {
 971         __le32 tag;
 972         __le32 status;
 973         __le32 err_qlfr;
 974         __le32 confg_page[12];
 975 } __attribute__((packed, aligned(4)));
 976
 977 struct kek_mgmt_resp {
 978         __le32 tag;
 979         __le32 status;
 980         __le32 kidx_new_curr_ksop;
 981         __le32 err_qlfr;
 982         u32 reserved[11];
 983 } __attribute__((packed, aligned(4)));
 984
 985 struct dek_mgmt_resp {
 986         __le32 tag;
 987         __le32 status;
 988         __le32 kekidx_tbls_dsop;
 989         __le32 dekidx;
 990         __le32 err_qlfr;
 991         u32 reserved[10];
 992 } __attribute__((packed, aligned(4)));
 993
 994 struct get_phy_profile_resp {
 995         __le32 tag;
 996         __le32 status;
 997         __le32 ppc_phyid;
 998         __le32 ppc_specific_rsp[12];
 999 } __attribute__((packed, aligned(4)));
1000
1001 struct flash_op_ext_resp {
1002         __le32 tag;
1003         __le32 cmd;
1004         __le32 status;
1005         __le32 epart_size;
1006         __le32 epart_sect_size;
1007         u32 reserved[10];
1008 } __attribute__((packed, aligned(4)));
1009
1010 struct set_phy_profile_resp {
1011         __le32 tag;
1012         __le32 status;
1013         __le32 ppc_phyid;
1014         __le32 ppc_specific_rsp[12];
1015 } __attribute__((packed, aligned(4)));
1016
1017 struct ssp_coalesced_comp_resp {
1018         __le32 coal_cnt;
1019         __le32 tag0;
1020         __le32 ssp_tag0;
1021         __le32 tag1;
1022         __le32 ssp_tag1;
1023         __le32 add_tag_ssp_tag[10];
1024 } __attribute__((packed, aligned(4)));
1025
1026 /* new outbound structure for spcv - ends */
1027
1028 /* brief data structure for SAS protocol timer configuration page.
1029  *
1030  */
1031 struct SASProtocolTimerConfig {
1032         __le32 pageCode;                        /* 0 */
1033         __le32 MST_MSI;                         /* 1 */
1034         __le32 STP_SSP_MCT_TMO;                 /* 2 */
1035         __le32 STP_FRM_TMO;                     /* 3 */
1036         __le32 STP_IDLE_TMO;                    /* 4 */
1037         __le32 OPNRJT_RTRY_INTVL;               /* 5 */
1038         __le32 Data_Cmd_OPNRJT_RTRY_TMO;        /* 6 */
1039         __le32 Data_Cmd_OPNRJT_RTRY_THR;        /* 7 */
1040         __le32 MAX_AIP;                         /* 8 */
1041 } __attribute__((packed, aligned(4)));
1042
1043 typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
1044
1045 #define NDS_BITS 0x0F
1046 #define PDS_BITS 0xF0
1047
1048 /*
1049  * HW Events type
1050  */
1051
1052 #define HW_EVENT_RESET_START                    0x01
1053 #define HW_EVENT_CHIP_RESET_COMPLETE            0x02
1054 #define HW_EVENT_PHY_STOP_STATUS                0x03
1055 #define HW_EVENT_SAS_PHY_UP                     0x04
1056 #define HW_EVENT_SATA_PHY_UP                    0x05
1057 #define HW_EVENT_SATA_SPINUP_HOLD               0x06
1058 #define HW_EVENT_PHY_DOWN                       0x07
1059 #define HW_EVENT_PORT_INVALID                   0x08
1060 #define HW_EVENT_BROADCAST_CHANGE               0x09
1061 #define HW_EVENT_PHY_ERROR                      0x0A
1062 #define HW_EVENT_BROADCAST_SES                  0x0B
1063 #define HW_EVENT_INBOUND_CRC_ERROR              0x0C
1064 #define HW_EVENT_HARD_RESET_RECEIVED            0x0D
1065 #define HW_EVENT_MALFUNCTION                    0x0E
1066 #define HW_EVENT_ID_FRAME_TIMEOUT               0x0F
1067 #define HW_EVENT_BROADCAST_EXP                  0x10
1068 #define HW_EVENT_PHY_START_STATUS               0x11
1069 #define HW_EVENT_LINK_ERR_INVALID_DWORD         0x12
1070 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR       0x13
1071 #define HW_EVENT_LINK_ERR_CODE_VIOLATION        0x14
1072 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH   0x15
1073 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED      0x16
1074 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO        0x17
1075 #define HW_EVENT_PORT_RECOVER                   0x18
1076 #define HW_EVENT_PORT_RESET_TIMER_TMO           0x19
1077 #define HW_EVENT_PORT_RESET_COMPLETE            0x20
1078 #define EVENT_BROADCAST_ASYNCH_EVENT            0x21
1079
1080 /* port state */
1081 #define PORT_NOT_ESTABLISHED                    0x00
1082 #define PORT_VALID                              0x01
1083 #define PORT_LOSTCOMM                           0x02
1084 #define PORT_IN_RESET                           0x04
1085 #define PORT_3RD_PARTY_RESET                    0x07
1086 #define PORT_INVALID                            0x08
1087
1088 /*
1089  * SSP/SMP/SATA IO Completion Status values
1090  */
1091
1092 #define IO_SUCCESS                              0x00
1093 #define IO_ABORTED                              0x01
1094 #define IO_OVERFLOW                             0x02
1095 #define IO_UNDERFLOW                            0x03
1096 #define IO_FAILED                               0x04
1097 #define IO_ABORT_RESET                          0x05
1098 #define IO_NOT_VALID                            0x06
1099 #define IO_NO_DEVICE                            0x07
1100 #define IO_ILLEGAL_PARAMETER                    0x08
1101 #define IO_LINK_FAILURE                         0x09
1102 #define IO_PROG_ERROR                           0x0A
1103
1104 #define IO_EDC_IN_ERROR                         0x0B
1105 #define IO_EDC_OUT_ERROR                        0x0C
1106 #define IO_ERROR_HW_TIMEOUT                     0x0D
1107 #define IO_XFER_ERROR_BREAK                     0x0E
1108 #define IO_XFER_ERROR_PHY_NOT_READY             0x0F
1109 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED        0x10
1110 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION                0x11
1111 #define IO_OPEN_CNX_ERROR_BREAK                         0x12
1112 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS                 0x13
1113 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION               0x14
1114 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
1115 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY            0x16
1116 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION             0x17
1117 /* This error code 0x18 is not used on SPCv */
1118 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR                 0x18
1119 #define IO_XFER_ERROR_NAK_RECEIVED                      0x19
1120 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT                   0x1A
1121 #define IO_XFER_ERROR_PEER_ABORTED                      0x1B
1122 #define IO_XFER_ERROR_RX_FRAME                          0x1C
1123 #define IO_XFER_ERROR_DMA                               0x1D
1124 #define IO_XFER_ERROR_CREDIT_TIMEOUT                    0x1E
1125 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT                 0x1F
1126 #define IO_XFER_ERROR_SATA                              0x20
1127
1128 /* This error code 0x22 is not used on SPCv */
1129 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST               0x22
1130 #define IO_XFER_ERROR_REJECTED_NCQ_MODE                 0x21
1131 #define IO_XFER_ERROR_ABORTED_NCQ_MODE                  0x23
1132 #define IO_XFER_OPEN_RETRY_TIMEOUT                      0x24
1133 /* This error code 0x25 is not used on SPCv */
1134 #define IO_XFER_SMP_RESP_CONNECTION_ERROR               0x25
1135 #define IO_XFER_ERROR_UNEXPECTED_PHASE                  0x26
1136 #define IO_XFER_ERROR_XFER_RDY_OVERRUN                  0x27
1137 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED             0x28
1138 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT         0x30
1139
1140 /* The following error code 0x31 and 0x32 are not using (obsolete) */
1141 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK    0x31
1142 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
1143
1144 #define IO_XFER_ERROR_OFFSET_MISMATCH                   0x34
1145 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN                0x35
1146 #define IO_XFER_CMD_FRAME_ISSUED                        0x36
1147 #define IO_ERROR_INTERNAL_SMP_RESOURCE                  0x37
1148 #define IO_PORT_IN_RESET                                0x38
1149 #define IO_DS_NON_OPERATIONAL                           0x39
1150 #define IO_DS_IN_RECOVERY                               0x3A
1151 #define IO_TM_TAG_NOT_FOUND                             0x3B
1152 #define IO_XFER_PIO_SETUP_ERROR                         0x3C
1153 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR                    0x3D
1154 #define IO_DS_IN_ERROR                                  0x3E
1155 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY              0x3F
1156 #define IO_ABORT_IN_PROGRESS                            0x40
1157 #define IO_ABORT_DELAYED                                0x41
1158 #define IO_INVALID_LENGTH                               0x42
1159
1160 /********** additional response event values *****************/
1161
1162 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT          0x43
1163 #define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED    0x44
1164 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO        0x45
1165 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST         0x46
1166 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE    0x47
1167 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
1168 #define IO_DS_INVALID                                   0x49
1169 /* WARNING: the value is not contiguous from here */
1170 #define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR     0x52
1171 #define IO_XFER_DMA_ACTIVATE_TIMEOUT            0x53
1172 #define IO_XFER_ERROR_INTERNAL_CRC_ERROR        0x54
1173 #define MPI_IO_RQE_BUSY_FULL                    0x55
1174 #define IO_XFER_ERR_EOB_DATA_OVERRUN            0x56
1175 #define IO_XFR_ERROR_INVALID_SSP_RSP_FRAME      0x57
1176 #define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED        0x58
1177
1178 #define MPI_ERR_IO_RESOURCE_UNAVAILABLE         0x1004
1179 #define MPI_ERR_ATAPI_DEVICE_BUSY               0x1024
1180
1181 #define IO_XFR_ERROR_DEK_KEY_CACHE_MISS         0x2040
1182 /*
1183  * An encryption IO request failed due to DEK Key Tag mismatch.
1184  * The key tag supplied in the encryption IOMB does not match with
1185  * the Key Tag in the referenced DEK Entry.
1186  */
1187 #define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH       0x2041
1188 #define IO_XFR_ERROR_CIPHER_MODE_INVALID        0x2042
1189 /*
1190  * An encryption I/O request failed because the initial value (IV)
1191  * in the unwrapped DEK blob didn't match the IV used to unwrap it.
1192  */
1193 #define IO_XFR_ERROR_DEK_IV_MISMATCH            0x2043
1194 /* An encryption I/O request failed due to an internal RAM ECC or
1195  * interface error while unwrapping the DEK. */
1196 #define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR    0x2044
1197 /* An encryption I/O request failed due to an internal RAM ECC or
1198  * interface error while unwrapping the DEK. */
1199 #define IO_XFR_ERROR_INTERNAL_RAM               0x2045
1200 /*
1201  * An encryption I/O request failed
1202  * because the DEK index specified in the I/O was outside the bounds of
1203  * the total number of entries in the host DEK table.
1204  */
1205 #define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
1206
1207 /* define DIF IO response error status code */
1208 #define IO_XFR_ERROR_DIF_MISMATCH                       0x3000
1209 #define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH       0x3001
1210 #define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH         0x3002
1211 #define IO_XFR_ERROR_DIF_CRC_MISMATCH                   0x3003
1212
1213 /* define operator management response status and error qualifier code */
1214 #define OPR_MGMT_OP_NOT_SUPPORTED                       0x2060
1215 #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL          0x2061
1216 #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND           0x2062
1217 #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH         0x2063
1218 #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED       0x2064
1219 #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL            0x2022
1220 #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE    0x2023
1221 /***************** additional response event values ***************/
1222
1223 /* WARNING: This error code must always be the last number.
1224  * If you add error code, modify this code also
1225  * It is used as an index
1226  */
1227 #define IO_ERROR_UNKNOWN_GENERIC                        0x2023
1228
1229 /* MSGU CONFIGURATION TABLE*/
1230
1231 #define SPCv_MSGU_CFG_TABLE_UPDATE              0x001
1232 #define SPCv_MSGU_CFG_TABLE_RESET               0x002
1233 #define SPCv_MSGU_CFG_TABLE_FREEZE              0x004
1234 #define SPCv_MSGU_CFG_TABLE_UNFREEZE            0x008
1235 #define MSGU_IBDB_SET                           0x00
1236 #define MSGU_HOST_INT_STATUS                    0x08
1237 #define MSGU_HOST_INT_MASK                      0x0C
1238 #define MSGU_IOPIB_INT_STATUS                   0x18
1239 #define MSGU_IOPIB_INT_MASK                     0x1C
1240 #define MSGU_IBDB_CLEAR                         0x20
1241
1242 #define MSGU_MSGU_CONTROL                       0x24
1243 #define MSGU_ODR                                0x20
1244 #define MSGU_ODCR                               0x28
1245
1246 #define MSGU_ODMR                               0x30
1247 #define MSGU_ODMR_U                             0x34
1248 #define MSGU_ODMR_CLR                           0x38
1249 #define MSGU_ODMR_CLR_U                         0x3C
1250 #define MSGU_OD_RSVD                            0x40
1251
1252 #define MSGU_SCRATCH_PAD_0                      0x44
1253 #define MSGU_SCRATCH_PAD_1                      0x48
1254 #define MSGU_SCRATCH_PAD_2                      0x4C
1255 #define MSGU_SCRATCH_PAD_3                      0x50
1256 #define MSGU_HOST_SCRATCH_PAD_0                 0x54
1257 #define MSGU_HOST_SCRATCH_PAD_1                 0x58
1258 #define MSGU_HOST_SCRATCH_PAD_2                 0x5C
1259 #define MSGU_HOST_SCRATCH_PAD_3                 0x60
1260 #define MSGU_HOST_SCRATCH_PAD_4                 0x64
1261 #define MSGU_HOST_SCRATCH_PAD_5                 0x68
1262 #define MSGU_HOST_SCRATCH_PAD_6                 0x6C
1263 #define MSGU_HOST_SCRATCH_PAD_7                 0x70
1264
1265 /* bit definition for ODMR register */
1266 #define ODMR_MASK_ALL                   0xFFFFFFFF/* mask all
1267                                         interrupt vector */
1268 #define ODMR_CLEAR_ALL                  0       /* clear all
1269                                         interrupt vector */
1270 /* bit definition for ODCR register */
1271 #define ODCR_CLEAR_ALL                  0xFFFFFFFF /* mask all
1272                                         interrupt vector*/
1273 /* MSIX Interupts */
1274 #define MSIX_TABLE_OFFSET               0x2000
1275 #define MSIX_TABLE_ELEMENT_SIZE         0x10
1276 #define MSIX_INTERRUPT_CONTROL_OFFSET   0xC
1277 #define MSIX_TABLE_BASE                 (MSIX_TABLE_OFFSET + \
1278                                         MSIX_INTERRUPT_CONTROL_OFFSET)
1279 #define MSIX_INTERRUPT_DISABLE          0x1
1280 #define MSIX_INTERRUPT_ENABLE           0x0
1281
1282 /* state definition for Scratch Pad1 register */
1283 #define SCRATCH_PAD_RAAE_READY          0x3
1284 #define SCRATCH_PAD_ILA_READY           0xC
1285 #define SCRATCH_PAD_BOOT_LOAD_SUCCESS   0x0
1286 #define SCRATCH_PAD_IOP0_READY          0xC00
1287 #define SCRATCH_PAD_IOP1_READY          0x3000
1288
1289 /* boot loader state */
1290 #define SCRATCH_PAD1_BOOTSTATE_MASK             0x70    /* Bit 4-6 */
1291 #define SCRATCH_PAD1_BOOTSTATE_SUCESS           0x0     /* Load successful */
1292 #define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM      0x10    /* HDA SEEPROM */
1293 #define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP    0x20    /* HDA BootStrap Pins */
1294 #define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET    0x30    /* HDA Soft Reset */
1295 #define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR       0x40    /* HDA critical error */
1296 #define SCRATCH_PAD1_BOOTSTATE_R1               0x50    /* Reserved */
1297 #define SCRATCH_PAD1_BOOTSTATE_R2               0x60    /* Reserved */
1298 #define SCRATCH_PAD1_BOOTSTATE_FATAL            0x70    /* Fatal Error */
1299
1300  /* state definition for Scratch Pad2 register */
1301 #define SCRATCH_PAD2_POR                0x00    /* power on state */
1302 #define SCRATCH_PAD2_SFR                0x01    /* soft reset state */
1303 #define SCRATCH_PAD2_ERR                0x02    /* error state */
1304 #define SCRATCH_PAD2_RDY                0x03    /* ready state */
1305 #define SCRATCH_PAD2_FWRDY_RST          0x04    /* FW rdy for soft reset flag */
1306 #define SCRATCH_PAD2_IOPRDY_RST         0x08    /* IOP ready for soft reset */
1307 #define SCRATCH_PAD2_STATE_MASK         0xFFFFFFF4 /* ScratchPad 2
1308  Mask, bit1-0 State */
1309 #define SCRATCH_PAD2_RESERVED           0x000003FC/* Scratch Pad1
1310  Reserved bit 2 to 9 */
1311
1312 #define SCRATCH_PAD_ERROR_MASK          0xFFFFFC00 /* Error mask bits */
1313 #define SCRATCH_PAD_STATE_MASK          0x00000003 /* State Mask bits */
1314
1315 /* main configuration offset - byte offset */
1316 #define MAIN_SIGNATURE_OFFSET           0x00 /* DWORD 0x00 */
1317 #define MAIN_INTERFACE_REVISION         0x04 /* DWORD 0x01 */
1318 #define MAIN_FW_REVISION                0x08 /* DWORD 0x02 */
1319 #define MAIN_MAX_OUTSTANDING_IO_OFFSET  0x0C /* DWORD 0x03 */
1320 #define MAIN_MAX_SGL_OFFSET             0x10 /* DWORD 0x04 */
1321 #define MAIN_CNTRL_CAP_OFFSET           0x14 /* DWORD 0x05 */
1322 #define MAIN_GST_OFFSET                 0x18 /* DWORD 0x06 */
1323 #define MAIN_IBQ_OFFSET                 0x1C /* DWORD 0x07 */
1324 #define MAIN_OBQ_OFFSET                 0x20 /* DWORD 0x08 */
1325 #define MAIN_IQNPPD_HPPD_OFFSET         0x24 /* DWORD 0x09 */
1326
1327 /* 0x28 - 0x4C - RSVD */
1328 #define MAIN_EVENT_CRC_CHECK            0x48 /* DWORD 0x12 */
1329 #define MAIN_EVENT_LOG_ADDR_HI          0x50 /* DWORD 0x14 */
1330 #define MAIN_EVENT_LOG_ADDR_LO          0x54 /* DWORD 0x15 */
1331 #define MAIN_EVENT_LOG_BUFF_SIZE        0x58 /* DWORD 0x16 */
1332 #define MAIN_EVENT_LOG_OPTION           0x5C /* DWORD 0x17 */
1333 #define MAIN_PCS_EVENT_LOG_ADDR_HI      0x60 /* DWORD 0x18 */
1334 #define MAIN_PCS_EVENT_LOG_ADDR_LO      0x64 /* DWORD 0x19 */
1335 #define MAIN_PCS_EVENT_LOG_BUFF_SIZE    0x68 /* DWORD 0x1A */
1336 #define MAIN_PCS_EVENT_LOG_OPTION       0x6C /* DWORD 0x1B */
1337 #define MAIN_FATAL_ERROR_INTERRUPT      0x70 /* DWORD 0x1C */
1338 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET  0x74 /* DWORD 0x1D */
1339 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH  0x78 /* DWORD 0x1E */
1340 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET  0x7C /* DWORD 0x1F */
1341 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH  0x80 /* DWORD 0x20 */
1342 #define MAIN_GPIO_LED_FLAGS_OFFSET      0x84 /* DWORD 0x21 */
1343 #define MAIN_ANALOG_SETUP_OFFSET        0x88 /* DWORD 0x22 */
1344
1345 #define MAIN_INT_VECTOR_TABLE_OFFSET    0x8C /* DWORD 0x23 */
1346 #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET  0x90 /* DWORD 0x24 */
1347 #define MAIN_PORT_RECOVERY_TIMER        0x94 /* DWORD 0x25 */
1348 #define MAIN_INT_REASSERTION_DELAY      0x98 /* DWORD 0x26 */
1349
1350 /* Gereral Status Table offset - byte offset */
1351 #define GST_GSTLEN_MPIS_OFFSET          0x00
1352 #define GST_IQ_FREEZE_STATE0_OFFSET     0x04
1353 #define GST_IQ_FREEZE_STATE1_OFFSET     0x08
1354 #define GST_MSGUTCNT_OFFSET             0x0C
1355 #define GST_IOPTCNT_OFFSET              0x10
1356 /* 0x14 - 0x34 - RSVD */
1357 #define GST_GPIO_INPUT_VAL              0x38
1358 /* 0x3c - 0x40 - RSVD */
1359 #define GST_RERRINFO_OFFSET0            0x44
1360 #define GST_RERRINFO_OFFSET1            0x48
1361 #define GST_RERRINFO_OFFSET2            0x4c
1362 #define GST_RERRINFO_OFFSET3            0x50
1363 #define GST_RERRINFO_OFFSET4            0x54
1364 #define GST_RERRINFO_OFFSET5            0x58
1365 #define GST_RERRINFO_OFFSET6            0x5c
1366 #define GST_RERRINFO_OFFSET7            0x60
1367
1368 /* General Status Table - MPI state */
1369 #define GST_MPI_STATE_UNINIT            0x00
1370 #define GST_MPI_STATE_INIT              0x01
1371 #define GST_MPI_STATE_TERMINATION       0x02
1372 #define GST_MPI_STATE_ERROR             0x03
1373 #define GST_MPI_STATE_MASK              0x07
1374
1375 /* Per SAS PHY Attributes */
1376
1377 #define PSPA_PHYSTATE0_OFFSET           0x00 /* Dword V */
1378 #define PSPA_OB_HW_EVENT_PID0_OFFSET    0x04 /* DWORD V+1 */
1379 #define PSPA_PHYSTATE1_OFFSET           0x08 /* Dword V+2 */
1380 #define PSPA_OB_HW_EVENT_PID1_OFFSET    0x0C /* DWORD V+3 */
1381 #define PSPA_PHYSTATE2_OFFSET           0x10 /* Dword V+4 */
1382 #define PSPA_OB_HW_EVENT_PID2_OFFSET    0x14 /* DWORD V+5 */
1383 #define PSPA_PHYSTATE3_OFFSET           0x18 /* Dword V+6 */
1384 #define PSPA_OB_HW_EVENT_PID3_OFFSET    0x1C /* DWORD V+7 */
1385 #define PSPA_PHYSTATE4_OFFSET           0x20 /* Dword V+8 */
1386 #define PSPA_OB_HW_EVENT_PID4_OFFSET    0x24 /* DWORD V+9 */
1387 #define PSPA_PHYSTATE5_OFFSET           0x28 /* Dword V+10 */
1388 #define PSPA_OB_HW_EVENT_PID5_OFFSET    0x2C /* DWORD V+11 */
1389 #define PSPA_PHYSTATE6_OFFSET           0x30 /* Dword V+12 */
1390 #define PSPA_OB_HW_EVENT_PID6_OFFSET    0x34 /* DWORD V+13 */
1391 #define PSPA_PHYSTATE7_OFFSET           0x38 /* Dword V+14 */
1392 #define PSPA_OB_HW_EVENT_PID7_OFFSET    0x3C /* DWORD V+15 */
1393 #define PSPA_PHYSTATE8_OFFSET           0x40 /* DWORD V+16 */
1394 #define PSPA_OB_HW_EVENT_PID8_OFFSET    0x44 /* DWORD V+17 */
1395 #define PSPA_PHYSTATE9_OFFSET           0x48 /* DWORD V+18 */
1396 #define PSPA_OB_HW_EVENT_PID9_OFFSET    0x4C /* DWORD V+19 */
1397 #define PSPA_PHYSTATE10_OFFSET          0x50 /* DWORD V+20 */
1398 #define PSPA_OB_HW_EVENT_PID10_OFFSET   0x54 /* DWORD V+21 */
1399 #define PSPA_PHYSTATE11_OFFSET          0x58 /* DWORD V+22 */
1400 #define PSPA_OB_HW_EVENT_PID11_OFFSET   0x5C /* DWORD V+23 */
1401 #define PSPA_PHYSTATE12_OFFSET          0x60 /* DWORD V+24 */
1402 #define PSPA_OB_HW_EVENT_PID12_OFFSET   0x64 /* DWORD V+25 */
1403 #define PSPA_PHYSTATE13_OFFSET          0x68 /* DWORD V+26 */
1404 #define PSPA_OB_HW_EVENT_PID13_OFFSET   0x6c /* DWORD V+27 */
1405 #define PSPA_PHYSTATE14_OFFSET          0x70 /* DWORD V+28 */
1406 #define PSPA_OB_HW_EVENT_PID14_OFFSET   0x74 /* DWORD V+29 */
1407 #define PSPA_PHYSTATE15_OFFSET          0x78 /* DWORD V+30 */
1408 #define PSPA_OB_HW_EVENT_PID15_OFFSET   0x7c /* DWORD V+31 */
1409 /* end PSPA */
1410
1411 /* inbound queue configuration offset - byte offset */
1412 #define IB_PROPERITY_OFFSET             0x00
1413 #define IB_BASE_ADDR_HI_OFFSET          0x04
1414 #define IB_BASE_ADDR_LO_OFFSET          0x08
1415 #define IB_CI_BASE_ADDR_HI_OFFSET       0x0C
1416 #define IB_CI_BASE_ADDR_LO_OFFSET       0x10
1417 #define IB_PIPCI_BAR                    0x14
1418 #define IB_PIPCI_BAR_OFFSET             0x18
1419 #define IB_RESERVED_OFFSET              0x1C
1420
1421 /* outbound queue configuration offset - byte offset */
1422 #define OB_PROPERITY_OFFSET             0x00
1423 #define OB_BASE_ADDR_HI_OFFSET          0x04
1424 #define OB_BASE_ADDR_LO_OFFSET          0x08
1425 #define OB_PI_BASE_ADDR_HI_OFFSET       0x0C
1426 #define OB_PI_BASE_ADDR_LO_OFFSET       0x10
1427 #define OB_CIPCI_BAR                    0x14
1428 #define OB_CIPCI_BAR_OFFSET             0x18
1429 #define OB_INTERRUPT_COALES_OFFSET      0x1C
1430 #define OB_DYNAMIC_COALES_OFFSET        0x20
1431 #define OB_PROPERTY_INT_ENABLE          0x40000000
1432
1433 #define MBIC_NMI_ENABLE_VPE0_IOP        0x000418
1434 #define MBIC_NMI_ENABLE_VPE0_AAP1       0x000418
1435 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
1436 #define PCIE_EVENT_INTERRUPT_ENABLE     0x003040
1437 #define PCIE_EVENT_INTERRUPT            0x003044
1438 #define PCIE_ERROR_INTERRUPT_ENABLE     0x003048
1439 #define PCIE_ERROR_INTERRUPT            0x00304C
1440
1441 /* SPCV soft reset */
1442 #define SPC_REG_SOFT_RESET 0x00001000
1443 #define SPCv_NORMAL_RESET_VALUE         0x1
1444
1445 #define SPCv_SOFT_RESET_READ_MASK               0xC0
1446 #define SPCv_SOFT_RESET_NO_RESET                0x0
1447 #define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED    0x40
1448 #define SPCv_SOFT_RESET_HDA_MODE_OCCURED        0x80
1449 #define SPCv_SOFT_RESET_CHIP_RESET_OCCURED      0xC0
1450
1451 /* signature definition for host scratch pad0 register */
1452 #define SPC_SOFT_RESET_SIGNATURE        0x252acbcd
1453 /* Signature for Soft Reset */
1454
1455 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
1456 #define SPC_REG_RESET                   0x000000/* reset register */
1457
1458 /* bit definition for SPC_RESET register */
1459 #define SPC_REG_RESET_OSSP              0x00000001
1460 #define SPC_REG_RESET_RAAE              0x00000002
1461 #define SPC_REG_RESET_PCS_SPBC          0x00000004
1462 #define SPC_REG_RESET_PCS_IOP_SS        0x00000008
1463 #define SPC_REG_RESET_PCS_AAP1_SS       0x00000010
1464 #define SPC_REG_RESET_PCS_AAP2_SS       0x00000020
1465 #define SPC_REG_RESET_PCS_LM            0x00000040
1466 #define SPC_REG_RESET_PCS               0x00000080
1467 #define SPC_REG_RESET_GSM               0x00000100
1468 #define SPC_REG_RESET_DDR2              0x00010000
1469 #define SPC_REG_RESET_BDMA_CORE         0x00020000
1470 #define SPC_REG_RESET_BDMA_SXCBI        0x00040000
1471 #define SPC_REG_RESET_PCIE_AL_SXCBI     0x00080000
1472 #define SPC_REG_RESET_PCIE_PWR          0x00100000
1473 #define SPC_REG_RESET_PCIE_SFT          0x00200000
1474 #define SPC_REG_RESET_PCS_SXCBI         0x00400000
1475 #define SPC_REG_RESET_LMS_SXCBI         0x00800000
1476 #define SPC_REG_RESET_PMIC_SXCBI        0x01000000
1477 #define SPC_REG_RESET_PMIC_CORE         0x02000000
1478 #define SPC_REG_RESET_PCIE_PC_SXCBI     0x04000000
1479 #define SPC_REG_RESET_DEVICE            0x80000000
1480
1481 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
1482 #define SPCV_IBW_AXI_TRANSLATION_LOW    0x001010
1483
1484 #define MBIC_AAP1_ADDR_BASE             0x060000
1485 #define MBIC_IOP_ADDR_BASE              0x070000
1486 #define GSM_ADDR_BASE                   0x0700000
1487 /* Dynamic map through Bar4 - 0x00700000 */
1488 #define GSM_CONFIG_RESET                0x00000000
1489 #define RAM_ECC_DB_ERR                  0x00000018
1490 #define GSM_READ_ADDR_PARITY_INDIC      0x00000058
1491 #define GSM_WRITE_ADDR_PARITY_INDIC     0x00000060
1492 #define GSM_WRITE_DATA_PARITY_INDIC     0x00000068
1493 #define GSM_READ_ADDR_PARITY_CHECK      0x00000038
1494 #define GSM_WRITE_ADDR_PARITY_CHECK     0x00000040
1495 #define GSM_WRITE_DATA_PARITY_CHECK     0x00000048
1496
1497 #define RB6_ACCESS_REG                  0x6A0000
1498 #define HDAC_EXEC_CMD                   0x0002
1499 #define HDA_C_PA                        0xcb
1500 #define HDA_SEQ_ID_BITS                 0x00ff0000
1501 #define HDA_GSM_OFFSET_BITS             0x00FFFFFF
1502 #define HDA_GSM_CMD_OFFSET_BITS         0x42C0
1503 #define HDA_GSM_RSP_OFFSET_BITS         0x42E0
1504
1505 #define MBIC_AAP1_ADDR_BASE             0x060000
1506 #define MBIC_IOP_ADDR_BASE              0x070000
1507 #define GSM_ADDR_BASE                   0x0700000
1508 #define SPC_TOP_LEVEL_ADDR_BASE         0x000000
1509 #define GSM_CONFIG_RESET_VALUE          0x00003b00
1510 #define GPIO_ADDR_BASE                  0x00090000
1511 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET   0x0000010c
1512
1513 /* RB6 offset */
1514 #define SPC_RB6_OFFSET                  0x80C0
1515 /* Magic number of soft reset for RB6 */
1516 #define RB6_MAGIC_NUMBER_RST            0x1234
1517
1518 /* Device Register status */
1519 #define DEVREG_SUCCESS                                  0x00
1520 #define DEVREG_FAILURE_OUT_OF_RESOURCE                  0x01
1521 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED        0x02
1522 #define DEVREG_FAILURE_INVALID_PHY_ID                   0x03
1523 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED        0x04
1524 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE             0x05
1525 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE             0x06
1526 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID            0x07
1527
1528
1529 #define MEMBASE_II_SHIFT_REGISTER       0x1010
1530 #endif