drivers/thermal/mtk_thermal.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Author: Hanyi Wu <hanyi.wu@mediatek.com>
   4  *         Sascha Hauer <s.hauer@pengutronix.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/nvmem-consumer.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/io.h>
  27 #include <linux/thermal.h>
  28 #include <linux/reset.h>
  29 #include <linux/types.h>
  30
  31 /* AUXADC Registers */
  32 #define AUXADC_CON0_V           0x000
  33 #define AUXADC_CON1_V           0x004
  34 #define AUXADC_CON1_SET_V       0x008
  35 #define AUXADC_CON1_CLR_V       0x00c
  36 #define AUXADC_CON2_V           0x010
  37 #define AUXADC_DATA(channel)    (0x14 + (channel) * 4)
  38 #define AUXADC_MISC_V           0x094
  39
  40 #define AUXADC_CON1_CHANNEL(x)  BIT(x)
  41
  42 #define APMIXED_SYS_TS_CON1     0x604
  43
  44 /* Thermal Controller Registers */
  45 #define TEMP_MONCTL0            0x000
  46 #define TEMP_MONCTL1            0x004
  47 #define TEMP_MONCTL2            0x008
  48 #define TEMP_MONIDET0           0x014
  49 #define TEMP_MONIDET1           0x018
  50 #define TEMP_MSRCTL0            0x038
  51 #define TEMP_AHBPOLL            0x040
  52 #define TEMP_AHBTO              0x044
  53 #define TEMP_ADCPNP0            0x048
  54 #define TEMP_ADCPNP1            0x04c
  55 #define TEMP_ADCPNP2            0x050
  56 #define TEMP_ADCPNP3            0x0b4
  57
  58 #define TEMP_ADCMUX             0x054
  59 #define TEMP_ADCEN              0x060
  60 #define TEMP_PNPMUXADDR         0x064
  61 #define TEMP_ADCMUXADDR         0x068
  62 #define TEMP_ADCENADDR          0x074
  63 #define TEMP_ADCVALIDADDR       0x078
  64 #define TEMP_ADCVOLTADDR        0x07c
  65 #define TEMP_RDCTRL             0x080
  66 #define TEMP_ADCVALIDMASK       0x084
  67 #define TEMP_ADCVOLTAGESHIFT    0x088
  68 #define TEMP_ADCWRITECTRL       0x08c
  69 #define TEMP_MSR0               0x090
  70 #define TEMP_MSR1               0x094
  71 #define TEMP_MSR2               0x098
  72 #define TEMP_MSR3               0x0B8
  73
  74 #define TEMP_SPARE0             0x0f0
  75
  76 #define PTPCORESEL              0x400
  77
  78 #define TEMP_MONCTL1_PERIOD_UNIT(x)     ((x) & 0x3ff)
  79
  80 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
  81 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
  82
  83 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)       (x)
  84
  85 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE         BIT(0)
  86 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE         BIT(1)
  87
  88 #define TEMP_ADCVALIDMASK_VALID_HIGH            BIT(5)
  89 #define TEMP_ADCVALIDMASK_VALID_POS(bit)        (bit)
  90
  91 #define MT8173_TS1      0
  92 #define MT8173_TS2      1
  93 #define MT8173_TS3      2
  94 #define MT8173_TS4      3
  95 #define MT8173_TSABB    4
  96
  97 /* AUXADC channel 11 is used for the temperature sensors */
  98 #define MT8173_TEMP_AUXADC_CHANNEL      11
  99
 100 /* The total number of temperature sensors in the MT8173 */
 101 #define MT8173_NUM_SENSORS              5
 102
 103 /* The number of banks in the MT8173 */
 104 #define MT8173_NUM_ZONES                4
 105
 106 /* The number of sensing points per bank */
 107 #define MT8173_NUM_SENSORS_PER_ZONE     4
 108
 109 /* Layout of the fuses providing the calibration data */
 110 #define MT8173_CALIB_BUF0_VALID         BIT(0)
 111 #define MT8173_CALIB_BUF1_ADC_GE(x)     (((x) >> 22) & 0x3ff)
 112 #define MT8173_CALIB_BUF0_VTS_TS1(x)    (((x) >> 17) & 0x1ff)
 113 #define MT8173_CALIB_BUF0_VTS_TS2(x)    (((x) >> 8) & 0x1ff)
 114 #define MT8173_CALIB_BUF1_VTS_TS3(x)    (((x) >> 0) & 0x1ff)
 115 #define MT8173_CALIB_BUF2_VTS_TS4(x)    (((x) >> 23) & 0x1ff)
 116 #define MT8173_CALIB_BUF2_VTS_TSABB(x)  (((x) >> 14) & 0x1ff)
 117 #define MT8173_CALIB_BUF0_DEGC_CALI(x)  (((x) >> 1) & 0x3f)
 118 #define MT8173_CALIB_BUF0_O_SLOPE(x)    (((x) >> 26) & 0x3f)
 119
 120 #define THERMAL_NAME    "mtk-thermal"
 121
 122 struct mtk_thermal;
 123
 124 struct mtk_thermal_bank {
 125         struct mtk_thermal *mt;
 126         int id;
 127 };
 128
 129 struct mtk_thermal {
 130         struct device *dev;
 131         void __iomem *thermal_base;
 132
 133         struct clk *clk_peri_therm;
 134         struct clk *clk_auxadc;
 135
 136         struct mtk_thermal_bank banks[MT8173_NUM_ZONES];
 137
 138         /* lock: for getting and putting banks */
 139         struct mutex lock;
 140
 141         /* Calibration values */
 142         s32 adc_ge;
 143         s32 degc_cali;
 144         s32 o_slope;
 145         s32 vts[MT8173_NUM_SENSORS];
 146
 147         struct thermal_zone_device *tzd;
 148 };
 149
 150 struct mtk_thermal_bank_cfg {
 151         unsigned int num_sensors;
 152         unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE];
 153 };
 154
 155 static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
 156
 157 /*
 158  * The MT8173 thermal controller has four banks. Each bank can read up to
 159  * four temperature sensors simultaneously. The MT8173 has a total of 5
 160  * temperature sensors. We use each bank to measure a certain area of the
 161  * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
 162  * areas, hence is used in different banks.
 163  *
 164  * The thermal core only gets the maximum temperature of all banks, so
 165  * the bank concept wouldn't be necessary here. However, the SVS (Smart
 166  * Voltage Scaling) unit makes its decisions based on the same bank
 167  * data, and this indeed needs the temperatures of the individual banks
 168  * for making better decisions.
 169  */
 170 static const struct mtk_thermal_bank_cfg bank_data[] = {
 171         {
 172                 .num_sensors = 2,
 173                 .sensors = { MT8173_TS2, MT8173_TS3 },
 174         }, {
 175                 .num_sensors = 2,
 176                 .sensors = { MT8173_TS2, MT8173_TS4 },
 177         }, {
 178                 .num_sensors = 3,
 179                 .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
 180         }, {
 181                 .num_sensors = 1,
 182                 .sensors = { MT8173_TS2 },
 183         },
 184 };
 185
 186 struct mtk_thermal_sense_point {
 187         int msr;
 188         int adcpnp;
 189 };
 190
 191 static const struct mtk_thermal_sense_point
 192                 sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = {
 193         {
 194                 .msr = TEMP_MSR0,
 195                 .adcpnp = TEMP_ADCPNP0,
 196         }, {
 197                 .msr = TEMP_MSR1,
 198                 .adcpnp = TEMP_ADCPNP1,
 199         }, {
 200                 .msr = TEMP_MSR2,
 201                 .adcpnp = TEMP_ADCPNP2,
 202         }, {
 203                 .msr = TEMP_MSR3,
 204                 .adcpnp = TEMP_ADCPNP3,
 205         },
 206 };
 207
 208 /**
 209  * raw_to_mcelsius - convert a raw ADC value to mcelsius
 210  * @mt:         The thermal controller
 211  * @raw:        raw ADC value
 212  *
 213  * This converts the raw ADC value to mcelsius using the SoC specific
 214  * calibration constants
 215  */
 216 static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
 217 {
 218         s32 tmp;
 219
 220         raw &= 0xfff;
 221
 222         tmp = 203450520 << 3;
 223         tmp /= 165 + mt->o_slope;
 224         tmp /= 10000 + mt->adc_ge;
 225         tmp *= raw - mt->vts[sensno] - 3350;
 226         tmp >>= 3;
 227
 228         return mt->degc_cali * 500 - tmp;
 229 }
 230
 231 /**
 232  * mtk_thermal_get_bank - get bank
 233  * @bank:       The bank
 234  *
 235  * The bank registers are banked, we have to select a bank in the
 236  * PTPCORESEL register to access it.
 237  */
 238 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
 239 {
 240         struct mtk_thermal *mt = bank->mt;
 241         u32 val;
 242
 243         mutex_lock(&mt->lock);
 244
 245         val = readl(mt->thermal_base + PTPCORESEL);
 246         val &= ~0xf;
 247         val |= bank->id;
 248         writel(val, mt->thermal_base + PTPCORESEL);
 249 }
 250
 251 /**
 252  * mtk_thermal_put_bank - release bank
 253  * @bank:       The bank
 254  *
 255  * release a bank previously taken with mtk_thermal_get_bank,
 256  */
 257 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
 258 {
 259         struct mtk_thermal *mt = bank->mt;
 260
 261         mutex_unlock(&mt->lock);
 262 }
 263
 264 /**
 265  * mtk_thermal_bank_temperature - get the temperature of a bank
 266  * @bank:       The bank
 267  *
 268  * The temperature of a bank is considered the maximum temperature of
 269  * the sensors associated to the bank.
 270  */
 271 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
 272 {
 273         struct mtk_thermal *mt = bank->mt;
 274         int i, temp = INT_MIN, max = INT_MIN;
 275         u32 raw;
 276
 277         for (i = 0; i < bank_data[bank->id].num_sensors; i++) {
 278                 raw = readl(mt->thermal_base + sensing_points[i].msr);
 279
 280                 temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw);
 281
 282                 /*
 283                  * The first read of a sensor often contains very high bogus
 284                  * temperature value. Filter these out so that the system does
 285                  * not immediately shut down.
 286                  */
 287                 if (temp > 200000)
 288                         temp = 0;
 289
 290                 if (temp > max)
 291                         max = temp;
 292         }
 293
 294         return max;
 295 }
 296
 297 static int mtk_read_temp(void *data, int *temperature)
 298 {
 299         struct mtk_thermal *mt = data;
 300         int i;
 301         int tempmax = INT_MIN;
 302
 303         for (i = 0; i < MT8173_NUM_ZONES; i++) {
 304                 struct mtk_thermal_bank *bank = &mt->banks[i];
 305
 306                 mtk_thermal_get_bank(bank);
 307
 308                 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
 309
 310                 mtk_thermal_put_bank(bank);
 311         }
 312
 313         *temperature = tempmax;
 314
 315         return 0;
 316 }
 317
 318 static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
 319         .get_temp = mtk_read_temp,
 320 };
 321
 322 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
 323                                   u32 apmixed_phys_base, u32 auxadc_phys_base)
 324 {
 325         struct mtk_thermal_bank *bank = &mt->banks[num];
 326         const struct mtk_thermal_bank_cfg *cfg = &bank_data[num];
 327         int i;
 328
 329         bank->id = num;
 330         bank->mt = mt;
 331
 332         mtk_thermal_get_bank(bank);
 333
 334         /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
 335         writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);
 336
 337         /*
 338          * filt interval is 1 * 46.540us = 46.54us,
 339          * sen interval is 429 * 46.540us = 19.96ms
 340          */
 341         writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
 342                         TEMP_MONCTL2_SENSOR_INTERVAL(429),
 343                         mt->thermal_base + TEMP_MONCTL2);
 344
 345         /* poll is set to 10u */
 346         writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
 347                mt->thermal_base + TEMP_AHBPOLL);
 348
 349         /* temperature sampling control, 1 sample */
 350         writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
 351
 352         /* exceed this polling time, IRQ would be inserted */
 353         writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);
 354
 355         /* number of interrupts per event, 1 is enough */
 356         writel(0x0, mt->thermal_base + TEMP_MONIDET0);
 357         writel(0x0, mt->thermal_base + TEMP_MONIDET1);
 358
 359         /*
 360          * The MT8173 thermal controller does not have its own ADC. Instead it
 361          * uses AHB bus accesses to control the AUXADC. To do this the thermal
 362          * controller has to be programmed with the physical addresses of the
 363          * AUXADC registers and with the various bit positions in the AUXADC.
 364          * Also the thermal controller controls a mux in the APMIXEDSYS register
 365          * space.
 366          */
 367
 368         /*
 369          * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
 370          * automatically by hw
 371          */
 372         writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX);
 373
 374         /* AHB address for auxadc mux selection */
 375         writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
 376                mt->thermal_base + TEMP_ADCMUXADDR);
 377
 378         /* AHB address for pnp sensor mux selection */
 379         writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
 380                mt->thermal_base + TEMP_PNPMUXADDR);
 381
 382         /* AHB value for auxadc enable */
 383         writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN);
 384
 385         /* AHB address for auxadc enable (channel 0 immediate mode selected) */
 386         writel(auxadc_phys_base + AUXADC_CON1_SET_V,
 387                mt->thermal_base + TEMP_ADCENADDR);
 388
 389         /* AHB address for auxadc valid bit */
 390         writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
 391                mt->thermal_base + TEMP_ADCVALIDADDR);
 392
 393         /* AHB address for auxadc voltage output */
 394         writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
 395                mt->thermal_base + TEMP_ADCVOLTADDR);
 396
 397         /* read valid & voltage are at the same register */
 398         writel(0x0, mt->thermal_base + TEMP_RDCTRL);
 399
 400         /* indicate where the valid bit is */
 401         writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
 402                mt->thermal_base + TEMP_ADCVALIDMASK);
 403
 404         /* no shift */
 405         writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
 406
 407         /* enable auxadc mux write transaction */
 408         writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
 409                mt->thermal_base + TEMP_ADCWRITECTRL);
 410
 411         for (i = 0; i < cfg->num_sensors; i++)
 412                 writel(sensor_mux_values[cfg->sensors[i]],
 413                        mt->thermal_base + sensing_points[i].adcpnp);
 414
 415         writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0);
 416
 417         writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
 418                TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
 419                mt->thermal_base + TEMP_ADCWRITECTRL);
 420
 421         mtk_thermal_put_bank(bank);
 422 }
 423
 424 static u64 of_get_phys_base(struct device_node *np)
 425 {
 426         u64 size64;
 427         const __be32 *regaddr_p;
 428
 429         regaddr_p = of_get_address(np, 0, &size64, NULL);
 430         if (!regaddr_p)
 431                 return OF_BAD_ADDR;
 432
 433         return of_translate_address(np, regaddr_p);
 434 }
 435
 436 static int mtk_thermal_get_calibration_data(struct device *dev,
 437                                             struct mtk_thermal *mt)
 438 {
 439         struct nvmem_cell *cell;
 440         u32 *buf;
 441         size_t len;
 442         int i, ret = 0;
 443
 444         /* Start with default values */
 445         mt->adc_ge = 512;
 446         for (i = 0; i < MT8173_NUM_SENSORS; i++)
 447                 mt->vts[i] = 260;
 448         mt->degc_cali = 40;
 449         mt->o_slope = 0;
 450
 451         cell = nvmem_cell_get(dev, "calibration-data");
 452         if (IS_ERR(cell)) {
 453                 if (PTR_ERR(cell) == -EPROBE_DEFER)
 454                         return PTR_ERR(cell);
 455                 return 0;
 456         }
 457
 458         buf = (u32 *)nvmem_cell_read(cell, &len);
 459
 460         nvmem_cell_put(cell);
 461
 462         if (IS_ERR(buf))
 463                 return PTR_ERR(buf);
 464
 465         if (len < 3 * sizeof(u32)) {
 466                 dev_warn(dev, "invalid calibration data\n");
 467                 ret = -EINVAL;
 468                 goto out;
 469         }
 470
 471         if (buf[0] & MT8173_CALIB_BUF0_VALID) {
 472                 mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]);
 473                 mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]);
 474                 mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]);
 475                 mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]);
 476                 mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]);
 477                 mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]);
 478                 mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]);
 479                 mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
 480         } else {
 481                 dev_info(dev, "Device not calibrated, using default calibration values\n");
 482         }
 483
 484 out:
 485         kfree(buf);
 486
 487         return ret;
 488 }
 489
 490 static int mtk_thermal_probe(struct platform_device *pdev)
 491 {
 492         int ret, i;
 493         struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
 494         struct mtk_thermal *mt;
 495         struct resource *res;
 496         u64 auxadc_phys_base, apmixed_phys_base;
 497
 498         mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
 499         if (!mt)
 500                 return -ENOMEM;
 501
 502         mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
 503         if (IS_ERR(mt->clk_peri_therm))
 504                 return PTR_ERR(mt->clk_peri_therm);
 505
 506         mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
 507         if (IS_ERR(mt->clk_auxadc))
 508                 return PTR_ERR(mt->clk_auxadc);
 509
 510         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 511         mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
 512         if (IS_ERR(mt->thermal_base))
 513                 return PTR_ERR(mt->thermal_base);
 514
 515         ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
 516         if (ret)
 517                 return ret;
 518
 519         mutex_init(&mt->lock);
 520
 521         mt->dev = &pdev->dev;
 522
 523         auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
 524         if (!auxadc) {
 525                 dev_err(&pdev->dev, "missing auxadc node\n");
 526                 return -ENODEV;
 527         }
 528
 529         auxadc_phys_base = of_get_phys_base(auxadc);
 530
 531         of_node_put(auxadc);
 532
 533         if (auxadc_phys_base == OF_BAD_ADDR) {
 534                 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
 535                 return -EINVAL;
 536         }
 537
 538         apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
 539         if (!apmixedsys) {
 540                 dev_err(&pdev->dev, "missing apmixedsys node\n");
 541                 return -ENODEV;
 542         }
 543
 544         apmixed_phys_base = of_get_phys_base(apmixedsys);
 545
 546         of_node_put(apmixedsys);
 547
 548         if (apmixed_phys_base == OF_BAD_ADDR) {
 549                 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
 550                 return -EINVAL;
 551         }
 552
 553         ret = clk_prepare_enable(mt->clk_auxadc);
 554         if (ret) {
 555                 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
 556                 return ret;
 557         }
 558
 559         ret = device_reset(&pdev->dev);
 560         if (ret)
 561                 goto err_disable_clk_auxadc;
 562
 563         ret = clk_prepare_enable(mt->clk_peri_therm);
 564         if (ret) {
 565                 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
 566                 goto err_disable_clk_auxadc;
 567         }
 568
 569         for (i = 0; i < MT8173_NUM_ZONES; i++)
 570                 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
 571                                       auxadc_phys_base);
 572
 573         platform_set_drvdata(pdev, mt);
 574
 575         mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
 576                                 &mtk_thermal_ops);
 577         if (IS_ERR(mt->tzd))
 578                 goto err_register;
 579
 580         return 0;
 581
 582 err_register:
 583         clk_disable_unprepare(mt->clk_peri_therm);
 584
 585 err_disable_clk_auxadc:
 586         clk_disable_unprepare(mt->clk_auxadc);
 587
 588         return ret;
 589 }
 590
 591 static int mtk_thermal_remove(struct platform_device *pdev)
 592 {
 593         struct mtk_thermal *mt = platform_get_drvdata(pdev);
 594
 595         thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd);
 596
 597         clk_disable_unprepare(mt->clk_peri_therm);
 598         clk_disable_unprepare(mt->clk_auxadc);
 599
 600         return 0;
 601 }
 602
 603 static const struct of_device_id mtk_thermal_of_match[] = {
 604         {
 605                 .compatible = "mediatek,mt8173-thermal",
 606         }, {
 607         },
 608 };
 609
 610 static struct platform_driver mtk_thermal_driver = {
 611         .probe = mtk_thermal_probe,
 612         .remove = mtk_thermal_remove,
 613         .driver = {
 614                 .name = THERMAL_NAME,
 615                 .of_match_table = mtk_thermal_of_match,
 616         },
 617 };
 618
 619 module_platform_driver(mtk_thermal_driver);
 620
 621 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
 622 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
 623 MODULE_DESCRIPTION("Mediatek thermal driver");
 624 MODULE_LICENSE("GPL v2");