?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
fs: make fiemap work from compat_ioctl
[linux/fpc-iii.git] / drivers / gpio / gpio-merrifield.c
blobec8560298805c8e6b7724b8c1dc97171e10ab39f
1 /*
2 * Intel Merrifield SoC GPIO driver
3 *
4 * Copyright (c) 2016 Intel Corporation.
5 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/pinctrl/consumer.h>
20
21 #define GCCR 0x000 /* controller configuration */
22 #define GPLR 0x004 /* pin level r/o */
23 #define GPDR 0x01c /* pin direction */
24 #define GPSR 0x034 /* pin set w/o */
25 #define GPCR 0x04c /* pin clear w/o */
26 #define GRER 0x064 /* rising edge detect */
27 #define GFER 0x07c /* falling edge detect */
28 #define GFBR 0x094 /* glitch filter bypass */
29 #define GIMR 0x0ac /* interrupt mask */
30 #define GISR 0x0c4 /* interrupt source */
31 #define GITR 0x300 /* input type */
32 #define GLPR 0x318 /* level input polarity */
33 #define GWMR 0x400 /* wake mask */
34 #define GWSR 0x418 /* wake source */
35 #define GSIR 0xc00 /* secure input */
36
37 /* Intel Merrifield has 192 GPIO pins */
38 #define MRFLD_NGPIO 192
39
40 struct mrfld_gpio_pinrange {
41 unsigned int gpio_base;
42 unsigned int pin_base;
43 unsigned int npins;
44 };
45
46 #define GPIO_PINRANGE(gstart, gend, pstart) \
47 { \
48 .gpio_base = (gstart), \
49 .pin_base = (pstart), \
50 .npins = (gend) - (gstart) + 1, \
51 }
52
53 struct mrfld_gpio {
54 struct gpio_chip chip;
55 void __iomem *reg_base;
56 raw_spinlock_t lock;
57 struct device *dev;
58 };
59
60 static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
61 GPIO_PINRANGE(0, 11, 146),
62 GPIO_PINRANGE(12, 13, 144),
63 GPIO_PINRANGE(14, 15, 35),
64 GPIO_PINRANGE(16, 16, 164),
65 GPIO_PINRANGE(17, 18, 105),
66 GPIO_PINRANGE(19, 22, 101),
67 GPIO_PINRANGE(23, 30, 107),
68 GPIO_PINRANGE(32, 43, 67),
69 GPIO_PINRANGE(44, 63, 195),
70 GPIO_PINRANGE(64, 67, 140),
71 GPIO_PINRANGE(68, 69, 165),
72 GPIO_PINRANGE(70, 71, 65),
73 GPIO_PINRANGE(72, 76, 228),
74 GPIO_PINRANGE(77, 86, 37),
75 GPIO_PINRANGE(87, 87, 48),
76 GPIO_PINRANGE(88, 88, 47),
77 GPIO_PINRANGE(89, 96, 49),
78 GPIO_PINRANGE(97, 97, 34),
79 GPIO_PINRANGE(102, 119, 83),
80 GPIO_PINRANGE(120, 123, 79),
81 GPIO_PINRANGE(124, 135, 115),
82 GPIO_PINRANGE(137, 142, 158),
83 GPIO_PINRANGE(154, 163, 24),
84 GPIO_PINRANGE(164, 176, 215),
85 GPIO_PINRANGE(177, 189, 127),
86 GPIO_PINRANGE(190, 191, 178),
87 };
88
89 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
90 unsigned int reg_type_offset)
91 {
92 struct mrfld_gpio *priv = gpiochip_get_data(chip);
93 u8 reg = offset / 32;
94
95 return priv->reg_base + reg_type_offset + reg * 4;
96 }
97
98 static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset)
99 {
100 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
101
102 return !!(readl(gplr) & BIT(offset % 32));
103 }
104
105 static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset,
106 int value)
107 {
108 struct mrfld_gpio *priv = gpiochip_get_data(chip);
109 void __iomem *gpsr, *gpcr;
110 unsigned long flags;
111
112 raw_spin_lock_irqsave(&priv->lock, flags);
113
114 if (value) {
115 gpsr = gpio_reg(chip, offset, GPSR);
116 writel(BIT(offset % 32), gpsr);
117 } else {
118 gpcr = gpio_reg(chip, offset, GPCR);
119 writel(BIT(offset % 32), gpcr);
120 }
121
122 raw_spin_unlock_irqrestore(&priv->lock, flags);
123 }
124
125 static int mrfld_gpio_direction_input(struct gpio_chip *chip,
126 unsigned int offset)
127 {
128 struct mrfld_gpio *priv = gpiochip_get_data(chip);
129 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
130 unsigned long flags;
131 u32 value;
132
133 raw_spin_lock_irqsave(&priv->lock, flags);
134
135 value = readl(gpdr);
136 value &= ~BIT(offset % 32);
137 writel(value, gpdr);
138
139 raw_spin_unlock_irqrestore(&priv->lock, flags);
140
141 return 0;
142 }
143
144 static int mrfld_gpio_direction_output(struct gpio_chip *chip,
145 unsigned int offset, int value)
146 {
147 struct mrfld_gpio *priv = gpiochip_get_data(chip);
148 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
149 unsigned long flags;
150
151 mrfld_gpio_set(chip, offset, value);
152
153 raw_spin_lock_irqsave(&priv->lock, flags);
154
155 value = readl(gpdr);
156 value |= BIT(offset % 32);
157 writel(value, gpdr);
158
159 raw_spin_unlock_irqrestore(&priv->lock, flags);
160
161 return 0;
162 }
163
164 static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
165 {
166 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
167
168 return !(readl(gpdr) & BIT(offset % 32));
169 }
170
171 static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
172 unsigned int debounce)
173 {
174 struct mrfld_gpio *priv = gpiochip_get_data(chip);
175 void __iomem *gfbr = gpio_reg(chip, offset, GFBR);
176 unsigned long flags;
177 u32 value;
178
179 raw_spin_lock_irqsave(&priv->lock, flags);
180
181 if (debounce)
182 value = readl(gfbr) & ~BIT(offset % 32);
183 else
184 value = readl(gfbr) | BIT(offset % 32);
185 writel(value, gfbr);
186
187 raw_spin_unlock_irqrestore(&priv->lock, flags);
188
189 return 0;
190 }
191
192 static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
193 unsigned long config)
194 {
195 u32 debounce;
196
197 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
198 return -ENOTSUPP;
199
200 debounce = pinconf_to_config_argument(config);
201 return mrfld_gpio_set_debounce(chip, offset, debounce);
202 }
203
204 static void mrfld_irq_ack(struct irq_data *d)
205 {
206 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
207 u32 gpio = irqd_to_hwirq(d);
208 void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR);
209 unsigned long flags;
210
211 raw_spin_lock_irqsave(&priv->lock, flags);
212
213 writel(BIT(gpio % 32), gisr);
214
215 raw_spin_unlock_irqrestore(&priv->lock, flags);
216 }
217
218 static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask)
219 {
220 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
221 u32 gpio = irqd_to_hwirq(d);
222 void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
223 unsigned long flags;
224 u32 value;
225
226 raw_spin_lock_irqsave(&priv->lock, flags);
227
228 if (unmask)
229 value = readl(gimr) | BIT(gpio % 32);
230 else
231 value = readl(gimr) & ~BIT(gpio % 32);
232 writel(value, gimr);
233
234 raw_spin_unlock_irqrestore(&priv->lock, flags);
235 }
236
237 static void mrfld_irq_mask(struct irq_data *d)
238 {
239 mrfld_irq_unmask_mask(d, false);
240 }
241
242 static void mrfld_irq_unmask(struct irq_data *d)
243 {
244 mrfld_irq_unmask_mask(d, true);
245 }
246
247 static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
248 {
249 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
250 struct mrfld_gpio *priv = gpiochip_get_data(gc);
251 u32 gpio = irqd_to_hwirq(d);
252 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
253 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
254 void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
255 void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
256 unsigned long flags;
257 u32 value;
258
259 raw_spin_lock_irqsave(&priv->lock, flags);
260
261 if (type & IRQ_TYPE_EDGE_RISING)
262 value = readl(grer) | BIT(gpio % 32);
263 else
264 value = readl(grer) & ~BIT(gpio % 32);
265 writel(value, grer);
266
267 if (type & IRQ_TYPE_EDGE_FALLING)
268 value = readl(gfer) | BIT(gpio % 32);
269 else
270 value = readl(gfer) & ~BIT(gpio % 32);
271 writel(value, gfer);
272
273 /*
274 * To prevent glitches from triggering an unintended level interrupt,
275 * configure GLPR register first and then configure GITR.
276 */
277 if (type & IRQ_TYPE_LEVEL_LOW)
278 value = readl(glpr) | BIT(gpio % 32);
279 else
280 value = readl(glpr) & ~BIT(gpio % 32);
281 writel(value, glpr);
282
283 if (type & IRQ_TYPE_LEVEL_MASK) {
284 value = readl(gitr) | BIT(gpio % 32);
285 writel(value, gitr);
286
287 irq_set_handler_locked(d, handle_level_irq);
288 } else if (type & IRQ_TYPE_EDGE_BOTH) {
289 value = readl(gitr) & ~BIT(gpio % 32);
290 writel(value, gitr);
291
292 irq_set_handler_locked(d, handle_edge_irq);
293 }
294
295 raw_spin_unlock_irqrestore(&priv->lock, flags);
296
297 return 0;
298 }
299
300 static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on)
301 {
302 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
303 struct mrfld_gpio *priv = gpiochip_get_data(gc);
304 u32 gpio = irqd_to_hwirq(d);
305 void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR);
306 void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR);
307 unsigned long flags;
308 u32 value;
309
310 raw_spin_lock_irqsave(&priv->lock, flags);
311
312 /* Clear the existing wake status */
313 writel(BIT(gpio % 32), gwsr);
314
315 if (on)
316 value = readl(gwmr) | BIT(gpio % 32);
317 else
318 value = readl(gwmr) & ~BIT(gpio % 32);
319 writel(value, gwmr);
320
321 raw_spin_unlock_irqrestore(&priv->lock, flags);
322
323 dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio);
324 return 0;
325 }
326
327 static struct irq_chip mrfld_irqchip = {
328 .name = "gpio-merrifield",
329 .irq_ack = mrfld_irq_ack,
330 .irq_mask = mrfld_irq_mask,
331 .irq_unmask = mrfld_irq_unmask,
332 .irq_set_type = mrfld_irq_set_type,
333 .irq_set_wake = mrfld_irq_set_wake,
334 };
335
336 static void mrfld_irq_handler(struct irq_desc *desc)
337 {
338 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
339 struct mrfld_gpio *priv = gpiochip_get_data(gc);
340 struct irq_chip *irqchip = irq_desc_get_chip(desc);
341 unsigned long base, gpio;
342
343 chained_irq_enter(irqchip, desc);
344
345 /* Check GPIO controller to check which pin triggered the interrupt */
346 for (base = 0; base < priv->chip.ngpio; base += 32) {
347 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
348 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
349 unsigned long pending, enabled;
350
351 pending = readl(gisr);
352 enabled = readl(gimr);
353
354 /* Only interrupts that are enabled */
355 pending &= enabled;
356
357 for_each_set_bit(gpio, &pending, 32) {
358 unsigned int irq;
359
360 irq = irq_find_mapping(gc->irqdomain, base + gpio);
361 generic_handle_irq(irq);
362 }
363 }
364
365 chained_irq_exit(irqchip, desc);
366 }
367
368 static void mrfld_irq_init_hw(struct mrfld_gpio *priv)
369 {
370 void __iomem *reg;
371 unsigned int base;
372
373 for (base = 0; base < priv->chip.ngpio; base += 32) {
374 /* Clear the rising-edge detect register */
375 reg = gpio_reg(&priv->chip, base, GRER);
376 writel(0, reg);
377 /* Clear the falling-edge detect register */
378 reg = gpio_reg(&priv->chip, base, GFER);
379 writel(0, reg);
380 }
381 }
382
383 static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
384 {
385 const struct mrfld_gpio_pinrange *range;
386 struct mrfld_gpio *priv;
387 u32 gpio_base, irq_base;
388 void __iomem *base;
389 unsigned int i;
390 int retval;
391
392 retval = pcim_enable_device(pdev);
393 if (retval)
394 return retval;
395
396 retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
397 if (retval) {
398 dev_err(&pdev->dev, "I/O memory mapping error\n");
399 return retval;
400 }
401
402 base = pcim_iomap_table(pdev)[1];
403
404 irq_base = readl(base);
405 gpio_base = readl(sizeof(u32) + base);
406
407 /* Release the IO mapping, since we already get the info from BAR1 */
408 pcim_iounmap_regions(pdev, BIT(1));
409
410 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
411 if (!priv) {
412 dev_err(&pdev->dev, "can't allocate chip data\n");
413 return -ENOMEM;
414 }
415
416 priv->dev = &pdev->dev;
417 priv->reg_base = pcim_iomap_table(pdev)[0];
418
419 priv->chip.label = dev_name(&pdev->dev);
420 priv->chip.parent = &pdev->dev;
421 priv->chip.request = gpiochip_generic_request;
422 priv->chip.free = gpiochip_generic_free;
423 priv->chip.direction_input = mrfld_gpio_direction_input;
424 priv->chip.direction_output = mrfld_gpio_direction_output;
425 priv->chip.get = mrfld_gpio_get;
426 priv->chip.set = mrfld_gpio_set;
427 priv->chip.get_direction = mrfld_gpio_get_direction;
428 priv->chip.set_config = mrfld_gpio_set_config;
429 priv->chip.base = gpio_base;
430 priv->chip.ngpio = MRFLD_NGPIO;
431 priv->chip.can_sleep = false;
432
433 raw_spin_lock_init(&priv->lock);
434
435 pci_set_drvdata(pdev, priv);
436 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
437 if (retval) {
438 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
439 return retval;
440 }
441
442 for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
443 range = &mrfld_gpio_ranges[i];
444 retval = gpiochip_add_pin_range(&priv->chip,
445 "pinctrl-merrifield",
446 range->gpio_base,
447 range->pin_base,
448 range->npins);
449 if (retval) {
450 dev_err(&pdev->dev, "failed to add GPIO pin range\n");
451 return retval;
452 }
453 }
454
455 retval = gpiochip_irqchip_add(&priv->chip, &mrfld_irqchip, irq_base,
456 handle_bad_irq, IRQ_TYPE_NONE);
457 if (retval) {
458 dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n");
459 return retval;
460 }
461
462 mrfld_irq_init_hw(priv);
463
464 gpiochip_set_chained_irqchip(&priv->chip, &mrfld_irqchip, pdev->irq,
465 mrfld_irq_handler);
466
467 return 0;
468 }
469
470 static const struct pci_device_id mrfld_gpio_ids[] = {
471 { PCI_VDEVICE(INTEL, 0x1199) },
472 { }
473 };
474 MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
475
476 static struct pci_driver mrfld_gpio_driver = {
477 .name = "gpio-merrifield",
478 .id_table = mrfld_gpio_ids,
479 .probe = mrfld_gpio_probe,
480 };
481
482 module_pci_driver(mrfld_gpio_driver);
483
484 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
485 MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
486 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support