| blob | c32d073282eabbf7ada03d814ba236e989c23d18 |
1 /*
2 * linux/arch/arm/mm/arm925.S: MMU functions for ARM925
3 *
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Copyright (C) 2002-2003 MontaVista Software, Inc.
8 *
9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
11 *
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * These are the low level assembler for performing cache and TLB
30 * functions on the arm925.
31 *
32 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
33 *
34 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
35 *
36 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
37 * entry mode" must be 0 to flush the entries in both segments
38 * at once. This is the default value. See TRM 2-20 and 2-24 for
39 * more information.
40 *
41 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
42 * like the "Transparent mode" must be on for partial cache flushes
43 * to work in this mode. This mode only works with 16-bit external
44 * memory. See TRM 2-24 for more information.
45 *
46 * NOTE3: Write-back cache flushing seems to be flakey with devices using
47 * direct memory access, such as USB OHCI. The workaround is to use
48 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
49 * the default for OMAP-1510).
50 */
52 #include <linux/linkage.h>
53 #include <linux/init.h>
54 #include <asm/assembler.h>
55 #include <asm/hwcap.h>
56 #include <asm/pgtable-hwdef.h>
57 #include <asm/pgtable.h>
58 #include <asm/page.h>
59 #include <asm/ptrace.h>
60 #include "proc-macros.S"
62 /*
63 * The size of one data cache line.
64 */
65 #define CACHE_DLINESIZE 16
67 /*
68 * The number of data cache segments.
69 */
70 #define CACHE_DSEGMENTS 2
72 /*
73 * The number of lines in a cache segment.
74 */
75 #define CACHE_DENTRIES 256
77 /*
78 * This is the size at which it becomes more efficient to
79 * clean the whole cache, rather than using the individual
80 * cache line maintenance instructions.
81 */
82 #define CACHE_DLIMIT 8192
84 .text
85 /*
86 * cpu_arm925_proc_init()
87 */
88 ENTRY(cpu_arm925_proc_init)
89 ret lr
91 /*
92 * cpu_arm925_proc_fin()
93 */
94 ENTRY(cpu_arm925_proc_fin)
95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 bic r0, r0, #0x1000 @ ...i............
97 bic r0, r0, #0x000e @ ............wca.
98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 ret lr
101 /*
102 * cpu_arm925_reset(loc)
103 *
104 * Perform a soft reset of the system. Put the CPU into the
105 * same state as it would be if it had been reset, and branch
106 * to what would be the reset vector.
107 *
108 * loc: location to jump to for soft reset
109 */
110 .align 5
111 .pushsection .idmap.text, "ax"
112 ENTRY(cpu_arm925_reset)
113 /* Send software reset to MPU and DSP */
114 mov ip, #0xff000000
115 orr ip, ip, #0x00fe0000
116 orr ip, ip, #0x0000ce00
117 mov r4, #1
118 strh r4, [ip, #0x10]
119 ENDPROC(cpu_arm925_reset)
120 .popsection
122 mov ip, #0
123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
124 mcr p15, 0, ip, c7, c10, 4 @ drain WB
125 #ifdef CONFIG_MMU
126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
127 #endif
128 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
129 bic ip, ip, #0x000f @ ............wcam
130 bic ip, ip, #0x1100 @ ...i...s........
131 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
132 ret r0
134 /*
135 * cpu_arm925_do_idle()
136 *
137 * Called with IRQs disabled
138 */
139 .align 10
140 ENTRY(cpu_arm925_do_idle)
141 mov r0, #0
142 mrc p15, 0, r1, c1, c0, 0 @ Read control register
143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
144 bic r2, r1, #1 << 12
145 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
147 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
148 ret lr
150 /*
151 * flush_icache_all()
152 *
153 * Unconditionally clean and invalidate the entire icache.
154 */
155 ENTRY(arm925_flush_icache_all)
156 mov r0, #0
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
158 ret lr
159 ENDPROC(arm925_flush_icache_all)
161 /*
162 * flush_user_cache_all()
163 *
164 * Clean and invalidate all cache entries in a particular
165 * address space.
166 */
167 ENTRY(arm925_flush_user_cache_all)
168 /* FALLTHROUGH */
170 /*
171 * flush_kern_cache_all()
172 *
173 * Clean and invalidate the entire cache.
174 */
175 ENTRY(arm925_flush_kern_cache_all)
176 mov r2, #VM_EXEC
177 mov ip, #0
178 __flush_whole_cache:
179 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
181 #else
182 /* Flush entries in both segments at once, see NOTE1 above */
183 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
184 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
185 subs r3, r3, #1 << 4
186 bcs 2b @ entries 255 to 0
187 #endif
188 tst r2, #VM_EXEC
189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
191 ret lr
193 /*
194 * flush_user_cache_range(start, end, flags)
195 *
196 * Clean and invalidate a range of cache entries in the
197 * specified address range.
198 *
199 * - start - start address (inclusive)
200 * - end - end address (exclusive)
201 * - flags - vm_flags describing address space
202 */
203 ENTRY(arm925_flush_user_cache_range)
204 mov ip, #0
205 sub r3, r1, r0 @ calculate total size
206 cmp r3, #CACHE_DLIMIT
207 bgt __flush_whole_cache
208 1: tst r2, #VM_EXEC
209 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
212 add r0, r0, #CACHE_DLINESIZE
213 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
214 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
215 add r0, r0, #CACHE_DLINESIZE
216 #else
217 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
218 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
219 add r0, r0, #CACHE_DLINESIZE
220 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
221 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
222 add r0, r0, #CACHE_DLINESIZE
223 #endif
224 cmp r0, r1
225 blo 1b
226 tst r2, #VM_EXEC
227 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
228 ret lr
230 /*
231 * coherent_kern_range(start, end)
232 *
233 * Ensure coherency between the Icache and the Dcache in the
234 * region described by start, end. If you have non-snooping
235 * Harvard caches, you need to implement this function.
236 *
237 * - start - virtual start address
238 * - end - virtual end address
239 */
240 ENTRY(arm925_coherent_kern_range)
241 /* FALLTHROUGH */
243 /*
244 * coherent_user_range(start, end)
245 *
246 * Ensure coherency between the Icache and the Dcache in the
247 * region described by start, end. If you have non-snooping
248 * Harvard caches, you need to implement this function.
249 *
250 * - start - virtual start address
251 * - end - virtual end address
252 */
253 ENTRY(arm925_coherent_user_range)
254 bic r0, r0, #CACHE_DLINESIZE - 1
255 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
256 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
257 add r0, r0, #CACHE_DLINESIZE
258 cmp r0, r1
259 blo 1b
260 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 mov r0, #0
262 ret lr
264 /*
265 * flush_kern_dcache_area(void *addr, size_t size)
266 *
267 * Ensure no D cache aliasing occurs, either with itself or
268 * the I cache
269 *
270 * - addr - kernel address
271 * - size - region size
272 */
273 ENTRY(arm925_flush_kern_dcache_area)
274 add r1, r0, r1
275 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
276 add r0, r0, #CACHE_DLINESIZE
277 cmp r0, r1
278 blo 1b
279 mov r0, #0
280 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
281 mcr p15, 0, r0, c7, c10, 4 @ drain WB
282 ret lr
284 /*
285 * dma_inv_range(start, end)
286 *
287 * Invalidate (discard) the specified virtual address range.
288 * May not write back any entries. If 'start' or 'end'
289 * are not cache line aligned, those lines must be written
290 * back.
291 *
292 * - start - virtual start address
293 * - end - virtual end address
294 *
295 * (same as v4wb)
296 */
297 arm925_dma_inv_range:
298 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
299 tst r0, #CACHE_DLINESIZE - 1
300 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
301 tst r1, #CACHE_DLINESIZE - 1
302 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
303 #endif
304 bic r0, r0, #CACHE_DLINESIZE - 1
305 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
306 add r0, r0, #CACHE_DLINESIZE
307 cmp r0, r1
308 blo 1b
309 mcr p15, 0, r0, c7, c10, 4 @ drain WB
310 ret lr
312 /*
313 * dma_clean_range(start, end)
314 *
315 * Clean the specified virtual address range.
316 *
317 * - start - virtual start address
318 * - end - virtual end address
319 *
320 * (same as v4wb)
321 */
322 arm925_dma_clean_range:
323 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
324 bic r0, r0, #CACHE_DLINESIZE - 1
325 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
326 add r0, r0, #CACHE_DLINESIZE
327 cmp r0, r1
328 blo 1b
329 #endif
330 mcr p15, 0, r0, c7, c10, 4 @ drain WB
331 ret lr
333 /*
334 * dma_flush_range(start, end)
335 *
336 * Clean and invalidate the specified virtual address range.
337 *
338 * - start - virtual start address
339 * - end - virtual end address
340 */
341 ENTRY(arm925_dma_flush_range)
342 bic r0, r0, #CACHE_DLINESIZE - 1
343 1:
344 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
345 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
346 #else
347 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
348 #endif
349 add r0, r0, #CACHE_DLINESIZE
350 cmp r0, r1
351 blo 1b
352 mcr p15, 0, r0, c7, c10, 4 @ drain WB
353 ret lr
355 /*
356 * dma_map_area(start, size, dir)
357 * - start - kernel virtual start address
358 * - size - size of region
359 * - dir - DMA direction
360 */
361 ENTRY(arm925_dma_map_area)
362 add r1, r1, r0
363 cmp r2, #DMA_TO_DEVICE
364 beq arm925_dma_clean_range
365 bcs arm925_dma_inv_range
366 b arm925_dma_flush_range
367 ENDPROC(arm925_dma_map_area)
369 /*
370 * dma_unmap_area(start, size, dir)
371 * - start - kernel virtual start address
372 * - size - size of region
373 * - dir - DMA direction
374 */
375 ENTRY(arm925_dma_unmap_area)
376 ret lr
377 ENDPROC(arm925_dma_unmap_area)
379 .globl arm925_flush_kern_cache_louis
380 .equ arm925_flush_kern_cache_louis, arm925_flush_kern_cache_all
382 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
383 define_cache_functions arm925
385 ENTRY(cpu_arm925_dcache_clean_area)
386 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
387 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
388 add r0, r0, #CACHE_DLINESIZE
389 subs r1, r1, #CACHE_DLINESIZE
390 bhi 1b
391 #endif
392 mcr p15, 0, r0, c7, c10, 4 @ drain WB
393 ret lr
395 /* =============================== PageTable ============================== */
397 /*
398 * cpu_arm925_switch_mm(pgd)
399 *
400 * Set the translation base pointer to be as described by pgd.
401 *
402 * pgd: new page tables
403 */
404 .align 5
405 ENTRY(cpu_arm925_switch_mm)
406 #ifdef CONFIG_MMU
407 mov ip, #0
408 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
409 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
410 #else
411 /* Flush entries in bothe segments at once, see NOTE1 above */
412 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
413 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
414 subs r3, r3, #1 << 4
415 bcs 2b @ entries 255 to 0
416 #endif
417 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
418 mcr p15, 0, ip, c7, c10, 4 @ drain WB
419 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
420 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
421 #endif
422 ret lr
424 /*
425 * cpu_arm925_set_pte_ext(ptep, pte, ext)
426 *
427 * Set a PTE and flush it out
428 */
429 .align 5
430 ENTRY(cpu_arm925_set_pte_ext)
431 #ifdef CONFIG_MMU
432 armv3_set_pte_ext
433 mov r0, r0
434 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
435 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
436 #endif
437 mcr p15, 0, r0, c7, c10, 4 @ drain WB
438 #endif /* CONFIG_MMU */
439 ret lr
441 .type __arm925_setup, #function
442 __arm925_setup:
443 mov r0, #0
444 #if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
445 orr r0,r0,#1 << 7
446 #endif
448 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
449 orr r0,r0,#1 << 1 @ transparent mode on
450 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
452 mov r0, #0
453 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
454 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
455 #ifdef CONFIG_MMU
456 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
457 #endif
459 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
460 mov r0, #4 @ disable write-back on caches explicitly
461 mcr p15, 7, r0, c15, c0, 0
462 #endif
464 adr r5, arm925_crval
465 ldmia r5, {r5, r6}
466 mrc p15, 0, r0, c1, c0 @ get control register v4
467 bic r0, r0, r5
468 orr r0, r0, r6
469 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
470 orr r0, r0, #0x4000 @ .1.. .... .... ....
471 #endif
472 ret lr
473 .size __arm925_setup, . - __arm925_setup
475 /*
476 * R
477 * .RVI ZFRS BLDP WCAM
478 * .011 0001 ..11 1101
479 *
480 */
481 .type arm925_crval, #object
482 arm925_crval:
483 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
485 __INITDATA
486 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
487 define_processor_functions arm925, dabort=v4t_early_abort, pabort=legacy_pabort
489 .section ".rodata"
491 string cpu_arch_name, "armv4t"
492 string cpu_elf_name, "v4"
493 string cpu_arm925_name, "ARM925T"
495 .align
497 .section ".proc.info.init", #alloc, #execinstr
499 .macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
500 .type __\name\()_proc_info,#object
501 __\name\()_proc_info:
502 .long \cpu_val
503 .long \cpu_mask
504 .long PMD_TYPE_SECT | \
505 PMD_SECT_CACHEABLE | \
506 PMD_BIT4 | \
507 PMD_SECT_AP_WRITE | \
508 PMD_SECT_AP_READ
509 .long PMD_TYPE_SECT | \
510 PMD_BIT4 | \
511 PMD_SECT_AP_WRITE | \
512 PMD_SECT_AP_READ
513 b __arm925_setup
514 .long cpu_arch_name
515 .long cpu_elf_name
516 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
517 .long cpu_arm925_name
518 .long arm925_processor_functions
519 .long v4wbi_tlb_fns
520 .long v4wb_user_fns
521 .long arm925_cache_fns
522 .size __\name\()_proc_info, . - __\name\()_proc_info
523 .endm
525 arm925_proc_info arm925, 0x54029250, 0xfffffff0, cpu_arm925_name
526 arm925_proc_info arm915, 0x54029150, 0xfffffff0, cpu_arm925_name