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irqchip/ts4800: Add TS-4800 interrupt controller
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / rv515.c
blobc55d653aaf5f6bcfb0b80d24ad1c42025d36e267
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include "rv515d.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "atom.h"
35 #include "rv515_reg_safe.h"
36
37 /* This files gather functions specifics to: rv515 */
38 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40 static void rv515_gpu_init(struct radeon_device *rdev);
41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
42
43 static const u32 crtc_offsets[2] =
44 {
45 0,
46 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
47 };
48
49 void rv515_debugfs(struct radeon_device *rdev)
50 {
51 if (r100_debugfs_rbbm_init(rdev)) {
52 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
53 }
54 if (rv515_debugfs_pipes_info_init(rdev)) {
55 DRM_ERROR("Failed to register debugfs file for pipes !\n");
56 }
57 if (rv515_debugfs_ga_info_init(rdev)) {
58 DRM_ERROR("Failed to register debugfs file for pipes !\n");
59 }
60 }
61
62 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
63 {
64 int r;
65
66 r = radeon_ring_lock(rdev, ring, 64);
67 if (r) {
68 return;
69 }
70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
71 radeon_ring_write(ring,
72 ISYNC_ANY2D_IDLE3D |
73 ISYNC_ANY3D_IDLE2D |
74 ISYNC_WAIT_IDLEGUI |
75 ISYNC_CPSCRATCH_IDLEGUI);
76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
77 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
79 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
81 radeon_ring_write(ring, 0);
82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
83 radeon_ring_write(ring, 0);
84 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
85 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
86 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
87 radeon_ring_write(ring, 0);
88 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
89 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
90 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
91 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
92 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
93 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
94 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
95 radeon_ring_write(ring, 0);
96 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
97 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
98 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
99 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
100 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
101 radeon_ring_write(ring,
102 ((6 << MS_X0_SHIFT) |
103 (6 << MS_Y0_SHIFT) |
104 (6 << MS_X1_SHIFT) |
105 (6 << MS_Y1_SHIFT) |
106 (6 << MS_X2_SHIFT) |
107 (6 << MS_Y2_SHIFT) |
108 (6 << MSBD0_Y_SHIFT) |
109 (6 << MSBD0_X_SHIFT)));
110 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
111 radeon_ring_write(ring,
112 ((6 << MS_X3_SHIFT) |
113 (6 << MS_Y3_SHIFT) |
114 (6 << MS_X4_SHIFT) |
115 (6 << MS_Y4_SHIFT) |
116 (6 << MS_X5_SHIFT) |
117 (6 << MS_Y5_SHIFT) |
118 (6 << MSBD1_SHIFT)));
119 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
120 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
121 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
122 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
123 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
124 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
125 radeon_ring_write(ring, PACKET0(0x20C8, 0));
126 radeon_ring_write(ring, 0);
127 radeon_ring_unlock_commit(rdev, ring, false);
128 }
129
130 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
131 {
132 unsigned i;
133 uint32_t tmp;
134
135 for (i = 0; i < rdev->usec_timeout; i++) {
136 /* read MC_STATUS */
137 tmp = RREG32_MC(MC_STATUS);
138 if (tmp & MC_STATUS_IDLE) {
139 return 0;
140 }
141 DRM_UDELAY(1);
142 }
143 return -1;
144 }
145
146 void rv515_vga_render_disable(struct radeon_device *rdev)
147 {
148 WREG32(R_000300_VGA_RENDER_CONTROL,
149 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
150 }
151
152 static void rv515_gpu_init(struct radeon_device *rdev)
153 {
154 unsigned pipe_select_current, gb_pipe_select, tmp;
155
156 if (r100_gui_wait_for_idle(rdev)) {
157 printk(KERN_WARNING "Failed to wait GUI idle while "
158 "resetting GPU. Bad things might happen.\n");
159 }
160 rv515_vga_render_disable(rdev);
161 r420_pipes_init(rdev);
162 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
163 tmp = RREG32(R300_DST_PIPE_CONFIG);
164 pipe_select_current = (tmp >> 2) & 3;
165 tmp = (1 << pipe_select_current) |
166 (((gb_pipe_select >> 8) & 0xF) << 4);
167 WREG32_PLL(0x000D, tmp);
168 if (r100_gui_wait_for_idle(rdev)) {
169 printk(KERN_WARNING "Failed to wait GUI idle while "
170 "resetting GPU. Bad things might happen.\n");
171 }
172 if (rv515_mc_wait_for_idle(rdev)) {
173 printk(KERN_WARNING "Failed to wait MC idle while "
174 "programming pipes. Bad things might happen.\n");
175 }
176 }
177
178 static void rv515_vram_get_type(struct radeon_device *rdev)
179 {
180 uint32_t tmp;
181
182 rdev->mc.vram_width = 128;
183 rdev->mc.vram_is_ddr = true;
184 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
185 switch (tmp) {
186 case 0:
187 rdev->mc.vram_width = 64;
188 break;
189 case 1:
190 rdev->mc.vram_width = 128;
191 break;
192 default:
193 rdev->mc.vram_width = 128;
194 break;
195 }
196 }
197
198 static void rv515_mc_init(struct radeon_device *rdev)
199 {
200
201 rv515_vram_get_type(rdev);
202 r100_vram_init_sizes(rdev);
203 radeon_vram_location(rdev, &rdev->mc, 0);
204 rdev->mc.gtt_base_align = 0;
205 if (!(rdev->flags & RADEON_IS_AGP))
206 radeon_gtt_location(rdev, &rdev->mc);
207 radeon_update_bandwidth_info(rdev);
208 }
209
210 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
211 {
212 unsigned long flags;
213 uint32_t r;
214
215 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
216 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
217 r = RREG32(MC_IND_DATA);
218 WREG32(MC_IND_INDEX, 0);
219 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
220
221 return r;
222 }
223
224 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
225 {
226 unsigned long flags;
227
228 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
229 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
230 WREG32(MC_IND_DATA, (v));
231 WREG32(MC_IND_INDEX, 0);
232 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
233 }
234
235 #if defined(CONFIG_DEBUG_FS)
236 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
237 {
238 struct drm_info_node *node = (struct drm_info_node *) m->private;
239 struct drm_device *dev = node->minor->dev;
240 struct radeon_device *rdev = dev->dev_private;
241 uint32_t tmp;
242
243 tmp = RREG32(GB_PIPE_SELECT);
244 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
245 tmp = RREG32(SU_REG_DEST);
246 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
247 tmp = RREG32(GB_TILE_CONFIG);
248 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
249 tmp = RREG32(DST_PIPE_CONFIG);
250 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
251 return 0;
252 }
253
254 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
255 {
256 struct drm_info_node *node = (struct drm_info_node *) m->private;
257 struct drm_device *dev = node->minor->dev;
258 struct radeon_device *rdev = dev->dev_private;
259 uint32_t tmp;
260
261 tmp = RREG32(0x2140);
262 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
263 radeon_asic_reset(rdev);
264 tmp = RREG32(0x425C);
265 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
266 return 0;
267 }
268
269 static struct drm_info_list rv515_pipes_info_list[] = {
270 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
271 };
272
273 static struct drm_info_list rv515_ga_info_list[] = {
274 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
275 };
276 #endif
277
278 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
279 {
280 #if defined(CONFIG_DEBUG_FS)
281 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
282 #else
283 return 0;
284 #endif
285 }
286
287 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
288 {
289 #if defined(CONFIG_DEBUG_FS)
290 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
291 #else
292 return 0;
293 #endif
294 }
295
296 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
297 {
298 u32 crtc_enabled, tmp, frame_count, blackout;
299 int i, j;
300
301 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
302 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
303
304 /* disable VGA render */
305 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
306 /* blank the display controllers */
307 for (i = 0; i < rdev->num_crtc; i++) {
308 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
309 if (crtc_enabled) {
310 save->crtc_enabled[i] = true;
311 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
312 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
313 radeon_wait_for_vblank(rdev, i);
314 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
315 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
316 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
317 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
318 }
319 /* wait for the next frame */
320 frame_count = radeon_get_vblank_counter(rdev, i);
321 for (j = 0; j < rdev->usec_timeout; j++) {
322 if (radeon_get_vblank_counter(rdev, i) != frame_count)
323 break;
324 udelay(1);
325 }
326
327 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
328 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
329 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
330 tmp &= ~AVIVO_CRTC_EN;
331 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
332 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
333 save->crtc_enabled[i] = false;
334 /* ***** */
335 } else {
336 save->crtc_enabled[i] = false;
337 }
338 }
339
340 radeon_mc_wait_for_idle(rdev);
341
342 if (rdev->family >= CHIP_R600) {
343 if (rdev->family >= CHIP_RV770)
344 blackout = RREG32(R700_MC_CITF_CNTL);
345 else
346 blackout = RREG32(R600_CITF_CNTL);
347 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
348 /* Block CPU access */
349 WREG32(R600_BIF_FB_EN, 0);
350 /* blackout the MC */
351 blackout |= R600_BLACKOUT_MASK;
352 if (rdev->family >= CHIP_RV770)
353 WREG32(R700_MC_CITF_CNTL, blackout);
354 else
355 WREG32(R600_CITF_CNTL, blackout);
356 }
357 }
358 /* wait for the MC to settle */
359 udelay(100);
360
361 /* lock double buffered regs */
362 for (i = 0; i < rdev->num_crtc; i++) {
363 if (save->crtc_enabled[i]) {
364 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
365 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
366 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
367 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
368 }
369 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
370 if (!(tmp & 1)) {
371 tmp |= 1;
372 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
373 }
374 }
375 }
376 }
377
378 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
379 {
380 u32 tmp, frame_count;
381 int i, j;
382
383 /* update crtc base addresses */
384 for (i = 0; i < rdev->num_crtc; i++) {
385 if (rdev->family >= CHIP_RV770) {
386 if (i == 0) {
387 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
388 upper_32_bits(rdev->mc.vram_start));
389 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
390 upper_32_bits(rdev->mc.vram_start));
391 } else {
392 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
393 upper_32_bits(rdev->mc.vram_start));
394 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
395 upper_32_bits(rdev->mc.vram_start));
396 }
397 }
398 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
399 (u32)rdev->mc.vram_start);
400 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
401 (u32)rdev->mc.vram_start);
402 }
403 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
404
405 /* unlock regs and wait for update */
406 for (i = 0; i < rdev->num_crtc; i++) {
407 if (save->crtc_enabled[i]) {
408 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
409 if ((tmp & 0x7) != 3) {
410 tmp &= ~0x7;
411 tmp |= 0x3;
412 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
413 }
414 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
415 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
416 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
417 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
418 }
419 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
420 if (tmp & 1) {
421 tmp &= ~1;
422 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
423 }
424 for (j = 0; j < rdev->usec_timeout; j++) {
425 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
426 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
427 break;
428 udelay(1);
429 }
430 }
431 }
432
433 if (rdev->family >= CHIP_R600) {
434 /* unblackout the MC */
435 if (rdev->family >= CHIP_RV770)
436 tmp = RREG32(R700_MC_CITF_CNTL);
437 else
438 tmp = RREG32(R600_CITF_CNTL);
439 tmp &= ~R600_BLACKOUT_MASK;
440 if (rdev->family >= CHIP_RV770)
441 WREG32(R700_MC_CITF_CNTL, tmp);
442 else
443 WREG32(R600_CITF_CNTL, tmp);
444 /* allow CPU access */
445 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
446 }
447
448 for (i = 0; i < rdev->num_crtc; i++) {
449 if (save->crtc_enabled[i]) {
450 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
451 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
452 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
453 /* wait for the next frame */
454 frame_count = radeon_get_vblank_counter(rdev, i);
455 for (j = 0; j < rdev->usec_timeout; j++) {
456 if (radeon_get_vblank_counter(rdev, i) != frame_count)
457 break;
458 udelay(1);
459 }
460 }
461 }
462 /* Unlock vga access */
463 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
464 mdelay(1);
465 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
466 }
467
468 static void rv515_mc_program(struct radeon_device *rdev)
469 {
470 struct rv515_mc_save save;
471
472 /* Stops all mc clients */
473 rv515_mc_stop(rdev, &save);
474
475 /* Wait for mc idle */
476 if (rv515_mc_wait_for_idle(rdev))
477 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
478 /* Write VRAM size in case we are limiting it */
479 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
480 /* Program MC, should be a 32bits limited address space */
481 WREG32_MC(R_000001_MC_FB_LOCATION,
482 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
483 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
484 WREG32(R_000134_HDP_FB_LOCATION,
485 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
486 if (rdev->flags & RADEON_IS_AGP) {
487 WREG32_MC(R_000002_MC_AGP_LOCATION,
488 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
489 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
490 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
491 WREG32_MC(R_000004_MC_AGP_BASE_2,
492 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
493 } else {
494 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
495 WREG32_MC(R_000003_MC_AGP_BASE, 0);
496 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
497 }
498
499 rv515_mc_resume(rdev, &save);
500 }
501
502 void rv515_clock_startup(struct radeon_device *rdev)
503 {
504 if (radeon_dynclks != -1 && radeon_dynclks)
505 radeon_atom_set_clock_gating(rdev, 1);
506 /* We need to force on some of the block */
507 WREG32_PLL(R_00000F_CP_DYN_CNTL,
508 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
509 WREG32_PLL(R_000011_E2_DYN_CNTL,
510 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
511 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
512 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
513 }
514
515 static int rv515_startup(struct radeon_device *rdev)
516 {
517 int r;
518
519 rv515_mc_program(rdev);
520 /* Resume clock */
521 rv515_clock_startup(rdev);
522 /* Initialize GPU configuration (# pipes, ...) */
523 rv515_gpu_init(rdev);
524 /* Initialize GART (initialize after TTM so we can allocate
525 * memory through TTM but finalize after TTM) */
526 if (rdev->flags & RADEON_IS_PCIE) {
527 r = rv370_pcie_gart_enable(rdev);
528 if (r)
529 return r;
530 }
531
532 /* allocate wb buffer */
533 r = radeon_wb_init(rdev);
534 if (r)
535 return r;
536
537 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
538 if (r) {
539 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
540 return r;
541 }
542
543 /* Enable IRQ */
544 if (!rdev->irq.installed) {
545 r = radeon_irq_kms_init(rdev);
546 if (r)
547 return r;
548 }
549
550 rs600_irq_set(rdev);
551 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
552 /* 1M ring buffer */
553 r = r100_cp_init(rdev, 1024 * 1024);
554 if (r) {
555 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
556 return r;
557 }
558
559 r = radeon_ib_pool_init(rdev);
560 if (r) {
561 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
562 return r;
563 }
564
565 return 0;
566 }
567
568 int rv515_resume(struct radeon_device *rdev)
569 {
570 int r;
571
572 /* Make sur GART are not working */
573 if (rdev->flags & RADEON_IS_PCIE)
574 rv370_pcie_gart_disable(rdev);
575 /* Resume clock before doing reset */
576 rv515_clock_startup(rdev);
577 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
578 if (radeon_asic_reset(rdev)) {
579 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
580 RREG32(R_000E40_RBBM_STATUS),
581 RREG32(R_0007C0_CP_STAT));
582 }
583 /* post */
584 atom_asic_init(rdev->mode_info.atom_context);
585 /* Resume clock after posting */
586 rv515_clock_startup(rdev);
587 /* Initialize surface registers */
588 radeon_surface_init(rdev);
589
590 rdev->accel_working = true;
591 r = rv515_startup(rdev);
592 if (r) {
593 rdev->accel_working = false;
594 }
595 return r;
596 }
597
598 int rv515_suspend(struct radeon_device *rdev)
599 {
600 radeon_pm_suspend(rdev);
601 r100_cp_disable(rdev);
602 radeon_wb_disable(rdev);
603 rs600_irq_disable(rdev);
604 if (rdev->flags & RADEON_IS_PCIE)
605 rv370_pcie_gart_disable(rdev);
606 return 0;
607 }
608
609 void rv515_set_safe_registers(struct radeon_device *rdev)
610 {
611 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
612 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
613 }
614
615 void rv515_fini(struct radeon_device *rdev)
616 {
617 radeon_pm_fini(rdev);
618 r100_cp_fini(rdev);
619 radeon_wb_fini(rdev);
620 radeon_ib_pool_fini(rdev);
621 radeon_gem_fini(rdev);
622 rv370_pcie_gart_fini(rdev);
623 radeon_agp_fini(rdev);
624 radeon_irq_kms_fini(rdev);
625 radeon_fence_driver_fini(rdev);
626 radeon_bo_fini(rdev);
627 radeon_atombios_fini(rdev);
628 kfree(rdev->bios);
629 rdev->bios = NULL;
630 }
631
632 int rv515_init(struct radeon_device *rdev)
633 {
634 int r;
635
636 /* Initialize scratch registers */
637 radeon_scratch_init(rdev);
638 /* Initialize surface registers */
639 radeon_surface_init(rdev);
640 /* TODO: disable VGA need to use VGA request */
641 /* restore some register to sane defaults */
642 r100_restore_sanity(rdev);
643 /* BIOS*/
644 if (!radeon_get_bios(rdev)) {
645 if (ASIC_IS_AVIVO(rdev))
646 return -EINVAL;
647 }
648 if (rdev->is_atom_bios) {
649 r = radeon_atombios_init(rdev);
650 if (r)
651 return r;
652 } else {
653 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
654 return -EINVAL;
655 }
656 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
657 if (radeon_asic_reset(rdev)) {
658 dev_warn(rdev->dev,
659 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
660 RREG32(R_000E40_RBBM_STATUS),
661 RREG32(R_0007C0_CP_STAT));
662 }
663 /* check if cards are posted or not */
664 if (radeon_boot_test_post_card(rdev) == false)
665 return -EINVAL;
666 /* Initialize clocks */
667 radeon_get_clock_info(rdev->ddev);
668 /* initialize AGP */
669 if (rdev->flags & RADEON_IS_AGP) {
670 r = radeon_agp_init(rdev);
671 if (r) {
672 radeon_agp_disable(rdev);
673 }
674 }
675 /* initialize memory controller */
676 rv515_mc_init(rdev);
677 rv515_debugfs(rdev);
678 /* Fence driver */
679 r = radeon_fence_driver_init(rdev);
680 if (r)
681 return r;
682 /* Memory manager */
683 r = radeon_bo_init(rdev);
684 if (r)
685 return r;
686 r = rv370_pcie_gart_init(rdev);
687 if (r)
688 return r;
689 rv515_set_safe_registers(rdev);
690
691 /* Initialize power management */
692 radeon_pm_init(rdev);
693
694 rdev->accel_working = true;
695 r = rv515_startup(rdev);
696 if (r) {
697 /* Somethings want wront with the accel init stop accel */
698 dev_err(rdev->dev, "Disabling GPU acceleration\n");
699 r100_cp_fini(rdev);
700 radeon_wb_fini(rdev);
701 radeon_ib_pool_fini(rdev);
702 radeon_irq_kms_fini(rdev);
703 rv370_pcie_gart_fini(rdev);
704 radeon_agp_fini(rdev);
705 rdev->accel_working = false;
706 }
707 return 0;
708 }
709
710 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
711 {
712 int index_reg = 0x6578 + crtc->crtc_offset;
713 int data_reg = 0x657c + crtc->crtc_offset;
714
715 WREG32(0x659C + crtc->crtc_offset, 0x0);
716 WREG32(0x6594 + crtc->crtc_offset, 0x705);
717 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
718 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
719 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
720 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
721 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
722 WREG32(index_reg, 0x0);
723 WREG32(data_reg, 0x841880A8);
724 WREG32(index_reg, 0x1);
725 WREG32(data_reg, 0x84208680);
726 WREG32(index_reg, 0x2);
727 WREG32(data_reg, 0xBFF880B0);
728 WREG32(index_reg, 0x100);
729 WREG32(data_reg, 0x83D88088);
730 WREG32(index_reg, 0x101);
731 WREG32(data_reg, 0x84608680);
732 WREG32(index_reg, 0x102);
733 WREG32(data_reg, 0xBFF080D0);
734 WREG32(index_reg, 0x200);
735 WREG32(data_reg, 0x83988068);
736 WREG32(index_reg, 0x201);
737 WREG32(data_reg, 0x84A08680);
738 WREG32(index_reg, 0x202);
739 WREG32(data_reg, 0xBFF080F8);
740 WREG32(index_reg, 0x300);
741 WREG32(data_reg, 0x83588058);
742 WREG32(index_reg, 0x301);
743 WREG32(data_reg, 0x84E08660);
744 WREG32(index_reg, 0x302);
745 WREG32(data_reg, 0xBFF88120);
746 WREG32(index_reg, 0x400);
747 WREG32(data_reg, 0x83188040);
748 WREG32(index_reg, 0x401);
749 WREG32(data_reg, 0x85008660);
750 WREG32(index_reg, 0x402);
751 WREG32(data_reg, 0xBFF88150);
752 WREG32(index_reg, 0x500);
753 WREG32(data_reg, 0x82D88030);
754 WREG32(index_reg, 0x501);
755 WREG32(data_reg, 0x85408640);
756 WREG32(index_reg, 0x502);
757 WREG32(data_reg, 0xBFF88180);
758 WREG32(index_reg, 0x600);
759 WREG32(data_reg, 0x82A08018);
760 WREG32(index_reg, 0x601);
761 WREG32(data_reg, 0x85808620);
762 WREG32(index_reg, 0x602);
763 WREG32(data_reg, 0xBFF081B8);
764 WREG32(index_reg, 0x700);
765 WREG32(data_reg, 0x82608010);
766 WREG32(index_reg, 0x701);
767 WREG32(data_reg, 0x85A08600);
768 WREG32(index_reg, 0x702);
769 WREG32(data_reg, 0x800081F0);
770 WREG32(index_reg, 0x800);
771 WREG32(data_reg, 0x8228BFF8);
772 WREG32(index_reg, 0x801);
773 WREG32(data_reg, 0x85E085E0);
774 WREG32(index_reg, 0x802);
775 WREG32(data_reg, 0xBFF88228);
776 WREG32(index_reg, 0x10000);
777 WREG32(data_reg, 0x82A8BF00);
778 WREG32(index_reg, 0x10001);
779 WREG32(data_reg, 0x82A08CC0);
780 WREG32(index_reg, 0x10002);
781 WREG32(data_reg, 0x8008BEF8);
782 WREG32(index_reg, 0x10100);
783 WREG32(data_reg, 0x81F0BF28);
784 WREG32(index_reg, 0x10101);
785 WREG32(data_reg, 0x83608CA0);
786 WREG32(index_reg, 0x10102);
787 WREG32(data_reg, 0x8018BED0);
788 WREG32(index_reg, 0x10200);
789 WREG32(data_reg, 0x8148BF38);
790 WREG32(index_reg, 0x10201);
791 WREG32(data_reg, 0x84408C80);
792 WREG32(index_reg, 0x10202);
793 WREG32(data_reg, 0x8008BEB8);
794 WREG32(index_reg, 0x10300);
795 WREG32(data_reg, 0x80B0BF78);
796 WREG32(index_reg, 0x10301);
797 WREG32(data_reg, 0x85008C20);
798 WREG32(index_reg, 0x10302);
799 WREG32(data_reg, 0x8020BEA0);
800 WREG32(index_reg, 0x10400);
801 WREG32(data_reg, 0x8028BF90);
802 WREG32(index_reg, 0x10401);
803 WREG32(data_reg, 0x85E08BC0);
804 WREG32(index_reg, 0x10402);
805 WREG32(data_reg, 0x8018BE90);
806 WREG32(index_reg, 0x10500);
807 WREG32(data_reg, 0xBFB8BFB0);
808 WREG32(index_reg, 0x10501);
809 WREG32(data_reg, 0x86C08B40);
810 WREG32(index_reg, 0x10502);
811 WREG32(data_reg, 0x8010BE90);
812 WREG32(index_reg, 0x10600);
813 WREG32(data_reg, 0xBF58BFC8);
814 WREG32(index_reg, 0x10601);
815 WREG32(data_reg, 0x87A08AA0);
816 WREG32(index_reg, 0x10602);
817 WREG32(data_reg, 0x8010BE98);
818 WREG32(index_reg, 0x10700);
819 WREG32(data_reg, 0xBF10BFF0);
820 WREG32(index_reg, 0x10701);
821 WREG32(data_reg, 0x886089E0);
822 WREG32(index_reg, 0x10702);
823 WREG32(data_reg, 0x8018BEB0);
824 WREG32(index_reg, 0x10800);
825 WREG32(data_reg, 0xBED8BFE8);
826 WREG32(index_reg, 0x10801);
827 WREG32(data_reg, 0x89408940);
828 WREG32(index_reg, 0x10802);
829 WREG32(data_reg, 0xBFE8BED8);
830 WREG32(index_reg, 0x20000);
831 WREG32(data_reg, 0x80008000);
832 WREG32(index_reg, 0x20001);
833 WREG32(data_reg, 0x90008000);
834 WREG32(index_reg, 0x20002);
835 WREG32(data_reg, 0x80008000);
836 WREG32(index_reg, 0x20003);
837 WREG32(data_reg, 0x80008000);
838 WREG32(index_reg, 0x20100);
839 WREG32(data_reg, 0x80108000);
840 WREG32(index_reg, 0x20101);
841 WREG32(data_reg, 0x8FE0BF70);
842 WREG32(index_reg, 0x20102);
843 WREG32(data_reg, 0xBFE880C0);
844 WREG32(index_reg, 0x20103);
845 WREG32(data_reg, 0x80008000);
846 WREG32(index_reg, 0x20200);
847 WREG32(data_reg, 0x8018BFF8);
848 WREG32(index_reg, 0x20201);
849 WREG32(data_reg, 0x8F80BF08);
850 WREG32(index_reg, 0x20202);
851 WREG32(data_reg, 0xBFD081A0);
852 WREG32(index_reg, 0x20203);
853 WREG32(data_reg, 0xBFF88000);
854 WREG32(index_reg, 0x20300);
855 WREG32(data_reg, 0x80188000);
856 WREG32(index_reg, 0x20301);
857 WREG32(data_reg, 0x8EE0BEC0);
858 WREG32(index_reg, 0x20302);
859 WREG32(data_reg, 0xBFB082A0);
860 WREG32(index_reg, 0x20303);
861 WREG32(data_reg, 0x80008000);
862 WREG32(index_reg, 0x20400);
863 WREG32(data_reg, 0x80188000);
864 WREG32(index_reg, 0x20401);
865 WREG32(data_reg, 0x8E00BEA0);
866 WREG32(index_reg, 0x20402);
867 WREG32(data_reg, 0xBF8883C0);
868 WREG32(index_reg, 0x20403);
869 WREG32(data_reg, 0x80008000);
870 WREG32(index_reg, 0x20500);
871 WREG32(data_reg, 0x80188000);
872 WREG32(index_reg, 0x20501);
873 WREG32(data_reg, 0x8D00BE90);
874 WREG32(index_reg, 0x20502);
875 WREG32(data_reg, 0xBF588500);
876 WREG32(index_reg, 0x20503);
877 WREG32(data_reg, 0x80008008);
878 WREG32(index_reg, 0x20600);
879 WREG32(data_reg, 0x80188000);
880 WREG32(index_reg, 0x20601);
881 WREG32(data_reg, 0x8BC0BE98);
882 WREG32(index_reg, 0x20602);
883 WREG32(data_reg, 0xBF308660);
884 WREG32(index_reg, 0x20603);
885 WREG32(data_reg, 0x80008008);
886 WREG32(index_reg, 0x20700);
887 WREG32(data_reg, 0x80108000);
888 WREG32(index_reg, 0x20701);
889 WREG32(data_reg, 0x8A80BEB0);
890 WREG32(index_reg, 0x20702);
891 WREG32(data_reg, 0xBF0087C0);
892 WREG32(index_reg, 0x20703);
893 WREG32(data_reg, 0x80008008);
894 WREG32(index_reg, 0x20800);
895 WREG32(data_reg, 0x80108000);
896 WREG32(index_reg, 0x20801);
897 WREG32(data_reg, 0x8920BED0);
898 WREG32(index_reg, 0x20802);
899 WREG32(data_reg, 0xBED08920);
900 WREG32(index_reg, 0x20803);
901 WREG32(data_reg, 0x80008010);
902 WREG32(index_reg, 0x30000);
903 WREG32(data_reg, 0x90008000);
904 WREG32(index_reg, 0x30001);
905 WREG32(data_reg, 0x80008000);
906 WREG32(index_reg, 0x30100);
907 WREG32(data_reg, 0x8FE0BF90);
908 WREG32(index_reg, 0x30101);
909 WREG32(data_reg, 0xBFF880A0);
910 WREG32(index_reg, 0x30200);
911 WREG32(data_reg, 0x8F60BF40);
912 WREG32(index_reg, 0x30201);
913 WREG32(data_reg, 0xBFE88180);
914 WREG32(index_reg, 0x30300);
915 WREG32(data_reg, 0x8EC0BF00);
916 WREG32(index_reg, 0x30301);
917 WREG32(data_reg, 0xBFC88280);
918 WREG32(index_reg, 0x30400);
919 WREG32(data_reg, 0x8DE0BEE0);
920 WREG32(index_reg, 0x30401);
921 WREG32(data_reg, 0xBFA083A0);
922 WREG32(index_reg, 0x30500);
923 WREG32(data_reg, 0x8CE0BED0);
924 WREG32(index_reg, 0x30501);
925 WREG32(data_reg, 0xBF7884E0);
926 WREG32(index_reg, 0x30600);
927 WREG32(data_reg, 0x8BA0BED8);
928 WREG32(index_reg, 0x30601);
929 WREG32(data_reg, 0xBF508640);
930 WREG32(index_reg, 0x30700);
931 WREG32(data_reg, 0x8A60BEE8);
932 WREG32(index_reg, 0x30701);
933 WREG32(data_reg, 0xBF2087A0);
934 WREG32(index_reg, 0x30800);
935 WREG32(data_reg, 0x8900BF00);
936 WREG32(index_reg, 0x30801);
937 WREG32(data_reg, 0xBF008900);
938 }
939
940 struct rv515_watermark {
941 u32 lb_request_fifo_depth;
942 fixed20_12 num_line_pair;
943 fixed20_12 estimated_width;
944 fixed20_12 worst_case_latency;
945 fixed20_12 consumption_rate;
946 fixed20_12 active_time;
947 fixed20_12 dbpp;
948 fixed20_12 priority_mark_max;
949 fixed20_12 priority_mark;
950 fixed20_12 sclk;
951 };
952
953 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
954 struct radeon_crtc *crtc,
955 struct rv515_watermark *wm,
956 bool low)
957 {
958 struct drm_display_mode *mode = &crtc->base.mode;
959 fixed20_12 a, b, c;
960 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
961 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
962 fixed20_12 sclk;
963 u32 selected_sclk;
964
965 if (!crtc->base.enabled) {
966 /* FIXME: wouldn't it better to set priority mark to maximum */
967 wm->lb_request_fifo_depth = 4;
968 return;
969 }
970
971 /* rv6xx, rv7xx */
972 if ((rdev->family >= CHIP_RV610) &&
973 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
974 selected_sclk = radeon_dpm_get_sclk(rdev, low);
975 else
976 selected_sclk = rdev->pm.current_sclk;
977
978 /* sclk in Mhz */
979 a.full = dfixed_const(100);
980 sclk.full = dfixed_const(selected_sclk);
981 sclk.full = dfixed_div(sclk, a);
982
983 if (crtc->vsc.full > dfixed_const(2))
984 wm->num_line_pair.full = dfixed_const(2);
985 else
986 wm->num_line_pair.full = dfixed_const(1);
987
988 b.full = dfixed_const(mode->crtc_hdisplay);
989 c.full = dfixed_const(256);
990 a.full = dfixed_div(b, c);
991 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
992 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
993 if (a.full < dfixed_const(4)) {
994 wm->lb_request_fifo_depth = 4;
995 } else {
996 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
997 }
998
999 /* Determine consumption rate
1000 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
1001 * vtaps = number of vertical taps,
1002 * vsc = vertical scaling ratio, defined as source/destination
1003 * hsc = horizontal scaling ration, defined as source/destination
1004 */
1005 a.full = dfixed_const(mode->clock);
1006 b.full = dfixed_const(1000);
1007 a.full = dfixed_div(a, b);
1008 pclk.full = dfixed_div(b, a);
1009 if (crtc->rmx_type != RMX_OFF) {
1010 b.full = dfixed_const(2);
1011 if (crtc->vsc.full > b.full)
1012 b.full = crtc->vsc.full;
1013 b.full = dfixed_mul(b, crtc->hsc);
1014 c.full = dfixed_const(2);
1015 b.full = dfixed_div(b, c);
1016 consumption_time.full = dfixed_div(pclk, b);
1017 } else {
1018 consumption_time.full = pclk.full;
1019 }
1020 a.full = dfixed_const(1);
1021 wm->consumption_rate.full = dfixed_div(a, consumption_time);
1022
1023
1024 /* Determine line time
1025 * LineTime = total time for one line of displayhtotal
1026 * LineTime = total number of horizontal pixels
1027 * pclk = pixel clock period(ns)
1028 */
1029 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1030 line_time.full = dfixed_mul(a, pclk);
1031
1032 /* Determine active time
1033 * ActiveTime = time of active region of display within one line,
1034 * hactive = total number of horizontal active pixels
1035 * htotal = total number of horizontal pixels
1036 */
1037 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1038 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1039 wm->active_time.full = dfixed_mul(line_time, b);
1040 wm->active_time.full = dfixed_div(wm->active_time, a);
1041
1042 /* Determine chunk time
1043 * ChunkTime = the time it takes the DCP to send one chunk of data
1044 * to the LB which consists of pipeline delay and inter chunk gap
1045 * sclk = system clock(Mhz)
1046 */
1047 a.full = dfixed_const(600 * 1000);
1048 chunk_time.full = dfixed_div(a, sclk);
1049 read_delay_latency.full = dfixed_const(1000);
1050
1051 /* Determine the worst case latency
1052 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1053 * WorstCaseLatency = worst case time from urgent to when the MC starts
1054 * to return data
1055 * READ_DELAY_IDLE_MAX = constant of 1us
1056 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1057 * which consists of pipeline delay and inter chunk gap
1058 */
1059 if (dfixed_trunc(wm->num_line_pair) > 1) {
1060 a.full = dfixed_const(3);
1061 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
1062 wm->worst_case_latency.full += read_delay_latency.full;
1063 } else {
1064 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1065 }
1066
1067 /* Determine the tolerable latency
1068 * TolerableLatency = Any given request has only 1 line time
1069 * for the data to be returned
1070 * LBRequestFifoDepth = Number of chunk requests the LB can
1071 * put into the request FIFO for a display
1072 * LineTime = total time for one line of display
1073 * ChunkTime = the time it takes the DCP to send one chunk
1074 * of data to the LB which consists of
1075 * pipeline delay and inter chunk gap
1076 */
1077 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
1078 tolerable_latency.full = line_time.full;
1079 } else {
1080 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
1081 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1082 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
1083 tolerable_latency.full = line_time.full - tolerable_latency.full;
1084 }
1085 /* We assume worst case 32bits (4 bytes) */
1086 wm->dbpp.full = dfixed_const(2 * 16);
1087
1088 /* Determine the maximum priority mark
1089 * width = viewport width in pixels
1090 */
1091 a.full = dfixed_const(16);
1092 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1093 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1094 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1095
1096 /* Determine estimated width */
1097 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1098 estimated_width.full = dfixed_div(estimated_width, consumption_time);
1099 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1100 wm->priority_mark.full = wm->priority_mark_max.full;
1101 } else {
1102 a.full = dfixed_const(16);
1103 wm->priority_mark.full = dfixed_div(estimated_width, a);
1104 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1105 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1106 }
1107 }
1108
1109 static void rv515_compute_mode_priority(struct radeon_device *rdev,
1110 struct rv515_watermark *wm0,
1111 struct rv515_watermark *wm1,
1112 struct drm_display_mode *mode0,
1113 struct drm_display_mode *mode1,
1114 u32 *d1mode_priority_a_cnt,
1115 u32 *d2mode_priority_a_cnt)
1116 {
1117 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1118 fixed20_12 a, b;
1119
1120 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
1121 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
1122
1123 if (mode0 && mode1) {
1124 if (dfixed_trunc(wm0->dbpp) > 64)
1125 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1126 else
1127 a.full = wm0->num_line_pair.full;
1128 if (dfixed_trunc(wm1->dbpp) > 64)
1129 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1130 else
1131 b.full = wm1->num_line_pair.full;
1132 a.full += b.full;
1133 fill_rate.full = dfixed_div(wm0->sclk, a);
1134 if (wm0->consumption_rate.full > fill_rate.full) {
1135 b.full = wm0->consumption_rate.full - fill_rate.full;
1136 b.full = dfixed_mul(b, wm0->active_time);
1137 a.full = dfixed_const(16);
1138 b.full = dfixed_div(b, a);
1139 a.full = dfixed_mul(wm0->worst_case_latency,
1140 wm0->consumption_rate);
1141 priority_mark02.full = a.full + b.full;
1142 } else {
1143 a.full = dfixed_mul(wm0->worst_case_latency,
1144 wm0->consumption_rate);
1145 b.full = dfixed_const(16 * 1000);
1146 priority_mark02.full = dfixed_div(a, b);
1147 }
1148 if (wm1->consumption_rate.full > fill_rate.full) {
1149 b.full = wm1->consumption_rate.full - fill_rate.full;
1150 b.full = dfixed_mul(b, wm1->active_time);
1151 a.full = dfixed_const(16);
1152 b.full = dfixed_div(b, a);
1153 a.full = dfixed_mul(wm1->worst_case_latency,
1154 wm1->consumption_rate);
1155 priority_mark12.full = a.full + b.full;
1156 } else {
1157 a.full = dfixed_mul(wm1->worst_case_latency,
1158 wm1->consumption_rate);
1159 b.full = dfixed_const(16 * 1000);
1160 priority_mark12.full = dfixed_div(a, b);
1161 }
1162 if (wm0->priority_mark.full > priority_mark02.full)
1163 priority_mark02.full = wm0->priority_mark.full;
1164 if (wm0->priority_mark_max.full > priority_mark02.full)
1165 priority_mark02.full = wm0->priority_mark_max.full;
1166 if (wm1->priority_mark.full > priority_mark12.full)
1167 priority_mark12.full = wm1->priority_mark.full;
1168 if (wm1->priority_mark_max.full > priority_mark12.full)
1169 priority_mark12.full = wm1->priority_mark_max.full;
1170 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1171 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1172 if (rdev->disp_priority == 2) {
1173 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1174 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1175 }
1176 } else if (mode0) {
1177 if (dfixed_trunc(wm0->dbpp) > 64)
1178 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1179 else
1180 a.full = wm0->num_line_pair.full;
1181 fill_rate.full = dfixed_div(wm0->sclk, a);
1182 if (wm0->consumption_rate.full > fill_rate.full) {
1183 b.full = wm0->consumption_rate.full - fill_rate.full;
1184 b.full = dfixed_mul(b, wm0->active_time);
1185 a.full = dfixed_const(16);
1186 b.full = dfixed_div(b, a);
1187 a.full = dfixed_mul(wm0->worst_case_latency,
1188 wm0->consumption_rate);
1189 priority_mark02.full = a.full + b.full;
1190 } else {
1191 a.full = dfixed_mul(wm0->worst_case_latency,
1192 wm0->consumption_rate);
1193 b.full = dfixed_const(16);
1194 priority_mark02.full = dfixed_div(a, b);
1195 }
1196 if (wm0->priority_mark.full > priority_mark02.full)
1197 priority_mark02.full = wm0->priority_mark.full;
1198 if (wm0->priority_mark_max.full > priority_mark02.full)
1199 priority_mark02.full = wm0->priority_mark_max.full;
1200 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1201 if (rdev->disp_priority == 2)
1202 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1203 } else if (mode1) {
1204 if (dfixed_trunc(wm1->dbpp) > 64)
1205 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1206 else
1207 a.full = wm1->num_line_pair.full;
1208 fill_rate.full = dfixed_div(wm1->sclk, a);
1209 if (wm1->consumption_rate.full > fill_rate.full) {
1210 b.full = wm1->consumption_rate.full - fill_rate.full;
1211 b.full = dfixed_mul(b, wm1->active_time);
1212 a.full = dfixed_const(16);
1213 b.full = dfixed_div(b, a);
1214 a.full = dfixed_mul(wm1->worst_case_latency,
1215 wm1->consumption_rate);
1216 priority_mark12.full = a.full + b.full;
1217 } else {
1218 a.full = dfixed_mul(wm1->worst_case_latency,
1219 wm1->consumption_rate);
1220 b.full = dfixed_const(16 * 1000);
1221 priority_mark12.full = dfixed_div(a, b);
1222 }
1223 if (wm1->priority_mark.full > priority_mark12.full)
1224 priority_mark12.full = wm1->priority_mark.full;
1225 if (wm1->priority_mark_max.full > priority_mark12.full)
1226 priority_mark12.full = wm1->priority_mark_max.full;
1227 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1228 if (rdev->disp_priority == 2)
1229 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1230 }
1231 }
1232
1233 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1234 {
1235 struct drm_display_mode *mode0 = NULL;
1236 struct drm_display_mode *mode1 = NULL;
1237 struct rv515_watermark wm0_high, wm0_low;
1238 struct rv515_watermark wm1_high, wm1_low;
1239 u32 tmp;
1240 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
1241 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
1242
1243 if (rdev->mode_info.crtcs[0]->base.enabled)
1244 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1245 if (rdev->mode_info.crtcs[1]->base.enabled)
1246 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1247 rs690_line_buffer_adjust(rdev, mode0, mode1);
1248
1249 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
1250 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
1251
1252 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
1253 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
1254
1255 tmp = wm0_high.lb_request_fifo_depth;
1256 tmp |= wm1_high.lb_request_fifo_depth << 16;
1257 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1258
1259 rv515_compute_mode_priority(rdev,
1260 &wm0_high, &wm1_high,
1261 mode0, mode1,
1262 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
1263 rv515_compute_mode_priority(rdev,
1264 &wm0_low, &wm1_low,
1265 mode0, mode1,
1266 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
1267
1268 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1269 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
1270 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1271 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
1272 }
1273
1274 void rv515_bandwidth_update(struct radeon_device *rdev)
1275 {
1276 uint32_t tmp;
1277 struct drm_display_mode *mode0 = NULL;
1278 struct drm_display_mode *mode1 = NULL;
1279
1280 if (!rdev->mode_info.mode_config_initialized)
1281 return;
1282
1283 radeon_update_display_priority(rdev);
1284
1285 if (rdev->mode_info.crtcs[0]->base.enabled)
1286 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1287 if (rdev->mode_info.crtcs[1]->base.enabled)
1288 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1289 /*
1290 * Set display0/1 priority up in the memory controller for
1291 * modes if the user specifies HIGH for displaypriority
1292 * option.
1293 */
1294 if ((rdev->disp_priority == 2) &&
1295 (rdev->family == CHIP_RV515)) {
1296 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1297 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1298 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1299 if (mode1)
1300 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1301 if (mode0)
1302 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1303 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1304 }
1305 rv515_bandwidth_avivo_update(rdev);
1306 }
Linux with added FPC-III support