acpiphp: Execute ACPI _REG method for hotadded devices
[linux/fpc-iii.git] / arch / arm / mm / fault-armv.c
blob56ee15321b005f0ae9a6cc62dfaaa5bd8ad5cf73
1 /*
2 * linux/arch/arm/mm/fault-armv.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2002 Russell King
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/mm.h>
15 #include <linux/bitops.h>
16 #include <linux/vmalloc.h>
17 #include <linux/init.h>
18 #include <linux/pagemap.h>
20 #include <asm/bugs.h>
21 #include <asm/cacheflush.h>
22 #include <asm/cachetype.h>
23 #include <asm/pgtable.h>
24 #include <asm/tlbflush.h>
26 #include "mm.h"
28 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
31 * We take the easy way out of this problem - we make the
32 * PTE uncacheable. However, we leave the write buffer on.
34 * Note that the pte lock held when calling update_mmu_cache must also
35 * guard the pte (somewhere else in the same mm) that we modify here.
36 * Therefore those configurations which might call adjust_pte (those
37 * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
39 static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
41 pgd_t *pgd;
42 pmd_t *pmd;
43 pte_t *pte, entry;
44 int ret;
46 pgd = pgd_offset(vma->vm_mm, address);
47 if (pgd_none(*pgd))
48 goto no_pgd;
49 if (pgd_bad(*pgd))
50 goto bad_pgd;
52 pmd = pmd_offset(pgd, address);
53 if (pmd_none(*pmd))
54 goto no_pmd;
55 if (pmd_bad(*pmd))
56 goto bad_pmd;
58 pte = pte_offset_map(pmd, address);
59 entry = *pte;
62 * If this page is present, it's actually being shared.
64 ret = pte_present(entry);
67 * If this page isn't present, or is already setup to
68 * fault (ie, is old), we can safely ignore any issues.
70 if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
71 unsigned long pfn = pte_pfn(entry);
72 flush_cache_page(vma, address, pfn);
73 outer_flush_range((pfn << PAGE_SHIFT),
74 (pfn << PAGE_SHIFT) + PAGE_SIZE);
75 pte_val(entry) &= ~L_PTE_MT_MASK;
76 pte_val(entry) |= shared_pte_mask;
77 set_pte_at(vma->vm_mm, address, pte, entry);
78 flush_tlb_page(vma, address);
80 pte_unmap(pte);
81 return ret;
83 bad_pgd:
84 pgd_ERROR(*pgd);
85 pgd_clear(pgd);
86 no_pgd:
87 return 0;
89 bad_pmd:
90 pmd_ERROR(*pmd);
91 pmd_clear(pmd);
92 no_pmd:
93 return 0;
96 static void
97 make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
99 struct mm_struct *mm = vma->vm_mm;
100 struct vm_area_struct *mpnt;
101 struct prio_tree_iter iter;
102 unsigned long offset;
103 pgoff_t pgoff;
104 int aliases = 0;
106 pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
109 * If we have any shared mappings that are in the same mm
110 * space, then we need to handle them specially to maintain
111 * cache coherency.
113 flush_dcache_mmap_lock(mapping);
114 vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
116 * If this VMA is not in our MM, we can ignore it.
117 * Note that we intentionally mask out the VMA
118 * that we are fixing up.
120 if (mpnt->vm_mm != mm || mpnt == vma)
121 continue;
122 if (!(mpnt->vm_flags & VM_MAYSHARE))
123 continue;
124 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
125 aliases += adjust_pte(mpnt, mpnt->vm_start + offset);
127 flush_dcache_mmap_unlock(mapping);
128 if (aliases)
129 adjust_pte(vma, addr);
130 else
131 flush_cache_page(vma, addr, pfn);
135 * Take care of architecture specific things when placing a new PTE into
136 * a page table, or changing an existing PTE. Basically, there are two
137 * things that we need to take care of:
139 * 1. If PG_dcache_dirty is set for the page, we need to ensure
140 * that any cache entries for the kernels virtual memory
141 * range are written back to the page.
142 * 2. If we have multiple shared mappings of the same space in
143 * an object, we need to deal with the cache aliasing issues.
145 * Note that the pte lock will be held.
147 void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
149 unsigned long pfn = pte_pfn(pte);
150 struct address_space *mapping;
151 struct page *page;
153 if (!pfn_valid(pfn))
154 return;
157 * The zero page is never written to, so never has any dirty
158 * cache lines, and therefore never needs to be flushed.
160 page = pfn_to_page(pfn);
161 if (page == ZERO_PAGE(0))
162 return;
164 mapping = page_mapping(page);
165 #ifndef CONFIG_SMP
166 if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
167 __flush_dcache_page(mapping, page);
168 #endif
169 if (mapping) {
170 if (cache_is_vivt())
171 make_coherent(mapping, vma, addr, pfn);
172 else if (vma->vm_flags & VM_EXEC)
173 __flush_icache_all();
178 * Check whether the write buffer has physical address aliasing
179 * issues. If it has, we need to avoid them for the case where
180 * we have several shared mappings of the same object in user
181 * space.
183 static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
185 register unsigned long zero = 0, one = 1, val;
187 local_irq_disable();
188 mb();
189 *p1 = one;
190 mb();
191 *p2 = zero;
192 mb();
193 val = *p1;
194 mb();
195 local_irq_enable();
196 return val != zero;
199 void __init check_writebuffer_bugs(void)
201 struct page *page;
202 const char *reason;
203 unsigned long v = 1;
205 printk(KERN_INFO "CPU: Testing write buffer coherency: ");
207 page = alloc_page(GFP_KERNEL);
208 if (page) {
209 unsigned long *p1, *p2;
210 pgprot_t prot = __pgprot_modify(PAGE_KERNEL,
211 L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE);
213 p1 = vmap(&page, 1, VM_IOREMAP, prot);
214 p2 = vmap(&page, 1, VM_IOREMAP, prot);
216 if (p1 && p2) {
217 v = check_writebuffer(p1, p2);
218 reason = "enabling work-around";
219 } else {
220 reason = "unable to map memory\n";
223 vunmap(p1);
224 vunmap(p2);
225 put_page(page);
226 } else {
227 reason = "unable to grab page\n";
230 if (v) {
231 printk("failed, %s\n", reason);
232 shared_pte_mask = L_PTE_MT_UNCACHED;
233 } else {
234 printk("ok\n");