| blob | 41fe25d234f50b76b563c6b5516a258d45c014fe |
1 /*
2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e.
25 *
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 */
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/hwcap.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
37 #include "proc-macros.S"
39 /*
40 * This is the maximum size of an area which will be invalidated
41 * using the single invalidate entry instructions. Anything larger
42 * than this, and we go for the whole cache.
43 *
44 * This value should be chosen such that we choose the cheapest
45 * alternative.
46 */
47 #define MAX_AREA_SIZE 32768
49 /*
50 * The size of one data cache line.
51 */
52 #define CACHE_DLINESIZE 32
54 /*
55 * The number of data cache segments.
56 */
57 #define CACHE_DSEGMENTS 16
59 /*
60 * The number of lines in a cache segment.
61 */
62 #define CACHE_DENTRIES 64
64 /*
65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual
67 * cache line maintainence instructions.
68 */
69 #define CACHE_DLIMIT 32768
71 .text
72 /*
73 * cpu_arm1020e_proc_init()
74 */
75 ENTRY(cpu_arm1020e_proc_init)
76 mov pc, lr
78 /*
79 * cpu_arm1020e_proc_fin()
80 */
81 ENTRY(cpu_arm1020e_proc_fin)
82 stmfd sp!, {lr}
83 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
84 msr cpsr_c, ip
85 bl arm1020e_flush_kern_cache_all
86 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
87 bic r0, r0, #0x1000 @ ...i............
88 bic r0, r0, #0x000e @ ............wca.
89 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 ldmfd sp!, {pc}
92 /*
93 * cpu_arm1020e_reset(loc)
94 *
95 * Perform a soft reset of the system. Put the CPU into the
96 * same state as it would be if it had been reset, and branch
97 * to what would be the reset vector.
98 *
99 * loc: location to jump to for soft reset
100 */
101 .align 5
102 ENTRY(cpu_arm1020e_reset)
103 mov ip, #0
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
105 mcr p15, 0, ip, c7, c10, 4 @ drain WB
106 #ifdef CONFIG_MMU
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 #endif
109 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
110 bic ip, ip, #0x000f @ ............wcam
111 bic ip, ip, #0x1100 @ ...i...s........
112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
113 mov pc, r0
115 /*
116 * cpu_arm1020e_do_idle()
117 */
118 .align 5
119 ENTRY(cpu_arm1020e_do_idle)
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
121 mov pc, lr
123 /* ================================= CACHE ================================ */
125 .align 5
126 /*
127 * flush_user_cache_all()
128 *
129 * Invalidate all cache entries in a particular address
130 * space.
131 */
132 ENTRY(arm1020e_flush_user_cache_all)
133 /* FALLTHROUGH */
134 /*
135 * flush_kern_cache_all()
136 *
137 * Clean and invalidate the entire cache.
138 */
139 ENTRY(arm1020e_flush_kern_cache_all)
140 mov r2, #VM_EXEC
141 mov ip, #0
142 __flush_whole_cache:
143 #ifndef CONFIG_CPU_DCACHE_DISABLE
144 mcr p15, 0, ip, c7, c10, 4 @ drain WB
145 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
146 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
148 subs r3, r3, #1 << 26
149 bcs 2b @ entries 63 to 0
150 subs r1, r1, #1 << 5
151 bcs 1b @ segments 15 to 0
152 #endif
153 tst r2, #VM_EXEC
154 #ifndef CONFIG_CPU_ICACHE_DISABLE
155 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
156 #endif
157 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
158 mov pc, lr
160 /*
161 * flush_user_cache_range(start, end, flags)
162 *
163 * Invalidate a range of cache entries in the specified
164 * address space.
165 *
166 * - start - start address (inclusive)
167 * - end - end address (exclusive)
168 * - flags - vm_flags for this space
169 */
170 ENTRY(arm1020e_flush_user_cache_range)
171 mov ip, #0
172 sub r3, r1, r0 @ calculate total size
173 cmp r3, #CACHE_DLIMIT
174 bhs __flush_whole_cache
176 #ifndef CONFIG_CPU_DCACHE_DISABLE
177 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
178 add r0, r0, #CACHE_DLINESIZE
179 cmp r0, r1
180 blo 1b
181 #endif
182 tst r2, #VM_EXEC
183 #ifndef CONFIG_CPU_ICACHE_DISABLE
184 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
185 #endif
186 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
187 mov pc, lr
189 /*
190 * coherent_kern_range(start, end)
191 *
192 * Ensure coherency between the Icache and the Dcache in the
193 * region described by start. If you have non-snooping
194 * Harvard caches, you need to implement this function.
195 *
196 * - start - virtual start address
197 * - end - virtual end address
198 */
199 ENTRY(arm1020e_coherent_kern_range)
200 /* FALLTHROUGH */
201 /*
202 * coherent_user_range(start, end)
203 *
204 * Ensure coherency between the Icache and the Dcache in the
205 * region described by start. If you have non-snooping
206 * Harvard caches, you need to implement this function.
207 *
208 * - start - virtual start address
209 * - end - virtual end address
210 */
211 ENTRY(arm1020e_coherent_user_range)
212 mov ip, #0
213 bic r0, r0, #CACHE_DLINESIZE - 1
214 1:
215 #ifndef CONFIG_CPU_DCACHE_DISABLE
216 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
217 #endif
218 #ifndef CONFIG_CPU_ICACHE_DISABLE
219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220 #endif
221 add r0, r0, #CACHE_DLINESIZE
222 cmp r0, r1
223 blo 1b
224 mcr p15, 0, ip, c7, c10, 4 @ drain WB
225 mov pc, lr
227 /*
228 * flush_kern_dcache_area(void *addr, size_t size)
229 *
230 * Ensure no D cache aliasing occurs, either with itself or
231 * the I cache
232 *
233 * - addr - kernel address
234 * - size - region size
235 */
236 ENTRY(arm1020e_flush_kern_dcache_area)
237 mov ip, #0
238 #ifndef CONFIG_CPU_DCACHE_DISABLE
239 add r1, r0, r1
240 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
241 add r0, r0, #CACHE_DLINESIZE
242 cmp r0, r1
243 blo 1b
244 #endif
245 mcr p15, 0, ip, c7, c10, 4 @ drain WB
246 mov pc, lr
248 /*
249 * dma_inv_range(start, end)
250 *
251 * Invalidate (discard) the specified virtual address range.
252 * May not write back any entries. If 'start' or 'end'
253 * are not cache line aligned, those lines must be written
254 * back.
255 *
256 * - start - virtual start address
257 * - end - virtual end address
258 *
259 * (same as v4wb)
260 */
261 ENTRY(arm1020e_dma_inv_range)
262 mov ip, #0
263 #ifndef CONFIG_CPU_DCACHE_DISABLE
264 tst r0, #CACHE_DLINESIZE - 1
265 bic r0, r0, #CACHE_DLINESIZE - 1
266 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
267 tst r1, #CACHE_DLINESIZE - 1
268 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
269 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
270 add r0, r0, #CACHE_DLINESIZE
271 cmp r0, r1
272 blo 1b
273 #endif
274 mcr p15, 0, ip, c7, c10, 4 @ drain WB
275 mov pc, lr
277 /*
278 * dma_clean_range(start, end)
279 *
280 * Clean the specified virtual address range.
281 *
282 * - start - virtual start address
283 * - end - virtual end address
284 *
285 * (same as v4wb)
286 */
287 ENTRY(arm1020e_dma_clean_range)
288 mov ip, #0
289 #ifndef CONFIG_CPU_DCACHE_DISABLE
290 bic r0, r0, #CACHE_DLINESIZE - 1
291 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
292 add r0, r0, #CACHE_DLINESIZE
293 cmp r0, r1
294 blo 1b
295 #endif
296 mcr p15, 0, ip, c7, c10, 4 @ drain WB
297 mov pc, lr
299 /*
300 * dma_flush_range(start, end)
301 *
302 * Clean and invalidate the specified virtual address range.
303 *
304 * - start - virtual start address
305 * - end - virtual end address
306 */
307 ENTRY(arm1020e_dma_flush_range)
308 mov ip, #0
309 #ifndef CONFIG_CPU_DCACHE_DISABLE
310 bic r0, r0, #CACHE_DLINESIZE - 1
311 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
312 add r0, r0, #CACHE_DLINESIZE
313 cmp r0, r1
314 blo 1b
315 #endif
316 mcr p15, 0, ip, c7, c10, 4 @ drain WB
317 mov pc, lr
319 ENTRY(arm1020e_cache_fns)
320 .long arm1020e_flush_kern_cache_all
321 .long arm1020e_flush_user_cache_all
322 .long arm1020e_flush_user_cache_range
323 .long arm1020e_coherent_kern_range
324 .long arm1020e_coherent_user_range
325 .long arm1020e_flush_kern_dcache_area
326 .long arm1020e_dma_inv_range
327 .long arm1020e_dma_clean_range
328 .long arm1020e_dma_flush_range
330 .align 5
331 ENTRY(cpu_arm1020e_dcache_clean_area)
332 #ifndef CONFIG_CPU_DCACHE_DISABLE
333 mov ip, #0
334 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
335 add r0, r0, #CACHE_DLINESIZE
336 subs r1, r1, #CACHE_DLINESIZE
337 bhi 1b
338 #endif
339 mov pc, lr
341 /* =============================== PageTable ============================== */
343 /*
344 * cpu_arm1020e_switch_mm(pgd)
345 *
346 * Set the translation base pointer to be as described by pgd.
347 *
348 * pgd: new page tables
349 */
350 .align 5
351 ENTRY(cpu_arm1020e_switch_mm)
352 #ifdef CONFIG_MMU
353 #ifndef CONFIG_CPU_DCACHE_DISABLE
354 mcr p15, 0, r3, c7, c10, 4
355 mov r1, #0xF @ 16 segments
356 1: mov r3, #0x3F @ 64 entries
357 2: mov ip, r3, LSL #26 @ shift up entry
358 orr ip, ip, r1, LSL #5 @ shift in/up index
359 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
360 mov ip, #0
361 subs r3, r3, #1
362 cmp r3, #0
363 bge 2b @ entries 3F to 0
364 subs r1, r1, #1
365 cmp r1, #0
366 bge 1b @ segments 15 to 0
368 #endif
369 mov r1, #0
370 #ifndef CONFIG_CPU_ICACHE_DISABLE
371 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
372 #endif
373 mcr p15, 0, r1, c7, c10, 4 @ drain WB
374 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
375 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
376 #endif
377 mov pc, lr
379 /*
380 * cpu_arm1020e_set_pte(ptep, pte)
381 *
382 * Set a PTE and flush it out
383 */
384 .align 5
385 ENTRY(cpu_arm1020e_set_pte_ext)
386 #ifdef CONFIG_MMU
387 armv3_set_pte_ext
388 mov r0, r0
389 #ifndef CONFIG_CPU_DCACHE_DISABLE
390 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
391 #endif
392 #endif /* CONFIG_MMU */
393 mov pc, lr
395 __INIT
397 .type __arm1020e_setup, #function
398 __arm1020e_setup:
399 mov r0, #0
400 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
401 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
402 #ifdef CONFIG_MMU
403 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
404 #endif
405 adr r5, arm1020e_crval
406 ldmia r5, {r5, r6}
407 mrc p15, 0, r0, c1, c0 @ get control register v4
408 bic r0, r0, r5
409 orr r0, r0, r6
410 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
411 orr r0, r0, #0x4000 @ .R.. .... .... ....
412 #endif
413 mov pc, lr
414 .size __arm1020e_setup, . - __arm1020e_setup
416 /*
417 * R
418 * .RVI ZFRS BLDP WCAM
419 * .011 1001 ..11 0101
420 */
421 .type arm1020e_crval, #object
422 arm1020e_crval:
423 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
425 __INITDATA
427 /*
428 * Purpose : Function pointers used to access above functions - all calls
429 * come through these
430 */
431 .type arm1020e_processor_functions, #object
432 arm1020e_processor_functions:
433 .word v4t_early_abort
434 .word legacy_pabort
435 .word cpu_arm1020e_proc_init
436 .word cpu_arm1020e_proc_fin
437 .word cpu_arm1020e_reset
438 .word cpu_arm1020e_do_idle
439 .word cpu_arm1020e_dcache_clean_area
440 .word cpu_arm1020e_switch_mm
441 .word cpu_arm1020e_set_pte_ext
442 .size arm1020e_processor_functions, . - arm1020e_processor_functions
444 .section ".rodata"
446 .type cpu_arch_name, #object
447 cpu_arch_name:
448 .asciz "armv5te"
449 .size cpu_arch_name, . - cpu_arch_name
451 .type cpu_elf_name, #object
452 cpu_elf_name:
453 .asciz "v5"
454 .size cpu_elf_name, . - cpu_elf_name
456 .type cpu_arm1020e_name, #object
457 cpu_arm1020e_name:
458 .asciz "ARM1020E"
459 .size cpu_arm1020e_name, . - cpu_arm1020e_name
461 .align
463 .section ".proc.info.init", #alloc, #execinstr
465 .type __arm1020e_proc_info,#object
466 __arm1020e_proc_info:
467 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
468 .long 0xff0ffff0
469 .long PMD_TYPE_SECT | \
470 PMD_BIT4 | \
471 PMD_SECT_AP_WRITE | \
472 PMD_SECT_AP_READ
473 .long PMD_TYPE_SECT | \
474 PMD_BIT4 | \
475 PMD_SECT_AP_WRITE | \
476 PMD_SECT_AP_READ
477 b __arm1020e_setup
478 .long cpu_arch_name
479 .long cpu_elf_name
480 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
481 .long cpu_arm1020e_name
482 .long arm1020e_processor_functions
483 .long v4wbi_tlb_fns
484 .long v4wb_user_fns
485 .long arm1020e_cache_fns
486 .size __arm1020e_proc_info, . - __arm1020e_proc_info