| blob | 471669e2d7cb458567d9233a805dd8ce772bf719 |
1 /*
2 * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
3 *
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm920.
25 *
26 * CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
27 */
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/hwcap.h>
32 #include <asm/pgtable-hwdef.h>
33 #include <asm/pgtable.h>
34 #include <asm/page.h>
35 #include <asm/ptrace.h>
36 #include "proc-macros.S"
38 /*
39 * The size of one data cache line.
40 */
41 #define CACHE_DLINESIZE 32
43 /*
44 * The number of data cache segments.
45 */
46 #define CACHE_DSEGMENTS 8
48 /*
49 * The number of lines in a cache segment.
50 */
51 #define CACHE_DENTRIES 64
53 /*
54 * This is the size at which it becomes more efficient to
55 * clean the whole cache, rather than using the individual
56 * cache line maintainence instructions.
57 */
58 #define CACHE_DLIMIT 65536
61 .text
62 /*
63 * cpu_arm920_proc_init()
64 */
65 ENTRY(cpu_arm920_proc_init)
66 mov pc, lr
68 /*
69 * cpu_arm920_proc_fin()
70 */
71 ENTRY(cpu_arm920_proc_fin)
72 stmfd sp!, {lr}
73 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
74 msr cpsr_c, ip
75 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
76 bl arm920_flush_kern_cache_all
77 #else
78 bl v4wt_flush_kern_cache_all
79 #endif
80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0, #0x1000 @ ...i............
82 bic r0, r0, #0x000e @ ............wca.
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
84 ldmfd sp!, {pc}
86 /*
87 * cpu_arm920_reset(loc)
88 *
89 * Perform a soft reset of the system. Put the CPU into the
90 * same state as it would be if it had been reset, and branch
91 * to what would be the reset vector.
92 *
93 * loc: location to jump to for soft reset
94 */
95 .align 5
96 ENTRY(cpu_arm920_reset)
97 mov ip, #0
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB
100 #ifdef CONFIG_MMU
101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
102 #endif
103 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
104 bic ip, ip, #0x000f @ ............wcam
105 bic ip, ip, #0x1100 @ ...i...s........
106 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
107 mov pc, r0
109 /*
110 * cpu_arm920_do_idle()
111 */
112 .align 5
113 ENTRY(cpu_arm920_do_idle)
114 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
115 mov pc, lr
118 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
120 /*
121 * flush_user_cache_all()
122 *
123 * Invalidate all cache entries in a particular address
124 * space.
125 */
126 ENTRY(arm920_flush_user_cache_all)
127 /* FALLTHROUGH */
129 /*
130 * flush_kern_cache_all()
131 *
132 * Clean and invalidate the entire cache.
133 */
134 ENTRY(arm920_flush_kern_cache_all)
135 mov r2, #VM_EXEC
136 mov ip, #0
137 __flush_whole_cache:
138 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
139 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
140 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
141 subs r3, r3, #1 << 26
142 bcs 2b @ entries 63 to 0
143 subs r1, r1, #1 << 5
144 bcs 1b @ segments 7 to 0
145 tst r2, #VM_EXEC
146 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
147 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
148 mov pc, lr
150 /*
151 * flush_user_cache_range(start, end, flags)
152 *
153 * Invalidate a range of cache entries in the specified
154 * address space.
155 *
156 * - start - start address (inclusive)
157 * - end - end address (exclusive)
158 * - flags - vm_flags for address space
159 */
160 ENTRY(arm920_flush_user_cache_range)
161 mov ip, #0
162 sub r3, r1, r0 @ calculate total size
163 cmp r3, #CACHE_DLIMIT
164 bhs __flush_whole_cache
166 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
167 tst r2, #VM_EXEC
168 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
169 add r0, r0, #CACHE_DLINESIZE
170 cmp r0, r1
171 blo 1b
172 tst r2, #VM_EXEC
173 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
174 mov pc, lr
176 /*
177 * coherent_kern_range(start, end)
178 *
179 * Ensure coherency between the Icache and the Dcache in the
180 * region described by start, end. If you have non-snooping
181 * Harvard caches, you need to implement this function.
182 *
183 * - start - virtual start address
184 * - end - virtual end address
185 */
186 ENTRY(arm920_coherent_kern_range)
187 /* FALLTHROUGH */
189 /*
190 * coherent_user_range(start, end)
191 *
192 * Ensure coherency between the Icache and the Dcache in the
193 * region described by start, end. If you have non-snooping
194 * Harvard caches, you need to implement this function.
195 *
196 * - start - virtual start address
197 * - end - virtual end address
198 */
199 ENTRY(arm920_coherent_user_range)
200 bic r0, r0, #CACHE_DLINESIZE - 1
201 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
202 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
203 add r0, r0, #CACHE_DLINESIZE
204 cmp r0, r1
205 blo 1b
206 mcr p15, 0, r0, c7, c10, 4 @ drain WB
207 mov pc, lr
209 /*
210 * flush_kern_dcache_area(void *addr, size_t size)
211 *
212 * Ensure no D cache aliasing occurs, either with itself or
213 * the I cache
214 *
215 * - addr - kernel address
216 * - size - region size
217 */
218 ENTRY(arm920_flush_kern_dcache_area)
219 add r1, r0, r1
220 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
221 add r0, r0, #CACHE_DLINESIZE
222 cmp r0, r1
223 blo 1b
224 mov r0, #0
225 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
226 mcr p15, 0, r0, c7, c10, 4 @ drain WB
227 mov pc, lr
229 /*
230 * dma_inv_range(start, end)
231 *
232 * Invalidate (discard) the specified virtual address range.
233 * May not write back any entries. If 'start' or 'end'
234 * are not cache line aligned, those lines must be written
235 * back.
236 *
237 * - start - virtual start address
238 * - end - virtual end address
239 *
240 * (same as v4wb)
241 */
242 ENTRY(arm920_dma_inv_range)
243 tst r0, #CACHE_DLINESIZE - 1
244 bic r0, r0, #CACHE_DLINESIZE - 1
245 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
246 tst r1, #CACHE_DLINESIZE - 1
247 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
248 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
249 add r0, r0, #CACHE_DLINESIZE
250 cmp r0, r1
251 blo 1b
252 mcr p15, 0, r0, c7, c10, 4 @ drain WB
253 mov pc, lr
255 /*
256 * dma_clean_range(start, end)
257 *
258 * Clean the specified virtual address range.
259 *
260 * - start - virtual start address
261 * - end - virtual end address
262 *
263 * (same as v4wb)
264 */
265 ENTRY(arm920_dma_clean_range)
266 bic r0, r0, #CACHE_DLINESIZE - 1
267 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
268 add r0, r0, #CACHE_DLINESIZE
269 cmp r0, r1
270 blo 1b
271 mcr p15, 0, r0, c7, c10, 4 @ drain WB
272 mov pc, lr
274 /*
275 * dma_flush_range(start, end)
276 *
277 * Clean and invalidate the specified virtual address range.
278 *
279 * - start - virtual start address
280 * - end - virtual end address
281 */
282 ENTRY(arm920_dma_flush_range)
283 bic r0, r0, #CACHE_DLINESIZE - 1
284 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
285 add r0, r0, #CACHE_DLINESIZE
286 cmp r0, r1
287 blo 1b
288 mcr p15, 0, r0, c7, c10, 4 @ drain WB
289 mov pc, lr
291 ENTRY(arm920_cache_fns)
292 .long arm920_flush_kern_cache_all
293 .long arm920_flush_user_cache_all
294 .long arm920_flush_user_cache_range
295 .long arm920_coherent_kern_range
296 .long arm920_coherent_user_range
297 .long arm920_flush_kern_dcache_area
298 .long arm920_dma_inv_range
299 .long arm920_dma_clean_range
300 .long arm920_dma_flush_range
302 #endif
305 ENTRY(cpu_arm920_dcache_clean_area)
306 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
307 add r0, r0, #CACHE_DLINESIZE
308 subs r1, r1, #CACHE_DLINESIZE
309 bhi 1b
310 mov pc, lr
312 /* =============================== PageTable ============================== */
314 /*
315 * cpu_arm920_switch_mm(pgd)
316 *
317 * Set the translation base pointer to be as described by pgd.
318 *
319 * pgd: new page tables
320 */
321 .align 5
322 ENTRY(cpu_arm920_switch_mm)
323 #ifdef CONFIG_MMU
324 mov ip, #0
325 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
326 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
327 #else
328 @ && 'Clean & Invalidate whole DCache'
329 @ && Re-written to use Index Ops.
330 @ && Uses registers r1, r3 and ip
332 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
333 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
334 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
335 subs r3, r3, #1 << 26
336 bcs 2b @ entries 63 to 0
337 subs r1, r1, #1 << 5
338 bcs 1b @ segments 7 to 0
339 #endif
340 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
341 mcr p15, 0, ip, c7, c10, 4 @ drain WB
342 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
343 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
344 #endif
345 mov pc, lr
347 /*
348 * cpu_arm920_set_pte(ptep, pte, ext)
349 *
350 * Set a PTE and flush it out
351 */
352 .align 5
353 ENTRY(cpu_arm920_set_pte_ext)
354 #ifdef CONFIG_MMU
355 armv3_set_pte_ext
356 mov r0, r0
357 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
358 mcr p15, 0, r0, c7, c10, 4 @ drain WB
359 #endif
360 mov pc, lr
362 __INIT
364 .type __arm920_setup, #function
365 __arm920_setup:
366 mov r0, #0
367 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
368 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
369 #ifdef CONFIG_MMU
370 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
371 #endif
372 adr r5, arm920_crval
373 ldmia r5, {r5, r6}
374 mrc p15, 0, r0, c1, c0 @ get control register v4
375 bic r0, r0, r5
376 orr r0, r0, r6
377 mov pc, lr
378 .size __arm920_setup, . - __arm920_setup
380 /*
381 * R
382 * .RVI ZFRS BLDP WCAM
383 * ..11 0001 ..11 0101
384 *
385 */
386 .type arm920_crval, #object
387 arm920_crval:
388 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
390 __INITDATA
392 /*
393 * Purpose : Function pointers used to access above functions - all calls
394 * come through these
395 */
396 .type arm920_processor_functions, #object
397 arm920_processor_functions:
398 .word v4t_early_abort
399 .word legacy_pabort
400 .word cpu_arm920_proc_init
401 .word cpu_arm920_proc_fin
402 .word cpu_arm920_reset
403 .word cpu_arm920_do_idle
404 .word cpu_arm920_dcache_clean_area
405 .word cpu_arm920_switch_mm
406 .word cpu_arm920_set_pte_ext
407 .size arm920_processor_functions, . - arm920_processor_functions
409 .section ".rodata"
411 .type cpu_arch_name, #object
412 cpu_arch_name:
413 .asciz "armv4t"
414 .size cpu_arch_name, . - cpu_arch_name
416 .type cpu_elf_name, #object
417 cpu_elf_name:
418 .asciz "v4"
419 .size cpu_elf_name, . - cpu_elf_name
421 .type cpu_arm920_name, #object
422 cpu_arm920_name:
423 .asciz "ARM920T"
424 .size cpu_arm920_name, . - cpu_arm920_name
426 .align
428 .section ".proc.info.init", #alloc, #execinstr
430 .type __arm920_proc_info,#object
431 __arm920_proc_info:
432 .long 0x41009200
433 .long 0xff00fff0
434 .long PMD_TYPE_SECT | \
435 PMD_SECT_BUFFERABLE | \
436 PMD_SECT_CACHEABLE | \
437 PMD_BIT4 | \
438 PMD_SECT_AP_WRITE | \
439 PMD_SECT_AP_READ
440 .long PMD_TYPE_SECT | \
441 PMD_BIT4 | \
442 PMD_SECT_AP_WRITE | \
443 PMD_SECT_AP_READ
444 b __arm920_setup
445 .long cpu_arch_name
446 .long cpu_elf_name
447 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
448 .long cpu_arm920_name
449 .long arm920_processor_functions
450 .long v4wbi_tlb_fns
451 .long v4wb_user_fns
452 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
453 .long arm920_cache_fns
454 #else
455 .long v4wt_cache_fns
456 #endif
457 .size __arm920_proc_info, . - __arm920_proc_info