| blob | ee111b00fa41951619593c758fe22eb06a4e4ee4 |
1 /*
2 * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
3 *
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2001 Altera Corporation
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * These are the low level assembler for performing cache and TLB
25 * functions on the arm922.
26 *
27 * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
28 */
29 #include <linux/linkage.h>
30 #include <linux/init.h>
31 #include <asm/assembler.h>
32 #include <asm/hwcap.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
35 #include <asm/page.h>
36 #include <asm/ptrace.h>
37 #include "proc-macros.S"
39 /*
40 * The size of one data cache line.
41 */
42 #define CACHE_DLINESIZE 32
44 /*
45 * The number of data cache segments.
46 */
47 #define CACHE_DSEGMENTS 4
49 /*
50 * The number of lines in a cache segment.
51 */
52 #define CACHE_DENTRIES 64
54 /*
55 * This is the size at which it becomes more efficient to
56 * clean the whole cache, rather than using the individual
57 * cache line maintainence instructions. (I think this should
58 * be 32768).
59 */
60 #define CACHE_DLIMIT 8192
63 .text
64 /*
65 * cpu_arm922_proc_init()
66 */
67 ENTRY(cpu_arm922_proc_init)
68 mov pc, lr
70 /*
71 * cpu_arm922_proc_fin()
72 */
73 ENTRY(cpu_arm922_proc_fin)
74 stmfd sp!, {lr}
75 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
76 msr cpsr_c, ip
77 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
78 bl arm922_flush_kern_cache_all
79 #else
80 bl v4wt_flush_kern_cache_all
81 #endif
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 ldmfd sp!, {pc}
88 /*
89 * cpu_arm922_reset(loc)
90 *
91 * Perform a soft reset of the system. Put the CPU into the
92 * same state as it would be if it had been reset, and branch
93 * to what would be the reset vector.
94 *
95 * loc: location to jump to for soft reset
96 */
97 .align 5
98 ENTRY(cpu_arm922_reset)
99 mov ip, #0
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
102 #ifdef CONFIG_MMU
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
104 #endif
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
109 mov pc, r0
111 /*
112 * cpu_arm922_do_idle()
113 */
114 .align 5
115 ENTRY(cpu_arm922_do_idle)
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
117 mov pc, lr
120 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
122 /*
123 * flush_user_cache_all()
124 *
125 * Clean and invalidate all cache entries in a particular
126 * address space.
127 */
128 ENTRY(arm922_flush_user_cache_all)
129 /* FALLTHROUGH */
131 /*
132 * flush_kern_cache_all()
133 *
134 * Clean and invalidate the entire cache.
135 */
136 ENTRY(arm922_flush_kern_cache_all)
137 mov r2, #VM_EXEC
138 mov ip, #0
139 __flush_whole_cache:
140 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
141 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
142 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
143 subs r3, r3, #1 << 26
144 bcs 2b @ entries 63 to 0
145 subs r1, r1, #1 << 5
146 bcs 1b @ segments 7 to 0
147 tst r2, #VM_EXEC
148 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
149 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
150 mov pc, lr
152 /*
153 * flush_user_cache_range(start, end, flags)
154 *
155 * Clean and invalidate a range of cache entries in the
156 * specified address range.
157 *
158 * - start - start address (inclusive)
159 * - end - end address (exclusive)
160 * - flags - vm_flags describing address space
161 */
162 ENTRY(arm922_flush_user_cache_range)
163 mov ip, #0
164 sub r3, r1, r0 @ calculate total size
165 cmp r3, #CACHE_DLIMIT
166 bhs __flush_whole_cache
168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
169 tst r2, #VM_EXEC
170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
171 add r0, r0, #CACHE_DLINESIZE
172 cmp r0, r1
173 blo 1b
174 tst r2, #VM_EXEC
175 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
176 mov pc, lr
178 /*
179 * coherent_kern_range(start, end)
180 *
181 * Ensure coherency between the Icache and the Dcache in the
182 * region described by start, end. If you have non-snooping
183 * Harvard caches, you need to implement this function.
184 *
185 * - start - virtual start address
186 * - end - virtual end address
187 */
188 ENTRY(arm922_coherent_kern_range)
189 /* FALLTHROUGH */
191 /*
192 * coherent_user_range(start, end)
193 *
194 * Ensure coherency between the Icache and the Dcache in the
195 * region described by start, end. If you have non-snooping
196 * Harvard caches, you need to implement this function.
197 *
198 * - start - virtual start address
199 * - end - virtual end address
200 */
201 ENTRY(arm922_coherent_user_range)
202 bic r0, r0, #CACHE_DLINESIZE - 1
203 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
204 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
205 add r0, r0, #CACHE_DLINESIZE
206 cmp r0, r1
207 blo 1b
208 mcr p15, 0, r0, c7, c10, 4 @ drain WB
209 mov pc, lr
211 /*
212 * flush_kern_dcache_area(void *addr, size_t size)
213 *
214 * Ensure no D cache aliasing occurs, either with itself or
215 * the I cache
216 *
217 * - addr - kernel address
218 * - size - region size
219 */
220 ENTRY(arm922_flush_kern_dcache_area)
221 add r1, r0, r1
222 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
223 add r0, r0, #CACHE_DLINESIZE
224 cmp r0, r1
225 blo 1b
226 mov r0, #0
227 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
228 mcr p15, 0, r0, c7, c10, 4 @ drain WB
229 mov pc, lr
231 /*
232 * dma_inv_range(start, end)
233 *
234 * Invalidate (discard) the specified virtual address range.
235 * May not write back any entries. If 'start' or 'end'
236 * are not cache line aligned, those lines must be written
237 * back.
238 *
239 * - start - virtual start address
240 * - end - virtual end address
241 *
242 * (same as v4wb)
243 */
244 ENTRY(arm922_dma_inv_range)
245 tst r0, #CACHE_DLINESIZE - 1
246 bic r0, r0, #CACHE_DLINESIZE - 1
247 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
248 tst r1, #CACHE_DLINESIZE - 1
249 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
250 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
251 add r0, r0, #CACHE_DLINESIZE
252 cmp r0, r1
253 blo 1b
254 mcr p15, 0, r0, c7, c10, 4 @ drain WB
255 mov pc, lr
257 /*
258 * dma_clean_range(start, end)
259 *
260 * Clean the specified virtual address range.
261 *
262 * - start - virtual start address
263 * - end - virtual end address
264 *
265 * (same as v4wb)
266 */
267 ENTRY(arm922_dma_clean_range)
268 bic r0, r0, #CACHE_DLINESIZE - 1
269 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
270 add r0, r0, #CACHE_DLINESIZE
271 cmp r0, r1
272 blo 1b
273 mcr p15, 0, r0, c7, c10, 4 @ drain WB
274 mov pc, lr
276 /*
277 * dma_flush_range(start, end)
278 *
279 * Clean and invalidate the specified virtual address range.
280 *
281 * - start - virtual start address
282 * - end - virtual end address
283 */
284 ENTRY(arm922_dma_flush_range)
285 bic r0, r0, #CACHE_DLINESIZE - 1
286 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
287 add r0, r0, #CACHE_DLINESIZE
288 cmp r0, r1
289 blo 1b
290 mcr p15, 0, r0, c7, c10, 4 @ drain WB
291 mov pc, lr
293 ENTRY(arm922_cache_fns)
294 .long arm922_flush_kern_cache_all
295 .long arm922_flush_user_cache_all
296 .long arm922_flush_user_cache_range
297 .long arm922_coherent_kern_range
298 .long arm922_coherent_user_range
299 .long arm922_flush_kern_dcache_area
300 .long arm922_dma_inv_range
301 .long arm922_dma_clean_range
302 .long arm922_dma_flush_range
304 #endif
307 ENTRY(cpu_arm922_dcache_clean_area)
308 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
309 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
310 add r0, r0, #CACHE_DLINESIZE
311 subs r1, r1, #CACHE_DLINESIZE
312 bhi 1b
313 #endif
314 mov pc, lr
316 /* =============================== PageTable ============================== */
318 /*
319 * cpu_arm922_switch_mm(pgd)
320 *
321 * Set the translation base pointer to be as described by pgd.
322 *
323 * pgd: new page tables
324 */
325 .align 5
326 ENTRY(cpu_arm922_switch_mm)
327 #ifdef CONFIG_MMU
328 mov ip, #0
329 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
330 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
331 #else
332 @ && 'Clean & Invalidate whole DCache'
333 @ && Re-written to use Index Ops.
334 @ && Uses registers r1, r3 and ip
336 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
337 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
338 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
339 subs r3, r3, #1 << 26
340 bcs 2b @ entries 63 to 0
341 subs r1, r1, #1 << 5
342 bcs 1b @ segments 7 to 0
343 #endif
344 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
345 mcr p15, 0, ip, c7, c10, 4 @ drain WB
346 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
347 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
348 #endif
349 mov pc, lr
351 /*
352 * cpu_arm922_set_pte_ext(ptep, pte, ext)
353 *
354 * Set a PTE and flush it out
355 */
356 .align 5
357 ENTRY(cpu_arm922_set_pte_ext)
358 #ifdef CONFIG_MMU
359 armv3_set_pte_ext
360 mov r0, r0
361 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
362 mcr p15, 0, r0, c7, c10, 4 @ drain WB
363 #endif /* CONFIG_MMU */
364 mov pc, lr
366 __INIT
368 .type __arm922_setup, #function
369 __arm922_setup:
370 mov r0, #0
371 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
372 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
373 #ifdef CONFIG_MMU
374 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
375 #endif
376 adr r5, arm922_crval
377 ldmia r5, {r5, r6}
378 mrc p15, 0, r0, c1, c0 @ get control register v4
379 bic r0, r0, r5
380 orr r0, r0, r6
381 mov pc, lr
382 .size __arm922_setup, . - __arm922_setup
384 /*
385 * R
386 * .RVI ZFRS BLDP WCAM
387 * ..11 0001 ..11 0101
388 *
389 */
390 .type arm922_crval, #object
391 arm922_crval:
392 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
394 __INITDATA
396 /*
397 * Purpose : Function pointers used to access above functions - all calls
398 * come through these
399 */
400 .type arm922_processor_functions, #object
401 arm922_processor_functions:
402 .word v4t_early_abort
403 .word legacy_pabort
404 .word cpu_arm922_proc_init
405 .word cpu_arm922_proc_fin
406 .word cpu_arm922_reset
407 .word cpu_arm922_do_idle
408 .word cpu_arm922_dcache_clean_area
409 .word cpu_arm922_switch_mm
410 .word cpu_arm922_set_pte_ext
411 .size arm922_processor_functions, . - arm922_processor_functions
413 .section ".rodata"
415 .type cpu_arch_name, #object
416 cpu_arch_name:
417 .asciz "armv4t"
418 .size cpu_arch_name, . - cpu_arch_name
420 .type cpu_elf_name, #object
421 cpu_elf_name:
422 .asciz "v4"
423 .size cpu_elf_name, . - cpu_elf_name
425 .type cpu_arm922_name, #object
426 cpu_arm922_name:
427 .asciz "ARM922T"
428 .size cpu_arm922_name, . - cpu_arm922_name
430 .align
432 .section ".proc.info.init", #alloc, #execinstr
434 .type __arm922_proc_info,#object
435 __arm922_proc_info:
436 .long 0x41009220
437 .long 0xff00fff0
438 .long PMD_TYPE_SECT | \
439 PMD_SECT_BUFFERABLE | \
440 PMD_SECT_CACHEABLE | \
441 PMD_BIT4 | \
442 PMD_SECT_AP_WRITE | \
443 PMD_SECT_AP_READ
444 .long PMD_TYPE_SECT | \
445 PMD_BIT4 | \
446 PMD_SECT_AP_WRITE | \
447 PMD_SECT_AP_READ
448 b __arm922_setup
449 .long cpu_arch_name
450 .long cpu_elf_name
451 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
452 .long cpu_arm922_name
453 .long arm922_processor_functions
454 .long v4wbi_tlb_fns
455 .long v4wb_user_fns
456 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
457 .long arm922_cache_fns
458 #else
459 .long v4wt_cache_fns
460 #endif
461 .size __arm922_proc_info, . - __arm922_proc_info