| blob | 64db6e275a442f610239fe9b692753c4d88d14f9 |
1 /*
2 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
3 *
4 * Copyright (C) 1999-2001 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm926.
25 *
26 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
27 */
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/hwcap.h>
32 #include <asm/pgtable-hwdef.h>
33 #include <asm/pgtable.h>
34 #include <asm/page.h>
35 #include <asm/ptrace.h>
36 #include "proc-macros.S"
38 /*
39 * This is the maximum size of an area which will be invalidated
40 * using the single invalidate entry instructions. Anything larger
41 * than this, and we go for the whole cache.
42 *
43 * This value should be chosen such that we choose the cheapest
44 * alternative.
45 */
46 #define CACHE_DLIMIT 16384
48 /*
49 * the cache line size of the I and D cache
50 */
51 #define CACHE_DLINESIZE 32
53 .text
54 /*
55 * cpu_arm926_proc_init()
56 */
57 ENTRY(cpu_arm926_proc_init)
58 mov pc, lr
60 /*
61 * cpu_arm926_proc_fin()
62 */
63 ENTRY(cpu_arm926_proc_fin)
64 stmfd sp!, {lr}
65 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
66 msr cpsr_c, ip
67 bl arm926_flush_kern_cache_all
68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 bic r0, r0, #0x1000 @ ...i............
70 bic r0, r0, #0x000e @ ............wca.
71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 ldmfd sp!, {pc}
74 /*
75 * cpu_arm926_reset(loc)
76 *
77 * Perform a soft reset of the system. Put the CPU into the
78 * same state as it would be if it had been reset, and branch
79 * to what would be the reset vector.
80 *
81 * loc: location to jump to for soft reset
82 */
83 .align 5
84 ENTRY(cpu_arm926_reset)
85 mov ip, #0
86 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
87 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 #ifdef CONFIG_MMU
89 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
90 #endif
91 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
92 bic ip, ip, #0x000f @ ............wcam
93 bic ip, ip, #0x1100 @ ...i...s........
94 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
95 mov pc, r0
97 /*
98 * cpu_arm926_do_idle()
99 *
100 * Called with IRQs disabled
101 */
102 .align 10
103 ENTRY(cpu_arm926_do_idle)
104 mov r0, #0
105 mrc p15, 0, r1, c1, c0, 0 @ Read control register
106 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
107 bic r2, r1, #1 << 12
108 mrs r3, cpsr @ Disable FIQs while Icache
109 orr ip, r3, #PSR_F_BIT @ is disabled
110 msr cpsr_c, ip
111 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
112 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
113 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
114 msr cpsr_c, r3 @ Restore FIQ state
115 mov pc, lr
117 /*
118 * flush_user_cache_all()
119 *
120 * Clean and invalidate all cache entries in a particular
121 * address space.
122 */
123 ENTRY(arm926_flush_user_cache_all)
124 /* FALLTHROUGH */
126 /*
127 * flush_kern_cache_all()
128 *
129 * Clean and invalidate the entire cache.
130 */
131 ENTRY(arm926_flush_kern_cache_all)
132 mov r2, #VM_EXEC
133 mov ip, #0
134 __flush_whole_cache:
135 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
136 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
137 #else
138 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
139 bne 1b
140 #endif
141 tst r2, #VM_EXEC
142 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
143 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
144 mov pc, lr
146 /*
147 * flush_user_cache_range(start, end, flags)
148 *
149 * Clean and invalidate a range of cache entries in the
150 * specified address range.
151 *
152 * - start - start address (inclusive)
153 * - end - end address (exclusive)
154 * - flags - vm_flags describing address space
155 */
156 ENTRY(arm926_flush_user_cache_range)
157 mov ip, #0
158 sub r3, r1, r0 @ calculate total size
159 cmp r3, #CACHE_DLIMIT
160 bgt __flush_whole_cache
161 1: tst r2, #VM_EXEC
162 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
163 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
164 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
165 add r0, r0, #CACHE_DLINESIZE
166 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
168 add r0, r0, #CACHE_DLINESIZE
169 #else
170 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
171 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
172 add r0, r0, #CACHE_DLINESIZE
173 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
175 add r0, r0, #CACHE_DLINESIZE
176 #endif
177 cmp r0, r1
178 blo 1b
179 tst r2, #VM_EXEC
180 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
181 mov pc, lr
183 /*
184 * coherent_kern_range(start, end)
185 *
186 * Ensure coherency between the Icache and the Dcache in the
187 * region described by start, end. If you have non-snooping
188 * Harvard caches, you need to implement this function.
189 *
190 * - start - virtual start address
191 * - end - virtual end address
192 */
193 ENTRY(arm926_coherent_kern_range)
194 /* FALLTHROUGH */
196 /*
197 * coherent_user_range(start, end)
198 *
199 * Ensure coherency between the Icache and the Dcache in the
200 * region described by start, end. If you have non-snooping
201 * Harvard caches, you need to implement this function.
202 *
203 * - start - virtual start address
204 * - end - virtual end address
205 */
206 ENTRY(arm926_coherent_user_range)
207 bic r0, r0, #CACHE_DLINESIZE - 1
208 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
209 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
210 add r0, r0, #CACHE_DLINESIZE
211 cmp r0, r1
212 blo 1b
213 mcr p15, 0, r0, c7, c10, 4 @ drain WB
214 mov pc, lr
216 /*
217 * flush_kern_dcache_area(void *addr, size_t size)
218 *
219 * Ensure no D cache aliasing occurs, either with itself or
220 * the I cache
221 *
222 * - addr - kernel address
223 * - size - region size
224 */
225 ENTRY(arm926_flush_kern_dcache_area)
226 add r1, r0, r1
227 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
228 add r0, r0, #CACHE_DLINESIZE
229 cmp r0, r1
230 blo 1b
231 mov r0, #0
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
233 mcr p15, 0, r0, c7, c10, 4 @ drain WB
234 mov pc, lr
236 /*
237 * dma_inv_range(start, end)
238 *
239 * Invalidate (discard) the specified virtual address range.
240 * May not write back any entries. If 'start' or 'end'
241 * are not cache line aligned, those lines must be written
242 * back.
243 *
244 * - start - virtual start address
245 * - end - virtual end address
246 *
247 * (same as v4wb)
248 */
249 ENTRY(arm926_dma_inv_range)
250 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
251 tst r0, #CACHE_DLINESIZE - 1
252 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
253 tst r1, #CACHE_DLINESIZE - 1
254 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
255 #endif
256 bic r0, r0, #CACHE_DLINESIZE - 1
257 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
258 add r0, r0, #CACHE_DLINESIZE
259 cmp r0, r1
260 blo 1b
261 mcr p15, 0, r0, c7, c10, 4 @ drain WB
262 mov pc, lr
264 /*
265 * dma_clean_range(start, end)
266 *
267 * Clean the specified virtual address range.
268 *
269 * - start - virtual start address
270 * - end - virtual end address
271 *
272 * (same as v4wb)
273 */
274 ENTRY(arm926_dma_clean_range)
275 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
276 bic r0, r0, #CACHE_DLINESIZE - 1
277 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
278 add r0, r0, #CACHE_DLINESIZE
279 cmp r0, r1
280 blo 1b
281 #endif
282 mcr p15, 0, r0, c7, c10, 4 @ drain WB
283 mov pc, lr
285 /*
286 * dma_flush_range(start, end)
287 *
288 * Clean and invalidate the specified virtual address range.
289 *
290 * - start - virtual start address
291 * - end - virtual end address
292 */
293 ENTRY(arm926_dma_flush_range)
294 bic r0, r0, #CACHE_DLINESIZE - 1
295 1:
296 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
297 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
298 #else
299 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
300 #endif
301 add r0, r0, #CACHE_DLINESIZE
302 cmp r0, r1
303 blo 1b
304 mcr p15, 0, r0, c7, c10, 4 @ drain WB
305 mov pc, lr
307 ENTRY(arm926_cache_fns)
308 .long arm926_flush_kern_cache_all
309 .long arm926_flush_user_cache_all
310 .long arm926_flush_user_cache_range
311 .long arm926_coherent_kern_range
312 .long arm926_coherent_user_range
313 .long arm926_flush_kern_dcache_area
314 .long arm926_dma_inv_range
315 .long arm926_dma_clean_range
316 .long arm926_dma_flush_range
318 ENTRY(cpu_arm926_dcache_clean_area)
319 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
320 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
321 add r0, r0, #CACHE_DLINESIZE
322 subs r1, r1, #CACHE_DLINESIZE
323 bhi 1b
324 #endif
325 mcr p15, 0, r0, c7, c10, 4 @ drain WB
326 mov pc, lr
328 /* =============================== PageTable ============================== */
330 /*
331 * cpu_arm926_switch_mm(pgd)
332 *
333 * Set the translation base pointer to be as described by pgd.
334 *
335 * pgd: new page tables
336 */
337 .align 5
338 ENTRY(cpu_arm926_switch_mm)
339 #ifdef CONFIG_MMU
340 mov ip, #0
341 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
342 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
343 #else
344 @ && 'Clean & Invalidate whole DCache'
345 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
346 bne 1b
347 #endif
348 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
349 mcr p15, 0, ip, c7, c10, 4 @ drain WB
350 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
351 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
352 #endif
353 mov pc, lr
355 /*
356 * cpu_arm926_set_pte_ext(ptep, pte, ext)
357 *
358 * Set a PTE and flush it out
359 */
360 .align 5
361 ENTRY(cpu_arm926_set_pte_ext)
362 #ifdef CONFIG_MMU
363 armv3_set_pte_ext
364 mov r0, r0
365 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
366 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
367 #endif
368 mcr p15, 0, r0, c7, c10, 4 @ drain WB
369 #endif
370 mov pc, lr
372 __INIT
374 .type __arm926_setup, #function
375 __arm926_setup:
376 mov r0, #0
377 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
378 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
379 #ifdef CONFIG_MMU
380 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
381 #endif
384 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
385 mov r0, #4 @ disable write-back on caches explicitly
386 mcr p15, 7, r0, c15, c0, 0
387 #endif
389 adr r5, arm926_crval
390 ldmia r5, {r5, r6}
391 mrc p15, 0, r0, c1, c0 @ get control register v4
392 bic r0, r0, r5
393 orr r0, r0, r6
394 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
395 orr r0, r0, #0x4000 @ .1.. .... .... ....
396 #endif
397 mov pc, lr
398 .size __arm926_setup, . - __arm926_setup
400 /*
401 * R
402 * .RVI ZFRS BLDP WCAM
403 * .011 0001 ..11 0101
404 *
405 */
406 .type arm926_crval, #object
407 arm926_crval:
408 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
410 __INITDATA
412 /*
413 * Purpose : Function pointers used to access above functions - all calls
414 * come through these
415 */
416 .type arm926_processor_functions, #object
417 arm926_processor_functions:
418 .word v5tj_early_abort
419 .word legacy_pabort
420 .word cpu_arm926_proc_init
421 .word cpu_arm926_proc_fin
422 .word cpu_arm926_reset
423 .word cpu_arm926_do_idle
424 .word cpu_arm926_dcache_clean_area
425 .word cpu_arm926_switch_mm
426 .word cpu_arm926_set_pte_ext
427 .size arm926_processor_functions, . - arm926_processor_functions
429 .section ".rodata"
431 .type cpu_arch_name, #object
432 cpu_arch_name:
433 .asciz "armv5tej"
434 .size cpu_arch_name, . - cpu_arch_name
436 .type cpu_elf_name, #object
437 cpu_elf_name:
438 .asciz "v5"
439 .size cpu_elf_name, . - cpu_elf_name
441 .type cpu_arm926_name, #object
442 cpu_arm926_name:
443 .asciz "ARM926EJ-S"
444 .size cpu_arm926_name, . - cpu_arm926_name
446 .align
448 .section ".proc.info.init", #alloc, #execinstr
450 .type __arm926_proc_info,#object
451 __arm926_proc_info:
452 .long 0x41069260 @ ARM926EJ-S (v5TEJ)
453 .long 0xff0ffff0
454 .long PMD_TYPE_SECT | \
455 PMD_SECT_BUFFERABLE | \
456 PMD_SECT_CACHEABLE | \
457 PMD_BIT4 | \
458 PMD_SECT_AP_WRITE | \
459 PMD_SECT_AP_READ
460 .long PMD_TYPE_SECT | \
461 PMD_BIT4 | \
462 PMD_SECT_AP_WRITE | \
463 PMD_SECT_AP_READ
464 b __arm926_setup
465 .long cpu_arch_name
466 .long cpu_elf_name
467 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
468 .long cpu_arm926_name
469 .long arm926_processor_functions
470 .long v4wbi_tlb_fns
471 .long v4wb_user_fns
472 .long arm926_cache_fns
473 .size __arm926_proc_info, . - __arm926_proc_info