| blob | 8196b9f401fb53f17cd0a215c384a872330e054d |
1 /*
2 * linux/arch/arm/mm/arm940.S: utility functions for ARM940T
3 *
4 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11 #include <linux/linkage.h>
12 #include <linux/init.h>
13 #include <asm/assembler.h>
14 #include <asm/hwcap.h>
15 #include <asm/pgtable-hwdef.h>
16 #include <asm/pgtable.h>
17 #include <asm/ptrace.h>
18 #include "proc-macros.S"
20 /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
21 #define CACHE_DLINESIZE 16
22 #define CACHE_DSEGMENTS 4
23 #define CACHE_DENTRIES 64
25 .text
26 /*
27 * cpu_arm940_proc_init()
28 * cpu_arm940_switch_mm()
29 *
30 * These are not required.
31 */
32 ENTRY(cpu_arm940_proc_init)
33 ENTRY(cpu_arm940_switch_mm)
34 mov pc, lr
36 /*
37 * cpu_arm940_proc_fin()
38 */
39 ENTRY(cpu_arm940_proc_fin)
40 stmfd sp!, {lr}
41 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
42 msr cpsr_c, ip
43 bl arm940_flush_kern_cache_all
44 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
45 bic r0, r0, #0x00001000 @ i-cache
46 bic r0, r0, #0x00000004 @ d-cache
47 mcr p15, 0, r0, c1, c0, 0 @ disable caches
48 ldmfd sp!, {pc}
50 /*
51 * cpu_arm940_reset(loc)
52 * Params : r0 = address to jump to
53 * Notes : This sets up everything for a reset
54 */
55 ENTRY(cpu_arm940_reset)
56 mov ip, #0
57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
60 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
61 bic ip, ip, #0x00000005 @ .............c.p
62 bic ip, ip, #0x00001000 @ i-cache
63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
64 mov pc, r0
66 /*
67 * cpu_arm940_do_idle()
68 */
69 .align 5
70 ENTRY(cpu_arm940_do_idle)
71 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
72 mov pc, lr
74 /*
75 * flush_user_cache_all()
76 */
77 ENTRY(arm940_flush_user_cache_all)
78 /* FALLTHROUGH */
80 /*
81 * flush_kern_cache_all()
82 *
83 * Clean and invalidate the entire cache.
84 */
85 ENTRY(arm940_flush_kern_cache_all)
86 mov r2, #VM_EXEC
87 /* FALLTHROUGH */
89 /*
90 * flush_user_cache_range(start, end, flags)
91 *
92 * There is no efficient way to flush a range of cache entries
93 * in the specified address range. Thus, flushes all.
94 *
95 * - start - start address (inclusive)
96 * - end - end address (exclusive)
97 * - flags - vm_flags describing address space
98 */
99 ENTRY(arm940_flush_user_cache_range)
100 mov ip, #0
101 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
102 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
103 #else
104 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
105 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
106 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
107 subs r3, r3, #1 << 26
108 bcs 2b @ entries 63 to 0
109 subs r1, r1, #1 << 4
110 bcs 1b @ segments 3 to 0
111 #endif
112 tst r2, #VM_EXEC
113 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
114 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
115 mov pc, lr
117 /*
118 * coherent_kern_range(start, end)
119 *
120 * Ensure coherency between the Icache and the Dcache in the
121 * region described by start, end. If you have non-snooping
122 * Harvard caches, you need to implement this function.
123 *
124 * - start - virtual start address
125 * - end - virtual end address
126 */
127 ENTRY(arm940_coherent_kern_range)
128 /* FALLTHROUGH */
130 /*
131 * coherent_user_range(start, end)
132 *
133 * Ensure coherency between the Icache and the Dcache in the
134 * region described by start, end. If you have non-snooping
135 * Harvard caches, you need to implement this function.
136 *
137 * - start - virtual start address
138 * - end - virtual end address
139 */
140 ENTRY(arm940_coherent_user_range)
141 /* FALLTHROUGH */
143 /*
144 * flush_kern_dcache_area(void *addr, size_t size)
145 *
146 * Ensure no D cache aliasing occurs, either with itself or
147 * the I cache
148 *
149 * - addr - kernel address
150 * - size - region size
151 */
152 ENTRY(arm940_flush_kern_dcache_area)
153 mov ip, #0
154 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
155 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
156 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
157 subs r3, r3, #1 << 26
158 bcs 2b @ entries 63 to 0
159 subs r1, r1, #1 << 4
160 bcs 1b @ segments 7 to 0
161 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
162 mcr p15, 0, ip, c7, c10, 4 @ drain WB
163 mov pc, lr
165 /*
166 * dma_inv_range(start, end)
167 *
168 * There is no efficient way to invalidate a specifid virtual
169 * address range. Thus, invalidates all.
170 *
171 * - start - virtual start address
172 * - end - virtual end address
173 */
174 ENTRY(arm940_dma_inv_range)
175 mov ip, #0
176 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
177 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
178 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
179 subs r3, r3, #1 << 26
180 bcs 2b @ entries 63 to 0
181 subs r1, r1, #1 << 4
182 bcs 1b @ segments 7 to 0
183 mcr p15, 0, ip, c7, c10, 4 @ drain WB
184 mov pc, lr
186 /*
187 * dma_clean_range(start, end)
188 *
189 * There is no efficient way to clean a specifid virtual
190 * address range. Thus, cleans all.
191 *
192 * - start - virtual start address
193 * - end - virtual end address
194 */
195 ENTRY(arm940_dma_clean_range)
196 ENTRY(cpu_arm940_dcache_clean_area)
197 mov ip, #0
198 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
199 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
200 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
201 2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
202 subs r3, r3, #1 << 26
203 bcs 2b @ entries 63 to 0
204 subs r1, r1, #1 << 4
205 bcs 1b @ segments 7 to 0
206 #endif
207 mcr p15, 0, ip, c7, c10, 4 @ drain WB
208 mov pc, lr
210 /*
211 * dma_flush_range(start, end)
212 *
213 * There is no efficient way to clean and invalidate a specifid
214 * virtual address range.
215 *
216 * - start - virtual start address
217 * - end - virtual end address
218 */
219 ENTRY(arm940_dma_flush_range)
220 mov ip, #0
221 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
222 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
223 2:
224 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
225 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
226 #else
227 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
228 #endif
229 subs r3, r3, #1 << 26
230 bcs 2b @ entries 63 to 0
231 subs r1, r1, #1 << 4
232 bcs 1b @ segments 7 to 0
233 mcr p15, 0, ip, c7, c10, 4 @ drain WB
234 mov pc, lr
236 ENTRY(arm940_cache_fns)
237 .long arm940_flush_kern_cache_all
238 .long arm940_flush_user_cache_all
239 .long arm940_flush_user_cache_range
240 .long arm940_coherent_kern_range
241 .long arm940_coherent_user_range
242 .long arm940_flush_kern_dcache_area
243 .long arm940_dma_inv_range
244 .long arm940_dma_clean_range
245 .long arm940_dma_flush_range
247 __INIT
249 .type __arm940_setup, #function
250 __arm940_setup:
251 mov r0, #0
252 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
253 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
254 mcr p15, 0, r0, c7, c10, 4 @ drain WB
256 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
257 mcr p15, 0, r0, c6, c4, 0
258 mcr p15, 0, r0, c6, c5, 0
259 mcr p15, 0, r0, c6, c6, 0
260 mcr p15, 0, r0, c6, c7, 0
262 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
263 mcr p15, 0, r0, c6, c4, 1
264 mcr p15, 0, r0, c6, c5, 1
265 mcr p15, 0, r0, c6, c6, 1
266 mcr p15, 0, r0, c6, c7, 1
268 mov r0, #0x0000003F @ base = 0, size = 4GB
269 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
270 mcr p15, 0, r0, c6, c0, 1
272 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
273 ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
274 mov r2, #10 @ 11 is the minimum (4KB)
275 1: add r2, r2, #1 @ area size *= 2
276 mov r1, r1, lsr #1
277 bne 1b @ count not zero r-shift
278 orr r0, r0, r2, lsl #1 @ the area register value
279 orr r0, r0, #1 @ set enable bit
280 mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
281 mcr p15, 0, r0, c6, c1, 1
283 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
284 ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
285 mov r2, #10 @ 11 is the minimum (4KB)
286 1: add r2, r2, #1 @ area size *= 2
287 mov r1, r1, lsr #1
288 bne 1b @ count not zero r-shift
289 orr r0, r0, r2, lsl #1 @ the area register value
290 orr r0, r0, #1 @ set enable bit
291 mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
292 mcr p15, 0, r0, c6, c2, 1
294 mov r0, #0x06
295 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
296 mcr p15, 0, r0, c2, c0, 1
297 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
298 mov r0, #0x00 @ disable whole write buffer
299 #else
300 mov r0, #0x02 @ Region 1 write bufferred
301 #endif
302 mcr p15, 0, r0, c3, c0, 0
304 mov r0, #0x10000
305 sub r0, r0, #1 @ r0 = 0xffff
306 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
307 mcr p15, 0, r0, c5, c0, 1
309 mrc p15, 0, r0, c1, c0 @ get control register
310 orr r0, r0, #0x00001000 @ I-cache
311 orr r0, r0, #0x00000005 @ MPU/D-cache
313 mov pc, lr
315 .size __arm940_setup, . - __arm940_setup
317 __INITDATA
319 /*
320 * Purpose : Function pointers used to access above functions - all calls
321 * come through these
322 */
323 .type arm940_processor_functions, #object
324 ENTRY(arm940_processor_functions)
325 .word nommu_early_abort
326 .word legacy_pabort
327 .word cpu_arm940_proc_init
328 .word cpu_arm940_proc_fin
329 .word cpu_arm940_reset
330 .word cpu_arm940_do_idle
331 .word cpu_arm940_dcache_clean_area
332 .word cpu_arm940_switch_mm
333 .word 0 @ cpu_*_set_pte
334 .size arm940_processor_functions, . - arm940_processor_functions
336 .section ".rodata"
338 .type cpu_arch_name, #object
339 cpu_arch_name:
340 .asciz "armv4t"
341 .size cpu_arch_name, . - cpu_arch_name
343 .type cpu_elf_name, #object
344 cpu_elf_name:
345 .asciz "v4"
346 .size cpu_elf_name, . - cpu_elf_name
348 .type cpu_arm940_name, #object
349 cpu_arm940_name:
350 .ascii "ARM940T"
351 .size cpu_arm940_name, . - cpu_arm940_name
353 .align
355 .section ".proc.info.init", #alloc, #execinstr
357 .type __arm940_proc_info,#object
358 __arm940_proc_info:
359 .long 0x41009400
360 .long 0xff00fff0
361 .long 0
362 b __arm940_setup
363 .long cpu_arch_name
364 .long cpu_elf_name
365 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
366 .long cpu_arm940_name
367 .long arm940_processor_functions
368 .long 0
369 .long 0
370 .long arm940_cache_fns
371 .size __arm940_proc_info, . - __arm940_proc_info