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acpiphp: Execute ACPI _REG method for hotadded devices
[linux/fpc-iii.git] / arch / arm / plat-omap / gpio.c
blobd2422c766cca215ecd6f51bfbfaa5ceeca303ac4
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30
31 /*
32 * OMAP1510 GPIO registers
33 */
34 #define OMAP1510_GPIO_BASE 0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43 #define OMAP1510_IH_GPIO_BASE 64
44
45 /*
46 * OMAP1610 specific GPIO registers
47 */
48 #define OMAP1610_GPIO1_BASE 0xfffbe400
49 #define OMAP1610_GPIO2_BASE 0xfffbec00
50 #define OMAP1610_GPIO3_BASE 0xfffbb400
51 #define OMAP1610_GPIO4_BASE 0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70 /*
71 * OMAP7XX specific GPIO registers
72 */
73 #define OMAP7XX_GPIO1_BASE 0xfffbc000
74 #define OMAP7XX_GPIO2_BASE 0xfffbc800
75 #define OMAP7XX_GPIO3_BASE 0xfffbd000
76 #define OMAP7XX_GPIO4_BASE 0xfffbd800
77 #define OMAP7XX_GPIO5_BASE 0xfffbe000
78 #define OMAP7XX_GPIO6_BASE 0xfffbe800
79 #define OMAP7XX_GPIO_DATA_INPUT 0x00
80 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
82 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
83 #define OMAP7XX_GPIO_INT_MASK 0x10
84 #define OMAP7XX_GPIO_INT_STATUS 0x14
85
86 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
87
88 /*
89 * omap24xx specific GPIO registers
90 */
91 #define OMAP242X_GPIO1_BASE 0x48018000
92 #define OMAP242X_GPIO2_BASE 0x4801a000
93 #define OMAP242X_GPIO3_BASE 0x4801c000
94 #define OMAP242X_GPIO4_BASE 0x4801e000
95
96 #define OMAP243X_GPIO1_BASE 0x4900C000
97 #define OMAP243X_GPIO2_BASE 0x4900E000
98 #define OMAP243X_GPIO3_BASE 0x49010000
99 #define OMAP243X_GPIO4_BASE 0x49012000
100 #define OMAP243X_GPIO5_BASE 0x480B6000
101
102 #define OMAP24XX_GPIO_REVISION 0x0000
103 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
104 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
105 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
106 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
107 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
108 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
109 #define OMAP24XX_GPIO_WAKE_EN 0x0020
110 #define OMAP24XX_GPIO_CTRL 0x0030
111 #define OMAP24XX_GPIO_OE 0x0034
112 #define OMAP24XX_GPIO_DATAIN 0x0038
113 #define OMAP24XX_GPIO_DATAOUT 0x003c
114 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
115 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
116 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
117 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
118 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
119 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
120 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
121 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
122 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
123 #define OMAP24XX_GPIO_SETWKUENA 0x0084
124 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
125 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
126
127 #define OMAP4_GPIO_REVISION 0x0000
128 #define OMAP4_GPIO_SYSCONFIG 0x0010
129 #define OMAP4_GPIO_EOI 0x0020
130 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
131 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
132 #define OMAP4_GPIO_IRQSTATUS0 0x002c
133 #define OMAP4_GPIO_IRQSTATUS1 0x0030
134 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
135 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
136 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
137 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138 #define OMAP4_GPIO_IRQWAKEN0 0x0044
139 #define OMAP4_GPIO_IRQWAKEN1 0x0048
140 #define OMAP4_GPIO_SYSSTATUS 0x0104
141 #define OMAP4_GPIO_CTRL 0x0130
142 #define OMAP4_GPIO_OE 0x0134
143 #define OMAP4_GPIO_DATAIN 0x0138
144 #define OMAP4_GPIO_DATAOUT 0x013c
145 #define OMAP4_GPIO_LEVELDETECT0 0x0140
146 #define OMAP4_GPIO_LEVELDETECT1 0x0144
147 #define OMAP4_GPIO_RISINGDETECT 0x0148
148 #define OMAP4_GPIO_FALLINGDETECT 0x014c
149 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
152 #define OMAP4_GPIO_SETDATAOUT 0x0194
153 /*
154 * omap34xx specific GPIO registers
155 */
156
157 #define OMAP34XX_GPIO1_BASE 0x48310000
158 #define OMAP34XX_GPIO2_BASE 0x49050000
159 #define OMAP34XX_GPIO3_BASE 0x49052000
160 #define OMAP34XX_GPIO4_BASE 0x49054000
161 #define OMAP34XX_GPIO5_BASE 0x49056000
162 #define OMAP34XX_GPIO6_BASE 0x49058000
163
164 /*
165 * OMAP44XX specific GPIO registers
166 */
167 #define OMAP44XX_GPIO1_BASE 0x4a310000
168 #define OMAP44XX_GPIO2_BASE 0x48055000
169 #define OMAP44XX_GPIO3_BASE 0x48057000
170 #define OMAP44XX_GPIO4_BASE 0x48059000
171 #define OMAP44XX_GPIO5_BASE 0x4805B000
172 #define OMAP44XX_GPIO6_BASE 0x4805D000
173
174 struct gpio_bank {
175 unsigned long pbase;
176 void __iomem *base;
177 u16 irq;
178 u16 virtual_irq_start;
179 int method;
180 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
181 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
182 u32 suspend_wakeup;
183 u32 saved_wakeup;
184 #endif
185 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
186 defined(CONFIG_ARCH_OMAP4)
187 u32 non_wakeup_gpios;
188 u32 enabled_non_wakeup_gpios;
189
190 u32 saved_datain;
191 u32 saved_fallingdetect;
192 u32 saved_risingdetect;
193 #endif
194 u32 level_mask;
195 u32 toggle_mask;
196 spinlock_t lock;
197 struct gpio_chip chip;
198 struct clk *dbck;
199 u32 mod_usage;
200 };
201
202 #define METHOD_MPUIO 0
203 #define METHOD_GPIO_1510 1
204 #define METHOD_GPIO_1610 2
205 #define METHOD_GPIO_7XX 3
206 #define METHOD_GPIO_24XX 5
207
208 #ifdef CONFIG_ARCH_OMAP16XX
209 static struct gpio_bank gpio_bank_1610[5] = {
210 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
211 METHOD_MPUIO },
212 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
213 METHOD_GPIO_1610 },
214 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
215 METHOD_GPIO_1610 },
216 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
217 METHOD_GPIO_1610 },
218 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
219 METHOD_GPIO_1610 },
220 };
221 #endif
222
223 #ifdef CONFIG_ARCH_OMAP15XX
224 static struct gpio_bank gpio_bank_1510[2] = {
225 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
226 METHOD_MPUIO },
227 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
228 METHOD_GPIO_1510 }
229 };
230 #endif
231
232 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
233 static struct gpio_bank gpio_bank_7xx[7] = {
234 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
235 METHOD_MPUIO },
236 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
237 METHOD_GPIO_7XX },
238 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
239 METHOD_GPIO_7XX },
240 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
241 METHOD_GPIO_7XX },
242 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
243 METHOD_GPIO_7XX },
244 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
245 METHOD_GPIO_7XX },
246 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
247 METHOD_GPIO_7XX },
248 };
249 #endif
250
251 #ifdef CONFIG_ARCH_OMAP24XX
252
253 static struct gpio_bank gpio_bank_242x[4] = {
254 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
255 METHOD_GPIO_24XX },
256 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
257 METHOD_GPIO_24XX },
258 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
259 METHOD_GPIO_24XX },
260 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
261 METHOD_GPIO_24XX },
262 };
263
264 static struct gpio_bank gpio_bank_243x[5] = {
265 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
266 METHOD_GPIO_24XX },
267 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
268 METHOD_GPIO_24XX },
269 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
270 METHOD_GPIO_24XX },
271 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
272 METHOD_GPIO_24XX },
273 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
274 METHOD_GPIO_24XX },
275 };
276
277 #endif
278
279 #ifdef CONFIG_ARCH_OMAP34XX
280 static struct gpio_bank gpio_bank_34xx[6] = {
281 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
282 METHOD_GPIO_24XX },
283 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
284 METHOD_GPIO_24XX },
285 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
286 METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
288 METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
290 METHOD_GPIO_24XX },
291 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
292 METHOD_GPIO_24XX },
293 };
294
295 struct omap3_gpio_regs {
296 u32 sysconfig;
297 u32 irqenable1;
298 u32 irqenable2;
299 u32 wake_en;
300 u32 ctrl;
301 u32 oe;
302 u32 leveldetect0;
303 u32 leveldetect1;
304 u32 risingdetect;
305 u32 fallingdetect;
306 u32 dataout;
307 u32 setwkuena;
308 u32 setdataout;
309 };
310
311 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
312 #endif
313
314 #ifdef CONFIG_ARCH_OMAP4
315 static struct gpio_bank gpio_bank_44xx[6] = {
316 { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
317 METHOD_GPIO_24XX },
318 { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
319 METHOD_GPIO_24XX },
320 { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
321 METHOD_GPIO_24XX },
322 { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
323 METHOD_GPIO_24XX },
324 { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
325 METHOD_GPIO_24XX },
326 { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
327 METHOD_GPIO_24XX },
328 };
329
330 #endif
331
332 static struct gpio_bank *gpio_bank;
333 static int gpio_bank_count;
334
335 static inline struct gpio_bank *get_gpio_bank(int gpio)
336 {
337 if (cpu_is_omap15xx()) {
338 if (OMAP_GPIO_IS_MPUIO(gpio))
339 return &gpio_bank[0];
340 return &gpio_bank[1];
341 }
342 if (cpu_is_omap16xx()) {
343 if (OMAP_GPIO_IS_MPUIO(gpio))
344 return &gpio_bank[0];
345 return &gpio_bank[1 + (gpio >> 4)];
346 }
347 if (cpu_is_omap7xx()) {
348 if (OMAP_GPIO_IS_MPUIO(gpio))
349 return &gpio_bank[0];
350 return &gpio_bank[1 + (gpio >> 5)];
351 }
352 if (cpu_is_omap24xx())
353 return &gpio_bank[gpio >> 5];
354 if (cpu_is_omap34xx() || cpu_is_omap44xx())
355 return &gpio_bank[gpio >> 5];
356 BUG();
357 return NULL;
358 }
359
360 static inline int get_gpio_index(int gpio)
361 {
362 if (cpu_is_omap7xx())
363 return gpio & 0x1f;
364 if (cpu_is_omap24xx())
365 return gpio & 0x1f;
366 if (cpu_is_omap34xx() || cpu_is_omap44xx())
367 return gpio & 0x1f;
368 return gpio & 0x0f;
369 }
370
371 static inline int gpio_valid(int gpio)
372 {
373 if (gpio < 0)
374 return -1;
375 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
376 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
377 return -1;
378 return 0;
379 }
380 if (cpu_is_omap15xx() && gpio < 16)
381 return 0;
382 if ((cpu_is_omap16xx()) && gpio < 64)
383 return 0;
384 if (cpu_is_omap7xx() && gpio < 192)
385 return 0;
386 if (cpu_is_omap24xx() && gpio < 128)
387 return 0;
388 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
389 return 0;
390 return -1;
391 }
392
393 static int check_gpio(int gpio)
394 {
395 if (unlikely(gpio_valid(gpio) < 0)) {
396 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
397 dump_stack();
398 return -1;
399 }
400 return 0;
401 }
402
403 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
404 {
405 void __iomem *reg = bank->base;
406 u32 l;
407
408 switch (bank->method) {
409 #ifdef CONFIG_ARCH_OMAP1
410 case METHOD_MPUIO:
411 reg += OMAP_MPUIO_IO_CNTL;
412 break;
413 #endif
414 #ifdef CONFIG_ARCH_OMAP15XX
415 case METHOD_GPIO_1510:
416 reg += OMAP1510_GPIO_DIR_CONTROL;
417 break;
418 #endif
419 #ifdef CONFIG_ARCH_OMAP16XX
420 case METHOD_GPIO_1610:
421 reg += OMAP1610_GPIO_DIRECTION;
422 break;
423 #endif
424 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
425 case METHOD_GPIO_7XX:
426 reg += OMAP7XX_GPIO_DIR_CONTROL;
427 break;
428 #endif
429 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
430 case METHOD_GPIO_24XX:
431 reg += OMAP24XX_GPIO_OE;
432 break;
433 #endif
434 #if defined(CONFIG_ARCH_OMAP4)
435 case METHOD_GPIO_24XX:
436 reg += OMAP4_GPIO_OE;
437 break;
438 #endif
439 default:
440 WARN_ON(1);
441 return;
442 }
443 l = __raw_readl(reg);
444 if (is_input)
445 l |= 1 << gpio;
446 else
447 l &= ~(1 << gpio);
448 __raw_writel(l, reg);
449 }
450
451 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
452 {
453 void __iomem *reg = bank->base;
454 u32 l = 0;
455
456 switch (bank->method) {
457 #ifdef CONFIG_ARCH_OMAP1
458 case METHOD_MPUIO:
459 reg += OMAP_MPUIO_OUTPUT;
460 l = __raw_readl(reg);
461 if (enable)
462 l |= 1 << gpio;
463 else
464 l &= ~(1 << gpio);
465 break;
466 #endif
467 #ifdef CONFIG_ARCH_OMAP15XX
468 case METHOD_GPIO_1510:
469 reg += OMAP1510_GPIO_DATA_OUTPUT;
470 l = __raw_readl(reg);
471 if (enable)
472 l |= 1 << gpio;
473 else
474 l &= ~(1 << gpio);
475 break;
476 #endif
477 #ifdef CONFIG_ARCH_OMAP16XX
478 case METHOD_GPIO_1610:
479 if (enable)
480 reg += OMAP1610_GPIO_SET_DATAOUT;
481 else
482 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
483 l = 1 << gpio;
484 break;
485 #endif
486 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
487 case METHOD_GPIO_7XX:
488 reg += OMAP7XX_GPIO_DATA_OUTPUT;
489 l = __raw_readl(reg);
490 if (enable)
491 l |= 1 << gpio;
492 else
493 l &= ~(1 << gpio);
494 break;
495 #endif
496 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
497 case METHOD_GPIO_24XX:
498 if (enable)
499 reg += OMAP24XX_GPIO_SETDATAOUT;
500 else
501 reg += OMAP24XX_GPIO_CLEARDATAOUT;
502 l = 1 << gpio;
503 break;
504 #endif
505 #ifdef CONFIG_ARCH_OMAP4
506 case METHOD_GPIO_24XX:
507 if (enable)
508 reg += OMAP4_GPIO_SETDATAOUT;
509 else
510 reg += OMAP4_GPIO_CLEARDATAOUT;
511 l = 1 << gpio;
512 break;
513 #endif
514 default:
515 WARN_ON(1);
516 return;
517 }
518 __raw_writel(l, reg);
519 }
520
521 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
522 {
523 void __iomem *reg;
524
525 if (check_gpio(gpio) < 0)
526 return -EINVAL;
527 reg = bank->base;
528 switch (bank->method) {
529 #ifdef CONFIG_ARCH_OMAP1
530 case METHOD_MPUIO:
531 reg += OMAP_MPUIO_INPUT_LATCH;
532 break;
533 #endif
534 #ifdef CONFIG_ARCH_OMAP15XX
535 case METHOD_GPIO_1510:
536 reg += OMAP1510_GPIO_DATA_INPUT;
537 break;
538 #endif
539 #ifdef CONFIG_ARCH_OMAP16XX
540 case METHOD_GPIO_1610:
541 reg += OMAP1610_GPIO_DATAIN;
542 break;
543 #endif
544 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
545 case METHOD_GPIO_7XX:
546 reg += OMAP7XX_GPIO_DATA_INPUT;
547 break;
548 #endif
549 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
550 case METHOD_GPIO_24XX:
551 reg += OMAP24XX_GPIO_DATAIN;
552 break;
553 #endif
554 #ifdef CONFIG_ARCH_OMAP4
555 case METHOD_GPIO_24XX:
556 reg += OMAP4_GPIO_DATAIN;
557 break;
558 #endif
559 default:
560 return -EINVAL;
561 }
562 return (__raw_readl(reg)
563 & (1 << get_gpio_index(gpio))) != 0;
564 }
565
566 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
567 {
568 void __iomem *reg;
569
570 if (check_gpio(gpio) < 0)
571 return -EINVAL;
572 reg = bank->base;
573
574 switch (bank->method) {
575 #ifdef CONFIG_ARCH_OMAP1
576 case METHOD_MPUIO:
577 reg += OMAP_MPUIO_OUTPUT;
578 break;
579 #endif
580 #ifdef CONFIG_ARCH_OMAP15XX
581 case METHOD_GPIO_1510:
582 reg += OMAP1510_GPIO_DATA_OUTPUT;
583 break;
584 #endif
585 #ifdef CONFIG_ARCH_OMAP16XX
586 case METHOD_GPIO_1610:
587 reg += OMAP1610_GPIO_DATAOUT;
588 break;
589 #endif
590 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
591 case METHOD_GPIO_7XX:
592 reg += OMAP7XX_GPIO_DATA_OUTPUT;
593 break;
594 #endif
595 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
596 defined(CONFIG_ARCH_OMAP4)
597 case METHOD_GPIO_24XX:
598 reg += OMAP24XX_GPIO_DATAOUT;
599 break;
600 #endif
601 default:
602 return -EINVAL;
603 }
604
605 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
606 }
607
608 #define MOD_REG_BIT(reg, bit_mask, set) \
609 do { \
610 int l = __raw_readl(base + reg); \
611 if (set) l |= bit_mask; \
612 else l &= ~bit_mask; \
613 __raw_writel(l, base + reg); \
614 } while(0)
615
616 void omap_set_gpio_debounce(int gpio, int enable)
617 {
618 struct gpio_bank *bank;
619 void __iomem *reg;
620 unsigned long flags;
621 u32 val, l = 1 << get_gpio_index(gpio);
622
623 if (cpu_class_is_omap1())
624 return;
625
626 bank = get_gpio_bank(gpio);
627 reg = bank->base;
628 #ifdef CONFIG_ARCH_OMAP4
629 reg += OMAP4_GPIO_DEBOUNCENABLE;
630 #else
631 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
632 #endif
633 if (!(bank->mod_usage & l)) {
634 printk(KERN_ERR "GPIO %d not requested\n", gpio);
635 return;
636 }
637
638 spin_lock_irqsave(&bank->lock, flags);
639 val = __raw_readl(reg);
640
641 if (enable && !(val & l))
642 val |= l;
643 else if (!enable && (val & l))
644 val &= ~l;
645 else
646 goto done;
647
648 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
649 if (enable)
650 clk_enable(bank->dbck);
651 else
652 clk_disable(bank->dbck);
653 }
654
655 __raw_writel(val, reg);
656 done:
657 spin_unlock_irqrestore(&bank->lock, flags);
658 }
659 EXPORT_SYMBOL(omap_set_gpio_debounce);
660
661 void omap_set_gpio_debounce_time(int gpio, int enc_time)
662 {
663 struct gpio_bank *bank;
664 void __iomem *reg;
665
666 if (cpu_class_is_omap1())
667 return;
668
669 bank = get_gpio_bank(gpio);
670 reg = bank->base;
671
672 if (!bank->mod_usage) {
673 printk(KERN_ERR "GPIO not requested\n");
674 return;
675 }
676
677 enc_time &= 0xff;
678 #ifdef CONFIG_ARCH_OMAP4
679 reg += OMAP4_GPIO_DEBOUNCINGTIME;
680 #else
681 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
682 #endif
683 __raw_writel(enc_time, reg);
684 }
685 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
686
687 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
688 defined(CONFIG_ARCH_OMAP4)
689 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
690 int trigger)
691 {
692 void __iomem *base = bank->base;
693 u32 gpio_bit = 1 << gpio;
694 u32 val;
695
696 if (cpu_is_omap44xx()) {
697 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
698 trigger & IRQ_TYPE_LEVEL_LOW);
699 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
700 trigger & IRQ_TYPE_LEVEL_HIGH);
701 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
702 trigger & IRQ_TYPE_EDGE_RISING);
703 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
704 trigger & IRQ_TYPE_EDGE_FALLING);
705 } else {
706 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
707 trigger & IRQ_TYPE_LEVEL_LOW);
708 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
709 trigger & IRQ_TYPE_LEVEL_HIGH);
710 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
711 trigger & IRQ_TYPE_EDGE_RISING);
712 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
713 trigger & IRQ_TYPE_EDGE_FALLING);
714 }
715 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
716 if (cpu_is_omap44xx()) {
717 if (trigger != 0)
718 __raw_writel(1 << gpio, bank->base+
719 OMAP4_GPIO_IRQWAKEN0);
720 else {
721 val = __raw_readl(bank->base +
722 OMAP4_GPIO_IRQWAKEN0);
723 __raw_writel(val & (~(1 << gpio)), bank->base +
724 OMAP4_GPIO_IRQWAKEN0);
725 }
726 } else {
727 if (trigger != 0)
728 __raw_writel(1 << gpio, bank->base
729 + OMAP24XX_GPIO_SETWKUENA);
730 else
731 __raw_writel(1 << gpio, bank->base
732 + OMAP24XX_GPIO_CLEARWKUENA);
733 }
734 } else {
735 if (trigger != 0)
736 bank->enabled_non_wakeup_gpios |= gpio_bit;
737 else
738 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
739 }
740
741 if (cpu_is_omap44xx()) {
742 bank->level_mask =
743 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
744 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
745 } else {
746 bank->level_mask =
747 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
748 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
749 }
750 }
751 #endif
752
753 #ifdef CONFIG_ARCH_OMAP1
754 /*
755 * This only applies to chips that can't do both rising and falling edge
756 * detection at once. For all other chips, this function is a noop.
757 */
758 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
759 {
760 void __iomem *reg = bank->base;
761 u32 l = 0;
762
763 switch (bank->method) {
764 case METHOD_MPUIO:
765 reg += OMAP_MPUIO_GPIO_INT_EDGE;
766 break;
767 #ifdef CONFIG_ARCH_OMAP15XX
768 case METHOD_GPIO_1510:
769 reg += OMAP1510_GPIO_INT_CONTROL;
770 break;
771 #endif
772 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
773 case METHOD_GPIO_7XX:
774 reg += OMAP7XX_GPIO_INT_CONTROL;
775 break;
776 #endif
777 default:
778 return;
779 }
780
781 l = __raw_readl(reg);
782 if ((l >> gpio) & 1)
783 l &= ~(1 << gpio);
784 else
785 l |= 1 << gpio;
786
787 __raw_writel(l, reg);
788 }
789 #endif
790
791 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
792 {
793 void __iomem *reg = bank->base;
794 u32 l = 0;
795
796 switch (bank->method) {
797 #ifdef CONFIG_ARCH_OMAP1
798 case METHOD_MPUIO:
799 reg += OMAP_MPUIO_GPIO_INT_EDGE;
800 l = __raw_readl(reg);
801 if (trigger & IRQ_TYPE_EDGE_BOTH)
802 bank->toggle_mask |= 1 << gpio;
803 if (trigger & IRQ_TYPE_EDGE_RISING)
804 l |= 1 << gpio;
805 else if (trigger & IRQ_TYPE_EDGE_FALLING)
806 l &= ~(1 << gpio);
807 else
808 goto bad;
809 break;
810 #endif
811 #ifdef CONFIG_ARCH_OMAP15XX
812 case METHOD_GPIO_1510:
813 reg += OMAP1510_GPIO_INT_CONTROL;
814 l = __raw_readl(reg);
815 if (trigger & IRQ_TYPE_EDGE_BOTH)
816 bank->toggle_mask |= 1 << gpio;
817 if (trigger & IRQ_TYPE_EDGE_RISING)
818 l |= 1 << gpio;
819 else if (trigger & IRQ_TYPE_EDGE_FALLING)
820 l &= ~(1 << gpio);
821 else
822 goto bad;
823 break;
824 #endif
825 #ifdef CONFIG_ARCH_OMAP16XX
826 case METHOD_GPIO_1610:
827 if (gpio & 0x08)
828 reg += OMAP1610_GPIO_EDGE_CTRL2;
829 else
830 reg += OMAP1610_GPIO_EDGE_CTRL1;
831 gpio &= 0x07;
832 l = __raw_readl(reg);
833 l &= ~(3 << (gpio << 1));
834 if (trigger & IRQ_TYPE_EDGE_RISING)
835 l |= 2 << (gpio << 1);
836 if (trigger & IRQ_TYPE_EDGE_FALLING)
837 l |= 1 << (gpio << 1);
838 if (trigger)
839 /* Enable wake-up during idle for dynamic tick */
840 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
841 else
842 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
843 break;
844 #endif
845 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
846 case METHOD_GPIO_7XX:
847 reg += OMAP7XX_GPIO_INT_CONTROL;
848 l = __raw_readl(reg);
849 if (trigger & IRQ_TYPE_EDGE_BOTH)
850 bank->toggle_mask |= 1 << gpio;
851 if (trigger & IRQ_TYPE_EDGE_RISING)
852 l |= 1 << gpio;
853 else if (trigger & IRQ_TYPE_EDGE_FALLING)
854 l &= ~(1 << gpio);
855 else
856 goto bad;
857 break;
858 #endif
859 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
860 defined(CONFIG_ARCH_OMAP4)
861 case METHOD_GPIO_24XX:
862 set_24xx_gpio_triggering(bank, gpio, trigger);
863 break;
864 #endif
865 default:
866 goto bad;
867 }
868 __raw_writel(l, reg);
869 return 0;
870 bad:
871 return -EINVAL;
872 }
873
874 static int gpio_irq_type(unsigned irq, unsigned type)
875 {
876 struct gpio_bank *bank;
877 unsigned gpio;
878 int retval;
879 unsigned long flags;
880
881 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
882 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
883 else
884 gpio = irq - IH_GPIO_BASE;
885
886 if (check_gpio(gpio) < 0)
887 return -EINVAL;
888
889 if (type & ~IRQ_TYPE_SENSE_MASK)
890 return -EINVAL;
891
892 /* OMAP1 allows only only edge triggering */
893 if (!cpu_class_is_omap2()
894 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
895 return -EINVAL;
896
897 bank = get_irq_chip_data(irq);
898 spin_lock_irqsave(&bank->lock, flags);
899 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
900 if (retval == 0) {
901 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
902 irq_desc[irq].status |= type;
903 }
904 spin_unlock_irqrestore(&bank->lock, flags);
905
906 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
907 __set_irq_handler_unlocked(irq, handle_level_irq);
908 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
909 __set_irq_handler_unlocked(irq, handle_edge_irq);
910
911 return retval;
912 }
913
914 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
915 {
916 void __iomem *reg = bank->base;
917
918 switch (bank->method) {
919 #ifdef CONFIG_ARCH_OMAP1
920 case METHOD_MPUIO:
921 /* MPUIO irqstatus is reset by reading the status register,
922 * so do nothing here */
923 return;
924 #endif
925 #ifdef CONFIG_ARCH_OMAP15XX
926 case METHOD_GPIO_1510:
927 reg += OMAP1510_GPIO_INT_STATUS;
928 break;
929 #endif
930 #ifdef CONFIG_ARCH_OMAP16XX
931 case METHOD_GPIO_1610:
932 reg += OMAP1610_GPIO_IRQSTATUS1;
933 break;
934 #endif
935 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
936 case METHOD_GPIO_7XX:
937 reg += OMAP7XX_GPIO_INT_STATUS;
938 break;
939 #endif
940 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
941 case METHOD_GPIO_24XX:
942 reg += OMAP24XX_GPIO_IRQSTATUS1;
943 break;
944 #endif
945 #if defined(CONFIG_ARCH_OMAP4)
946 case METHOD_GPIO_24XX:
947 reg += OMAP4_GPIO_IRQSTATUS0;
948 break;
949 #endif
950 default:
951 WARN_ON(1);
952 return;
953 }
954 __raw_writel(gpio_mask, reg);
955
956 /* Workaround for clearing DSP GPIO interrupts to allow retention */
957 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
958 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
959 #endif
960 #if defined(CONFIG_ARCH_OMAP4)
961 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
962 #endif
963 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
964 __raw_writel(gpio_mask, reg);
965
966 /* Flush posted write for the irq status to avoid spurious interrupts */
967 __raw_readl(reg);
968 }
969 }
970
971 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
972 {
973 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
974 }
975
976 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
977 {
978 void __iomem *reg = bank->base;
979 int inv = 0;
980 u32 l;
981 u32 mask;
982
983 switch (bank->method) {
984 #ifdef CONFIG_ARCH_OMAP1
985 case METHOD_MPUIO:
986 reg += OMAP_MPUIO_GPIO_MASKIT;
987 mask = 0xffff;
988 inv = 1;
989 break;
990 #endif
991 #ifdef CONFIG_ARCH_OMAP15XX
992 case METHOD_GPIO_1510:
993 reg += OMAP1510_GPIO_INT_MASK;
994 mask = 0xffff;
995 inv = 1;
996 break;
997 #endif
998 #ifdef CONFIG_ARCH_OMAP16XX
999 case METHOD_GPIO_1610:
1000 reg += OMAP1610_GPIO_IRQENABLE1;
1001 mask = 0xffff;
1002 break;
1003 #endif
1004 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1005 case METHOD_GPIO_7XX:
1006 reg += OMAP7XX_GPIO_INT_MASK;
1007 mask = 0xffffffff;
1008 inv = 1;
1009 break;
1010 #endif
1011 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1012 case METHOD_GPIO_24XX:
1013 reg += OMAP24XX_GPIO_IRQENABLE1;
1014 mask = 0xffffffff;
1015 break;
1016 #endif
1017 #if defined(CONFIG_ARCH_OMAP4)
1018 case METHOD_GPIO_24XX:
1019 reg += OMAP4_GPIO_IRQSTATUSSET0;
1020 mask = 0xffffffff;
1021 break;
1022 #endif
1023 default:
1024 WARN_ON(1);
1025 return 0;
1026 }
1027
1028 l = __raw_readl(reg);
1029 if (inv)
1030 l = ~l;
1031 l &= mask;
1032 return l;
1033 }
1034
1035 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1036 {
1037 void __iomem *reg = bank->base;
1038 u32 l;
1039
1040 switch (bank->method) {
1041 #ifdef CONFIG_ARCH_OMAP1
1042 case METHOD_MPUIO:
1043 reg += OMAP_MPUIO_GPIO_MASKIT;
1044 l = __raw_readl(reg);
1045 if (enable)
1046 l &= ~(gpio_mask);
1047 else
1048 l |= gpio_mask;
1049 break;
1050 #endif
1051 #ifdef CONFIG_ARCH_OMAP15XX
1052 case METHOD_GPIO_1510:
1053 reg += OMAP1510_GPIO_INT_MASK;
1054 l = __raw_readl(reg);
1055 if (enable)
1056 l &= ~(gpio_mask);
1057 else
1058 l |= gpio_mask;
1059 break;
1060 #endif
1061 #ifdef CONFIG_ARCH_OMAP16XX
1062 case METHOD_GPIO_1610:
1063 if (enable)
1064 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1065 else
1066 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1067 l = gpio_mask;
1068 break;
1069 #endif
1070 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1071 case METHOD_GPIO_7XX:
1072 reg += OMAP7XX_GPIO_INT_MASK;
1073 l = __raw_readl(reg);
1074 if (enable)
1075 l &= ~(gpio_mask);
1076 else
1077 l |= gpio_mask;
1078 break;
1079 #endif
1080 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1081 case METHOD_GPIO_24XX:
1082 if (enable)
1083 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1084 else
1085 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1086 l = gpio_mask;
1087 break;
1088 #endif
1089 #ifdef CONFIG_ARCH_OMAP4
1090 case METHOD_GPIO_24XX:
1091 if (enable)
1092 reg += OMAP4_GPIO_IRQSTATUSSET0;
1093 else
1094 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1095 l = gpio_mask;
1096 break;
1097 #endif
1098 default:
1099 WARN_ON(1);
1100 return;
1101 }
1102 __raw_writel(l, reg);
1103 }
1104
1105 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1106 {
1107 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1108 }
1109
1110 /*
1111 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1112 * 1510 does not seem to have a wake-up register. If JTAG is connected
1113 * to the target, system will wake up always on GPIO events. While
1114 * system is running all registered GPIO interrupts need to have wake-up
1115 * enabled. When system is suspended, only selected GPIO interrupts need
1116 * to have wake-up enabled.
1117 */
1118 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1119 {
1120 unsigned long uninitialized_var(flags);
1121
1122 switch (bank->method) {
1123 #ifdef CONFIG_ARCH_OMAP16XX
1124 case METHOD_MPUIO:
1125 case METHOD_GPIO_1610:
1126 spin_lock_irqsave(&bank->lock, flags);
1127 if (enable)
1128 bank->suspend_wakeup |= (1 << gpio);
1129 else
1130 bank->suspend_wakeup &= ~(1 << gpio);
1131 spin_unlock_irqrestore(&bank->lock, flags);
1132 return 0;
1133 #endif
1134 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1135 defined(CONFIG_ARCH_OMAP4)
1136 case METHOD_GPIO_24XX:
1137 if (bank->non_wakeup_gpios & (1 << gpio)) {
1138 printk(KERN_ERR "Unable to modify wakeup on "
1139 "non-wakeup GPIO%d\n",
1140 (bank - gpio_bank) * 32 + gpio);
1141 return -EINVAL;
1142 }
1143 spin_lock_irqsave(&bank->lock, flags);
1144 if (enable)
1145 bank->suspend_wakeup |= (1 << gpio);
1146 else
1147 bank->suspend_wakeup &= ~(1 << gpio);
1148 spin_unlock_irqrestore(&bank->lock, flags);
1149 return 0;
1150 #endif
1151 default:
1152 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1153 bank->method);
1154 return -EINVAL;
1155 }
1156 }
1157
1158 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1159 {
1160 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1161 _set_gpio_irqenable(bank, gpio, 0);
1162 _clear_gpio_irqstatus(bank, gpio);
1163 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1164 }
1165
1166 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1167 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1168 {
1169 unsigned int gpio = irq - IH_GPIO_BASE;
1170 struct gpio_bank *bank;
1171 int retval;
1172
1173 if (check_gpio(gpio) < 0)
1174 return -ENODEV;
1175 bank = get_irq_chip_data(irq);
1176 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1177
1178 return retval;
1179 }
1180
1181 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1182 {
1183 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1184 unsigned long flags;
1185
1186 spin_lock_irqsave(&bank->lock, flags);
1187
1188 /* Set trigger to none. You need to enable the desired trigger with
1189 * request_irq() or set_irq_type().
1190 */
1191 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1192
1193 #ifdef CONFIG_ARCH_OMAP15XX
1194 if (bank->method == METHOD_GPIO_1510) {
1195 void __iomem *reg;
1196
1197 /* Claim the pin for MPU */
1198 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1199 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1200 }
1201 #endif
1202 if (!cpu_class_is_omap1()) {
1203 if (!bank->mod_usage) {
1204 u32 ctrl;
1205 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1206 ctrl &= 0xFFFFFFFE;
1207 /* Module is enabled, clocks are not gated */
1208 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1209 }
1210 bank->mod_usage |= 1 << offset;
1211 }
1212 spin_unlock_irqrestore(&bank->lock, flags);
1213
1214 return 0;
1215 }
1216
1217 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1218 {
1219 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1220 unsigned long flags;
1221
1222 spin_lock_irqsave(&bank->lock, flags);
1223 #ifdef CONFIG_ARCH_OMAP16XX
1224 if (bank->method == METHOD_GPIO_1610) {
1225 /* Disable wake-up during idle for dynamic tick */
1226 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1227 __raw_writel(1 << offset, reg);
1228 }
1229 #endif
1230 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1231 defined(CONFIG_ARCH_OMAP4)
1232 if (bank->method == METHOD_GPIO_24XX) {
1233 /* Disable wake-up during idle for dynamic tick */
1234 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1235 __raw_writel(1 << offset, reg);
1236 }
1237 #endif
1238 if (!cpu_class_is_omap1()) {
1239 bank->mod_usage &= ~(1 << offset);
1240 if (!bank->mod_usage) {
1241 u32 ctrl;
1242 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1243 /* Module is disabled, clocks are gated */
1244 ctrl |= 1;
1245 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1246 }
1247 }
1248 _reset_gpio(bank, bank->chip.base + offset);
1249 spin_unlock_irqrestore(&bank->lock, flags);
1250 }
1251
1252 /*
1253 * We need to unmask the GPIO bank interrupt as soon as possible to
1254 * avoid missing GPIO interrupts for other lines in the bank.
1255 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1256 * in the bank to avoid missing nested interrupts for a GPIO line.
1257 * If we wait to unmask individual GPIO lines in the bank after the
1258 * line's interrupt handler has been run, we may miss some nested
1259 * interrupts.
1260 */
1261 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1262 {
1263 void __iomem *isr_reg = NULL;
1264 u32 isr;
1265 unsigned int gpio_irq, gpio_index;
1266 struct gpio_bank *bank;
1267 u32 retrigger = 0;
1268 int unmasked = 0;
1269
1270 desc->chip->ack(irq);
1271
1272 bank = get_irq_data(irq);
1273 #ifdef CONFIG_ARCH_OMAP1
1274 if (bank->method == METHOD_MPUIO)
1275 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1276 #endif
1277 #ifdef CONFIG_ARCH_OMAP15XX
1278 if (bank->method == METHOD_GPIO_1510)
1279 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1280 #endif
1281 #if defined(CONFIG_ARCH_OMAP16XX)
1282 if (bank->method == METHOD_GPIO_1610)
1283 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1284 #endif
1285 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1286 if (bank->method == METHOD_GPIO_7XX)
1287 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1288 #endif
1289 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1290 if (bank->method == METHOD_GPIO_24XX)
1291 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1292 #endif
1293 #if defined(CONFIG_ARCH_OMAP4)
1294 if (bank->method == METHOD_GPIO_24XX)
1295 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1296 #endif
1297 while(1) {
1298 u32 isr_saved, level_mask = 0;
1299 u32 enabled;
1300
1301 enabled = _get_gpio_irqbank_mask(bank);
1302 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1303
1304 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1305 isr &= 0x0000ffff;
1306
1307 if (cpu_class_is_omap2()) {
1308 level_mask = bank->level_mask & enabled;
1309 }
1310
1311 /* clear edge sensitive interrupts before handler(s) are
1312 called so that we don't miss any interrupt occurred while
1313 executing them */
1314 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1315 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1316 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1317
1318 /* if there is only edge sensitive GPIO pin interrupts
1319 configured, we could unmask GPIO bank interrupt immediately */
1320 if (!level_mask && !unmasked) {
1321 unmasked = 1;
1322 desc->chip->unmask(irq);
1323 }
1324
1325 isr |= retrigger;
1326 retrigger = 0;
1327 if (!isr)
1328 break;
1329
1330 gpio_irq = bank->virtual_irq_start;
1331 for (; isr != 0; isr >>= 1, gpio_irq++) {
1332 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1333
1334 if (!(isr & 1))
1335 continue;
1336
1337 #ifdef CONFIG_ARCH_OMAP1
1338 /*
1339 * Some chips can't respond to both rising and falling
1340 * at the same time. If this irq was requested with
1341 * both flags, we need to flip the ICR data for the IRQ
1342 * to respond to the IRQ for the opposite direction.
1343 * This will be indicated in the bank toggle_mask.
1344 */
1345 if (bank->toggle_mask & (1 << gpio_index))
1346 _toggle_gpio_edge_triggering(bank, gpio_index);
1347 #endif
1348
1349 generic_handle_irq(gpio_irq);
1350 }
1351 }
1352 /* if bank has any level sensitive GPIO pin interrupt
1353 configured, we must unmask the bank interrupt only after
1354 handler(s) are executed in order to avoid spurious bank
1355 interrupt */
1356 if (!unmasked)
1357 desc->chip->unmask(irq);
1358
1359 }
1360
1361 static void gpio_irq_shutdown(unsigned int irq)
1362 {
1363 unsigned int gpio = irq - IH_GPIO_BASE;
1364 struct gpio_bank *bank = get_irq_chip_data(irq);
1365
1366 _reset_gpio(bank, gpio);
1367 }
1368
1369 static void gpio_ack_irq(unsigned int irq)
1370 {
1371 unsigned int gpio = irq - IH_GPIO_BASE;
1372 struct gpio_bank *bank = get_irq_chip_data(irq);
1373
1374 _clear_gpio_irqstatus(bank, gpio);
1375 }
1376
1377 static void gpio_mask_irq(unsigned int irq)
1378 {
1379 unsigned int gpio = irq - IH_GPIO_BASE;
1380 struct gpio_bank *bank = get_irq_chip_data(irq);
1381
1382 _set_gpio_irqenable(bank, gpio, 0);
1383 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1384 }
1385
1386 static void gpio_unmask_irq(unsigned int irq)
1387 {
1388 unsigned int gpio = irq - IH_GPIO_BASE;
1389 struct gpio_bank *bank = get_irq_chip_data(irq);
1390 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1391 struct irq_desc *desc = irq_to_desc(irq);
1392 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1393
1394 if (trigger)
1395 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1396
1397 /* For level-triggered GPIOs, the clearing must be done after
1398 * the HW source is cleared, thus after the handler has run */
1399 if (bank->level_mask & irq_mask) {
1400 _set_gpio_irqenable(bank, gpio, 0);
1401 _clear_gpio_irqstatus(bank, gpio);
1402 }
1403
1404 _set_gpio_irqenable(bank, gpio, 1);
1405 }
1406
1407 static struct irq_chip gpio_irq_chip = {
1408 .name = "GPIO",
1409 .shutdown = gpio_irq_shutdown,
1410 .ack = gpio_ack_irq,
1411 .mask = gpio_mask_irq,
1412 .unmask = gpio_unmask_irq,
1413 .set_type = gpio_irq_type,
1414 .set_wake = gpio_wake_enable,
1415 };
1416
1417 /*---------------------------------------------------------------------*/
1418
1419 #ifdef CONFIG_ARCH_OMAP1
1420
1421 /* MPUIO uses the always-on 32k clock */
1422
1423 static void mpuio_ack_irq(unsigned int irq)
1424 {
1425 /* The ISR is reset automatically, so do nothing here. */
1426 }
1427
1428 static void mpuio_mask_irq(unsigned int irq)
1429 {
1430 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1431 struct gpio_bank *bank = get_irq_chip_data(irq);
1432
1433 _set_gpio_irqenable(bank, gpio, 0);
1434 }
1435
1436 static void mpuio_unmask_irq(unsigned int irq)
1437 {
1438 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1439 struct gpio_bank *bank = get_irq_chip_data(irq);
1440
1441 _set_gpio_irqenable(bank, gpio, 1);
1442 }
1443
1444 static struct irq_chip mpuio_irq_chip = {
1445 .name = "MPUIO",
1446 .ack = mpuio_ack_irq,
1447 .mask = mpuio_mask_irq,
1448 .unmask = mpuio_unmask_irq,
1449 .set_type = gpio_irq_type,
1450 #ifdef CONFIG_ARCH_OMAP16XX
1451 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1452 .set_wake = gpio_wake_enable,
1453 #endif
1454 };
1455
1456
1457 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1458
1459
1460 #ifdef CONFIG_ARCH_OMAP16XX
1461
1462 #include <linux/platform_device.h>
1463
1464 static int omap_mpuio_suspend_noirq(struct device *dev)
1465 {
1466 struct platform_device *pdev = to_platform_device(dev);
1467 struct gpio_bank *bank = platform_get_drvdata(pdev);
1468 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1469 unsigned long flags;
1470
1471 spin_lock_irqsave(&bank->lock, flags);
1472 bank->saved_wakeup = __raw_readl(mask_reg);
1473 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1474 spin_unlock_irqrestore(&bank->lock, flags);
1475
1476 return 0;
1477 }
1478
1479 static int omap_mpuio_resume_noirq(struct device *dev)
1480 {
1481 struct platform_device *pdev = to_platform_device(dev);
1482 struct gpio_bank *bank = platform_get_drvdata(pdev);
1483 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1484 unsigned long flags;
1485
1486 spin_lock_irqsave(&bank->lock, flags);
1487 __raw_writel(bank->saved_wakeup, mask_reg);
1488 spin_unlock_irqrestore(&bank->lock, flags);
1489
1490 return 0;
1491 }
1492
1493 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1494 .suspend_noirq = omap_mpuio_suspend_noirq,
1495 .resume_noirq = omap_mpuio_resume_noirq,
1496 };
1497
1498 /* use platform_driver for this, now that there's no longer any
1499 * point to sys_device (other than not disturbing old code).
1500 */
1501 static struct platform_driver omap_mpuio_driver = {
1502 .driver = {
1503 .name = "mpuio",
1504 .pm = &omap_mpuio_dev_pm_ops,
1505 },
1506 };
1507
1508 static struct platform_device omap_mpuio_device = {
1509 .name = "mpuio",
1510 .id = -1,
1511 .dev = {
1512 .driver = &omap_mpuio_driver.driver,
1513 }
1514 /* could list the /proc/iomem resources */
1515 };
1516
1517 static inline void mpuio_init(void)
1518 {
1519 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1520
1521 if (platform_driver_register(&omap_mpuio_driver) == 0)
1522 (void) platform_device_register(&omap_mpuio_device);
1523 }
1524
1525 #else
1526 static inline void mpuio_init(void) {}
1527 #endif /* 16xx */
1528
1529 #else
1530
1531 extern struct irq_chip mpuio_irq_chip;
1532
1533 #define bank_is_mpuio(bank) 0
1534 static inline void mpuio_init(void) {}
1535
1536 #endif
1537
1538 /*---------------------------------------------------------------------*/
1539
1540 /* REVISIT these are stupid implementations! replace by ones that
1541 * don't switch on METHOD_* and which mostly avoid spinlocks
1542 */
1543
1544 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1545 {
1546 struct gpio_bank *bank;
1547 unsigned long flags;
1548
1549 bank = container_of(chip, struct gpio_bank, chip);
1550 spin_lock_irqsave(&bank->lock, flags);
1551 _set_gpio_direction(bank, offset, 1);
1552 spin_unlock_irqrestore(&bank->lock, flags);
1553 return 0;
1554 }
1555
1556 static int gpio_is_input(struct gpio_bank *bank, int mask)
1557 {
1558 void __iomem *reg = bank->base;
1559
1560 switch (bank->method) {
1561 case METHOD_MPUIO:
1562 reg += OMAP_MPUIO_IO_CNTL;
1563 break;
1564 case METHOD_GPIO_1510:
1565 reg += OMAP1510_GPIO_DIR_CONTROL;
1566 break;
1567 case METHOD_GPIO_1610:
1568 reg += OMAP1610_GPIO_DIRECTION;
1569 break;
1570 case METHOD_GPIO_7XX:
1571 reg += OMAP7XX_GPIO_DIR_CONTROL;
1572 break;
1573 case METHOD_GPIO_24XX:
1574 reg += OMAP24XX_GPIO_OE;
1575 break;
1576 }
1577 return __raw_readl(reg) & mask;
1578 }
1579
1580 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1581 {
1582 struct gpio_bank *bank;
1583 void __iomem *reg;
1584 int gpio;
1585 u32 mask;
1586
1587 gpio = chip->base + offset;
1588 bank = get_gpio_bank(gpio);
1589 reg = bank->base;
1590 mask = 1 << get_gpio_index(gpio);
1591
1592 if (gpio_is_input(bank, mask))
1593 return _get_gpio_datain(bank, gpio);
1594 else
1595 return _get_gpio_dataout(bank, gpio);
1596 }
1597
1598 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1599 {
1600 struct gpio_bank *bank;
1601 unsigned long flags;
1602
1603 bank = container_of(chip, struct gpio_bank, chip);
1604 spin_lock_irqsave(&bank->lock, flags);
1605 _set_gpio_dataout(bank, offset, value);
1606 _set_gpio_direction(bank, offset, 0);
1607 spin_unlock_irqrestore(&bank->lock, flags);
1608 return 0;
1609 }
1610
1611 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1612 {
1613 struct gpio_bank *bank;
1614 unsigned long flags;
1615
1616 bank = container_of(chip, struct gpio_bank, chip);
1617 spin_lock_irqsave(&bank->lock, flags);
1618 _set_gpio_dataout(bank, offset, value);
1619 spin_unlock_irqrestore(&bank->lock, flags);
1620 }
1621
1622 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1623 {
1624 struct gpio_bank *bank;
1625
1626 bank = container_of(chip, struct gpio_bank, chip);
1627 return bank->virtual_irq_start + offset;
1628 }
1629
1630 /*---------------------------------------------------------------------*/
1631
1632 static int initialized;
1633 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1634 static struct clk * gpio_ick;
1635 #endif
1636
1637 #if defined(CONFIG_ARCH_OMAP2)
1638 static struct clk * gpio_fck;
1639 #endif
1640
1641 #if defined(CONFIG_ARCH_OMAP2430)
1642 static struct clk * gpio5_ick;
1643 static struct clk * gpio5_fck;
1644 #endif
1645
1646 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1647 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1648 #endif
1649
1650 static void __init omap_gpio_show_rev(void)
1651 {
1652 u32 rev;
1653
1654 if (cpu_is_omap16xx())
1655 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1656 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1657 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1658 else if (cpu_is_omap44xx())
1659 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1660 else
1661 return;
1662
1663 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1664 (rev >> 4) & 0x0f, rev & 0x0f);
1665 }
1666
1667 /* This lock class tells lockdep that GPIO irqs are in a different
1668 * category than their parents, so it won't report false recursion.
1669 */
1670 static struct lock_class_key gpio_lock_class;
1671
1672 static int __init _omap_gpio_init(void)
1673 {
1674 int i;
1675 int gpio = 0;
1676 struct gpio_bank *bank;
1677 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1678 char clk_name[11];
1679
1680 initialized = 1;
1681
1682 #if defined(CONFIG_ARCH_OMAP1)
1683 if (cpu_is_omap15xx()) {
1684 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1685 if (IS_ERR(gpio_ick))
1686 printk("Could not get arm_gpio_ck\n");
1687 else
1688 clk_enable(gpio_ick);
1689 }
1690 #endif
1691 #if defined(CONFIG_ARCH_OMAP2)
1692 if (cpu_class_is_omap2()) {
1693 gpio_ick = clk_get(NULL, "gpios_ick");
1694 if (IS_ERR(gpio_ick))
1695 printk("Could not get gpios_ick\n");
1696 else
1697 clk_enable(gpio_ick);
1698 gpio_fck = clk_get(NULL, "gpios_fck");
1699 if (IS_ERR(gpio_fck))
1700 printk("Could not get gpios_fck\n");
1701 else
1702 clk_enable(gpio_fck);
1703
1704 /*
1705 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1706 */
1707 #if defined(CONFIG_ARCH_OMAP2430)
1708 if (cpu_is_omap2430()) {
1709 gpio5_ick = clk_get(NULL, "gpio5_ick");
1710 if (IS_ERR(gpio5_ick))
1711 printk("Could not get gpio5_ick\n");
1712 else
1713 clk_enable(gpio5_ick);
1714 gpio5_fck = clk_get(NULL, "gpio5_fck");
1715 if (IS_ERR(gpio5_fck))
1716 printk("Could not get gpio5_fck\n");
1717 else
1718 clk_enable(gpio5_fck);
1719 }
1720 #endif
1721 }
1722 #endif
1723
1724 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1725 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1726 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1727 sprintf(clk_name, "gpio%d_ick", i + 1);
1728 gpio_iclks[i] = clk_get(NULL, clk_name);
1729 if (IS_ERR(gpio_iclks[i]))
1730 printk(KERN_ERR "Could not get %s\n", clk_name);
1731 else
1732 clk_enable(gpio_iclks[i]);
1733 }
1734 }
1735 #endif
1736
1737
1738 #ifdef CONFIG_ARCH_OMAP15XX
1739 if (cpu_is_omap15xx()) {
1740 gpio_bank_count = 2;
1741 gpio_bank = gpio_bank_1510;
1742 bank_size = SZ_2K;
1743 }
1744 #endif
1745 #if defined(CONFIG_ARCH_OMAP16XX)
1746 if (cpu_is_omap16xx()) {
1747 gpio_bank_count = 5;
1748 gpio_bank = gpio_bank_1610;
1749 bank_size = SZ_2K;
1750 }
1751 #endif
1752 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1753 if (cpu_is_omap7xx()) {
1754 gpio_bank_count = 7;
1755 gpio_bank = gpio_bank_7xx;
1756 bank_size = SZ_2K;
1757 }
1758 #endif
1759 #ifdef CONFIG_ARCH_OMAP24XX
1760 if (cpu_is_omap242x()) {
1761 gpio_bank_count = 4;
1762 gpio_bank = gpio_bank_242x;
1763 }
1764 if (cpu_is_omap243x()) {
1765 gpio_bank_count = 5;
1766 gpio_bank = gpio_bank_243x;
1767 }
1768 #endif
1769 #ifdef CONFIG_ARCH_OMAP34XX
1770 if (cpu_is_omap34xx()) {
1771 gpio_bank_count = OMAP34XX_NR_GPIOS;
1772 gpio_bank = gpio_bank_34xx;
1773 }
1774 #endif
1775 #ifdef CONFIG_ARCH_OMAP4
1776 if (cpu_is_omap44xx()) {
1777 gpio_bank_count = OMAP34XX_NR_GPIOS;
1778 gpio_bank = gpio_bank_44xx;
1779 }
1780 #endif
1781 for (i = 0; i < gpio_bank_count; i++) {
1782 int j, gpio_count = 16;
1783
1784 bank = &gpio_bank[i];
1785 spin_lock_init(&bank->lock);
1786
1787 /* Static mapping, never released */
1788 bank->base = ioremap(bank->pbase, bank_size);
1789 if (!bank->base) {
1790 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1791 continue;
1792 }
1793
1794 if (bank_is_mpuio(bank))
1795 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1796 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1797 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1798 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1799 }
1800 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1801 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1802 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1803 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1804 }
1805 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1806 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1807 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1808
1809 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1810 }
1811
1812 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1813 defined(CONFIG_ARCH_OMAP4)
1814 if (bank->method == METHOD_GPIO_24XX) {
1815 static const u32 non_wakeup_gpios[] = {
1816 0xe203ffc0, 0x08700040
1817 };
1818 if (cpu_is_omap44xx()) {
1819 __raw_writel(0xffffffff, bank->base +
1820 OMAP4_GPIO_IRQSTATUSCLR0);
1821 __raw_writew(0x0015, bank->base +
1822 OMAP4_GPIO_SYSCONFIG);
1823 __raw_writel(0x00000000, bank->base +
1824 OMAP4_GPIO_DEBOUNCENABLE);
1825 /* Initialize interface clock ungated, module enabled */
1826 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1827 } else {
1828 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1829 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1830 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1831 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1832
1833 /* Initialize interface clock ungated, module enabled */
1834 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1835 }
1836 if (i < ARRAY_SIZE(non_wakeup_gpios))
1837 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1838 gpio_count = 32;
1839 }
1840 #endif
1841
1842 bank->mod_usage = 0;
1843 /* REVISIT eventually switch from OMAP-specific gpio structs
1844 * over to the generic ones
1845 */
1846 bank->chip.request = omap_gpio_request;
1847 bank->chip.free = omap_gpio_free;
1848 bank->chip.direction_input = gpio_input;
1849 bank->chip.get = gpio_get;
1850 bank->chip.direction_output = gpio_output;
1851 bank->chip.set = gpio_set;
1852 bank->chip.to_irq = gpio_2irq;
1853 if (bank_is_mpuio(bank)) {
1854 bank->chip.label = "mpuio";
1855 #ifdef CONFIG_ARCH_OMAP16XX
1856 bank->chip.dev = &omap_mpuio_device.dev;
1857 #endif
1858 bank->chip.base = OMAP_MPUIO(0);
1859 } else {
1860 bank->chip.label = "gpio";
1861 bank->chip.base = gpio;
1862 gpio += gpio_count;
1863 }
1864 bank->chip.ngpio = gpio_count;
1865
1866 gpiochip_add(&bank->chip);
1867
1868 for (j = bank->virtual_irq_start;
1869 j < bank->virtual_irq_start + gpio_count; j++) {
1870 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1871 set_irq_chip_data(j, bank);
1872 if (bank_is_mpuio(bank))
1873 set_irq_chip(j, &mpuio_irq_chip);
1874 else
1875 set_irq_chip(j, &gpio_irq_chip);
1876 set_irq_handler(j, handle_simple_irq);
1877 set_irq_flags(j, IRQF_VALID);
1878 }
1879 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1880 set_irq_data(bank->irq, bank);
1881
1882 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1883 sprintf(clk_name, "gpio%d_dbck", i + 1);
1884 bank->dbck = clk_get(NULL, clk_name);
1885 if (IS_ERR(bank->dbck))
1886 printk(KERN_ERR "Could not get %s\n", clk_name);
1887 }
1888 }
1889
1890 /* Enable system clock for GPIO module.
1891 * The CAM_CLK_CTRL *is* really the right place. */
1892 if (cpu_is_omap16xx())
1893 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1894
1895 /* Enable autoidle for the OCP interface */
1896 if (cpu_is_omap24xx())
1897 omap_writel(1 << 0, 0x48019010);
1898 if (cpu_is_omap34xx())
1899 omap_writel(1 << 0, 0x48306814);
1900
1901 omap_gpio_show_rev();
1902
1903 return 0;
1904 }
1905
1906 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1907 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1908 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1909 {
1910 int i;
1911
1912 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1913 return 0;
1914
1915 for (i = 0; i < gpio_bank_count; i++) {
1916 struct gpio_bank *bank = &gpio_bank[i];
1917 void __iomem *wake_status;
1918 void __iomem *wake_clear;
1919 void __iomem *wake_set;
1920 unsigned long flags;
1921
1922 switch (bank->method) {
1923 #ifdef CONFIG_ARCH_OMAP16XX
1924 case METHOD_GPIO_1610:
1925 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1926 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1927 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1928 break;
1929 #endif
1930 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1931 case METHOD_GPIO_24XX:
1932 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1933 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1934 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1935 break;
1936 #endif
1937 #ifdef CONFIG_ARCH_OMAP4
1938 case METHOD_GPIO_24XX:
1939 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1940 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1941 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1942 break;
1943 #endif
1944 default:
1945 continue;
1946 }
1947
1948 spin_lock_irqsave(&bank->lock, flags);
1949 bank->saved_wakeup = __raw_readl(wake_status);
1950 __raw_writel(0xffffffff, wake_clear);
1951 __raw_writel(bank->suspend_wakeup, wake_set);
1952 spin_unlock_irqrestore(&bank->lock, flags);
1953 }
1954
1955 return 0;
1956 }
1957
1958 static int omap_gpio_resume(struct sys_device *dev)
1959 {
1960 int i;
1961
1962 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1963 return 0;
1964
1965 for (i = 0; i < gpio_bank_count; i++) {
1966 struct gpio_bank *bank = &gpio_bank[i];
1967 void __iomem *wake_clear;
1968 void __iomem *wake_set;
1969 unsigned long flags;
1970
1971 switch (bank->method) {
1972 #ifdef CONFIG_ARCH_OMAP16XX
1973 case METHOD_GPIO_1610:
1974 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1975 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1976 break;
1977 #endif
1978 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1979 case METHOD_GPIO_24XX:
1980 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1981 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1982 break;
1983 #endif
1984 #ifdef CONFIG_ARCH_OMAP4
1985 case METHOD_GPIO_24XX:
1986 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1987 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1988 break;
1989 #endif
1990 default:
1991 continue;
1992 }
1993
1994 spin_lock_irqsave(&bank->lock, flags);
1995 __raw_writel(0xffffffff, wake_clear);
1996 __raw_writel(bank->saved_wakeup, wake_set);
1997 spin_unlock_irqrestore(&bank->lock, flags);
1998 }
1999
2000 return 0;
2001 }
2002
2003 static struct sysdev_class omap_gpio_sysclass = {
2004 .name = "gpio",
2005 .suspend = omap_gpio_suspend,
2006 .resume = omap_gpio_resume,
2007 };
2008
2009 static struct sys_device omap_gpio_device = {
2010 .id = 0,
2011 .cls = &omap_gpio_sysclass,
2012 };
2013
2014 #endif
2015
2016 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
2017 defined(CONFIG_ARCH_OMAP4)
2018
2019 static int workaround_enabled;
2020
2021 void omap2_gpio_prepare_for_retention(void)
2022 {
2023 int i, c = 0;
2024
2025 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
2026 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
2027 for (i = 0; i < gpio_bank_count; i++) {
2028 struct gpio_bank *bank = &gpio_bank[i];
2029 u32 l1, l2;
2030
2031 if (!(bank->enabled_non_wakeup_gpios))
2032 continue;
2033 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2034 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2035 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2036 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2037 #endif
2038 #ifdef CONFIG_ARCH_OMAP4
2039 bank->saved_datain = __raw_readl(bank->base +
2040 OMAP4_GPIO_DATAIN);
2041 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
2042 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
2043 #endif
2044 bank->saved_fallingdetect = l1;
2045 bank->saved_risingdetect = l2;
2046 l1 &= ~bank->enabled_non_wakeup_gpios;
2047 l2 &= ~bank->enabled_non_wakeup_gpios;
2048 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2049 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2050 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
2051 #endif
2052 #ifdef CONFIG_ARCH_OMAP4
2053 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2054 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2055 #endif
2056 c++;
2057 }
2058 if (!c) {
2059 workaround_enabled = 0;
2060 return;
2061 }
2062 workaround_enabled = 1;
2063 }
2064
2065 void omap2_gpio_resume_after_retention(void)
2066 {
2067 int i;
2068
2069 if (!workaround_enabled)
2070 return;
2071 for (i = 0; i < gpio_bank_count; i++) {
2072 struct gpio_bank *bank = &gpio_bank[i];
2073 u32 l, gen, gen0, gen1;
2074
2075 if (!(bank->enabled_non_wakeup_gpios))
2076 continue;
2077 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2078 __raw_writel(bank->saved_fallingdetect,
2079 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2080 __raw_writel(bank->saved_risingdetect,
2081 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2082 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2083 #endif
2084 #ifdef CONFIG_ARCH_OMAP4
2085 __raw_writel(bank->saved_fallingdetect,
2086 bank->base + OMAP4_GPIO_FALLINGDETECT);
2087 __raw_writel(bank->saved_risingdetect,
2088 bank->base + OMAP4_GPIO_RISINGDETECT);
2089 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2090 #endif
2091 /* Check if any of the non-wakeup interrupt GPIOs have changed
2092 * state. If so, generate an IRQ by software. This is
2093 * horribly racy, but it's the best we can do to work around
2094 * this silicon bug. */
2095 l ^= bank->saved_datain;
2096 l &= bank->non_wakeup_gpios;
2097
2098 /*
2099 * No need to generate IRQs for the rising edge for gpio IRQs
2100 * configured with falling edge only; and vice versa.
2101 */
2102 gen0 = l & bank->saved_fallingdetect;
2103 gen0 &= bank->saved_datain;
2104
2105 gen1 = l & bank->saved_risingdetect;
2106 gen1 &= ~(bank->saved_datain);
2107
2108 /* FIXME: Consider GPIO IRQs with level detections properly! */
2109 gen = l & (~(bank->saved_fallingdetect) &
2110 ~(bank->saved_risingdetect));
2111 /* Consider all GPIO IRQs needed to be updated */
2112 gen |= gen0 | gen1;
2113
2114 if (gen) {
2115 u32 old0, old1;
2116 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2117 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2118 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2119 __raw_writel(old0 | gen, bank->base +
2120 OMAP24XX_GPIO_LEVELDETECT0);
2121 __raw_writel(old1 | gen, bank->base +
2122 OMAP24XX_GPIO_LEVELDETECT1);
2123 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2124 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2125 #endif
2126 #ifdef CONFIG_ARCH_OMAP4
2127 old0 = __raw_readl(bank->base +
2128 OMAP4_GPIO_LEVELDETECT0);
2129 old1 = __raw_readl(bank->base +
2130 OMAP4_GPIO_LEVELDETECT1);
2131 __raw_writel(old0 | l, bank->base +
2132 OMAP4_GPIO_LEVELDETECT0);
2133 __raw_writel(old1 | l, bank->base +
2134 OMAP4_GPIO_LEVELDETECT1);
2135 __raw_writel(old0, bank->base +
2136 OMAP4_GPIO_LEVELDETECT0);
2137 __raw_writel(old1, bank->base +
2138 OMAP4_GPIO_LEVELDETECT1);
2139 #endif
2140 }
2141 }
2142
2143 }
2144
2145 #endif
2146
2147 #ifdef CONFIG_ARCH_OMAP34XX
2148 /* save the registers of bank 2-6 */
2149 void omap_gpio_save_context(void)
2150 {
2151 int i;
2152
2153 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2154 for (i = 1; i < gpio_bank_count; i++) {
2155 struct gpio_bank *bank = &gpio_bank[i];
2156 gpio_context[i].sysconfig =
2157 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2158 gpio_context[i].irqenable1 =
2159 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2160 gpio_context[i].irqenable2 =
2161 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2162 gpio_context[i].wake_en =
2163 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2164 gpio_context[i].ctrl =
2165 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2166 gpio_context[i].oe =
2167 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2168 gpio_context[i].leveldetect0 =
2169 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2170 gpio_context[i].leveldetect1 =
2171 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2172 gpio_context[i].risingdetect =
2173 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2174 gpio_context[i].fallingdetect =
2175 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2176 gpio_context[i].dataout =
2177 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2178 gpio_context[i].setwkuena =
2179 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2180 gpio_context[i].setdataout =
2181 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2182 }
2183 }
2184
2185 /* restore the required registers of bank 2-6 */
2186 void omap_gpio_restore_context(void)
2187 {
2188 int i;
2189
2190 for (i = 1; i < gpio_bank_count; i++) {
2191 struct gpio_bank *bank = &gpio_bank[i];
2192 __raw_writel(gpio_context[i].sysconfig,
2193 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2194 __raw_writel(gpio_context[i].irqenable1,
2195 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2196 __raw_writel(gpio_context[i].irqenable2,
2197 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2198 __raw_writel(gpio_context[i].wake_en,
2199 bank->base + OMAP24XX_GPIO_WAKE_EN);
2200 __raw_writel(gpio_context[i].ctrl,
2201 bank->base + OMAP24XX_GPIO_CTRL);
2202 __raw_writel(gpio_context[i].oe,
2203 bank->base + OMAP24XX_GPIO_OE);
2204 __raw_writel(gpio_context[i].leveldetect0,
2205 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2206 __raw_writel(gpio_context[i].leveldetect1,
2207 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2208 __raw_writel(gpio_context[i].risingdetect,
2209 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2210 __raw_writel(gpio_context[i].fallingdetect,
2211 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2212 __raw_writel(gpio_context[i].dataout,
2213 bank->base + OMAP24XX_GPIO_DATAOUT);
2214 __raw_writel(gpio_context[i].setwkuena,
2215 bank->base + OMAP24XX_GPIO_SETWKUENA);
2216 __raw_writel(gpio_context[i].setdataout,
2217 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2218 }
2219 }
2220 #endif
2221
2222 /*
2223 * This may get called early from board specific init
2224 * for boards that have interrupts routed via FPGA.
2225 */
2226 int __init omap_gpio_init(void)
2227 {
2228 if (!initialized)
2229 return _omap_gpio_init();
2230 else
2231 return 0;
2232 }
2233
2234 static int __init omap_gpio_sysinit(void)
2235 {
2236 int ret = 0;
2237
2238 if (!initialized)
2239 ret = _omap_gpio_init();
2240
2241 mpuio_init();
2242
2243 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2244 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2245 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2246 if (ret == 0) {
2247 ret = sysdev_class_register(&omap_gpio_sysclass);
2248 if (ret == 0)
2249 ret = sysdev_register(&omap_gpio_device);
2250 }
2251 }
2252 #endif
2253
2254 return ret;
2255 }
2256
2257 arch_initcall(omap_gpio_sysinit);
2258
2259
2260 #ifdef CONFIG_DEBUG_FS
2261
2262 #include <linux/debugfs.h>
2263 #include <linux/seq_file.h>
2264
2265 static int dbg_gpio_show(struct seq_file *s, void *unused)
2266 {
2267 unsigned i, j, gpio;
2268
2269 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2270 struct gpio_bank *bank = gpio_bank + i;
2271 unsigned bankwidth = 16;
2272 u32 mask = 1;
2273
2274 if (bank_is_mpuio(bank))
2275 gpio = OMAP_MPUIO(0);
2276 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2277 bankwidth = 32;
2278
2279 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2280 unsigned irq, value, is_in, irqstat;
2281 const char *label;
2282
2283 label = gpiochip_is_requested(&bank->chip, j);
2284 if (!label)
2285 continue;
2286
2287 irq = bank->virtual_irq_start + j;
2288 value = gpio_get_value(gpio);
2289 is_in = gpio_is_input(bank, mask);
2290
2291 if (bank_is_mpuio(bank))
2292 seq_printf(s, "MPUIO %2d ", j);
2293 else
2294 seq_printf(s, "GPIO %3d ", gpio);
2295 seq_printf(s, "(%-20.20s): %s %s",
2296 label,
2297 is_in ? "in " : "out",
2298 value ? "hi" : "lo");
2299
2300 /* FIXME for at least omap2, show pullup/pulldown state */
2301
2302 irqstat = irq_desc[irq].status;
2303 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2304 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2305 if (is_in && ((bank->suspend_wakeup & mask)
2306 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2307 char *trigger = NULL;
2308
2309 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2310 case IRQ_TYPE_EDGE_FALLING:
2311 trigger = "falling";
2312 break;
2313 case IRQ_TYPE_EDGE_RISING:
2314 trigger = "rising";
2315 break;
2316 case IRQ_TYPE_EDGE_BOTH:
2317 trigger = "bothedge";
2318 break;
2319 case IRQ_TYPE_LEVEL_LOW:
2320 trigger = "low";
2321 break;
2322 case IRQ_TYPE_LEVEL_HIGH:
2323 trigger = "high";
2324 break;
2325 case IRQ_TYPE_NONE:
2326 trigger = "(?)";
2327 break;
2328 }
2329 seq_printf(s, ", irq-%d %-8s%s",
2330 irq, trigger,
2331 (bank->suspend_wakeup & mask)
2332 ? " wakeup" : "");
2333 }
2334 #endif
2335 seq_printf(s, "\n");
2336 }
2337
2338 if (bank_is_mpuio(bank)) {
2339 seq_printf(s, "\n");
2340 gpio = 0;
2341 }
2342 }
2343 return 0;
2344 }
2345
2346 static int dbg_gpio_open(struct inode *inode, struct file *file)
2347 {
2348 return single_open(file, dbg_gpio_show, &inode->i_private);
2349 }
2350
2351 static const struct file_operations debug_fops = {
2352 .open = dbg_gpio_open,
2353 .read = seq_read,
2354 .llseek = seq_lseek,
2355 .release = single_release,
2356 };
2357
2358 static int __init omap_gpio_debuginit(void)
2359 {
2360 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2361 NULL, NULL, &debug_fops);
2362 return 0;
2363 }
2364 late_initcall(omap_gpio_debuginit);
2365 #endif
Linux with added FPC-III support