arch/arm/plat-omap/include/plat/omap850.h

   1 /* arch/arm/plat-omap/include/mach/omap850.h
   2  *
   3  * Hardware definitions for TI OMAP850 processor.
   4  *
   5  * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  13  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  15  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  16  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  18  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  20  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the  GNU General Public License along
  24  * with this program; if not, write  to the Free Software Foundation, Inc.,
  25  * 675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27
  28 #ifndef __ASM_ARCH_OMAP850_H
  29 #define __ASM_ARCH_OMAP850_H
  30
  31 /*
  32  * ----------------------------------------------------------------------------
  33  * Base addresses
  34  * ----------------------------------------------------------------------------
  35  */
  36
  37 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
  38
  39 #define OMAP850_DSP_BASE        0xE0000000
  40 #define OMAP850_DSP_SIZE        0x50000
  41 #define OMAP850_DSP_START       0xE0000000
  42
  43 #define OMAP850_DSPREG_BASE     0xE1000000
  44 #define OMAP850_DSPREG_SIZE     SZ_128K
  45 #define OMAP850_DSPREG_START    0xE1000000
  46
  47 /*
  48  * ----------------------------------------------------------------------------
  49  * OMAP850 specific configuration registers
  50  * ----------------------------------------------------------------------------
  51  */
  52 #define OMAP850_CONFIG_BASE     0xfffe1000
  53 #define OMAP850_IO_CONF_0       0xfffe1070
  54 #define OMAP850_IO_CONF_1       0xfffe1074
  55 #define OMAP850_IO_CONF_2       0xfffe1078
  56 #define OMAP850_IO_CONF_3       0xfffe107c
  57 #define OMAP850_IO_CONF_4       0xfffe1080
  58 #define OMAP850_IO_CONF_5       0xfffe1084
  59 #define OMAP850_IO_CONF_6       0xfffe1088
  60 #define OMAP850_IO_CONF_7       0xfffe108c
  61 #define OMAP850_IO_CONF_8       0xfffe1090
  62 #define OMAP850_IO_CONF_9       0xfffe1094
  63 #define OMAP850_IO_CONF_10      0xfffe1098
  64 #define OMAP850_IO_CONF_11      0xfffe109c
  65 #define OMAP850_IO_CONF_12      0xfffe10a0
  66 #define OMAP850_IO_CONF_13      0xfffe10a4
  67
  68 #define OMAP850_MODE_1          0xfffe1010
  69 #define OMAP850_MODE_2          0xfffe1014
  70
  71 /* CSMI specials: in terms of base + offset */
  72 #define OMAP850_MODE2_OFFSET    0x14
  73
  74 /*
  75  * ----------------------------------------------------------------------------
  76  * OMAP850 traffic controller configuration registers
  77  * ----------------------------------------------------------------------------
  78  */
  79 #define OMAP850_FLASH_CFG_0     0xfffecc10
  80 #define OMAP850_FLASH_ACFG_0    0xfffecc50
  81 #define OMAP850_FLASH_CFG_1     0xfffecc14
  82 #define OMAP850_FLASH_ACFG_1    0xfffecc54
  83
  84 /*
  85  * ----------------------------------------------------------------------------
  86  * OMAP850 DSP control registers
  87  * ----------------------------------------------------------------------------
  88  */
  89 #define OMAP850_ICR_BASE        0xfffbb800
  90 #define OMAP850_DSP_M_CTL       0xfffbb804
  91 #define OMAP850_DSP_MMU_BASE    0xfffed200
  92
  93 /*
  94  * ----------------------------------------------------------------------------
  95  * OMAP850 PCC_UPLD configuration registers
  96  * ----------------------------------------------------------------------------
  97  */
  98 #define OMAP850_PCC_UPLD_CTRL_BASE      (0xfffe0900)
  99 #define OMAP850_PCC_UPLD_CTRL           (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
 100
 101 #endif /*  __ASM_ARCH_OMAP850_H */
 102