arch/arm/plat-omap/include/plat/powerdomain.h

   1 /*
   2  * OMAP2/3 powerdomain control
   3  *
   4  * Copyright (C) 2007-8 Texas Instruments, Inc.
   5  * Copyright (C) 2007-8 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
  15 #define ASM_ARM_ARCH_OMAP_POWERDOMAIN
  16
  17 #include <linux/types.h>
  18 #include <linux/list.h>
  19
  20 #include <asm/atomic.h>
  21
  22 #include <plat/cpu.h>
  23
  24
  25 /* Powerdomain basic power states */
  26 #define PWRDM_POWER_OFF         0x0
  27 #define PWRDM_POWER_RET         0x1
  28 #define PWRDM_POWER_INACTIVE    0x2
  29 #define PWRDM_POWER_ON          0x3
  30
  31 #define PWRDM_MAX_PWRSTS        4
  32
  33 /* Powerdomain allowable state bitfields */
  34 #define PWRSTS_OFF_ON           ((1 << PWRDM_POWER_OFF) | \
  35                                  (1 << PWRDM_POWER_ON))
  36
  37 #define PWRSTS_OFF_RET          ((1 << PWRDM_POWER_OFF) | \
  38                                  (1 << PWRDM_POWER_RET))
  39
  40 #define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
  41
  42
  43 /* Powerdomain flags */
  44 #define PWRDM_HAS_HDWR_SAR      (1 << 0) /* hardware save-and-restore support */
  45 #define PWRDM_HAS_MPU_QUIRK     (1 << 1) /* MPU pwr domain has MEM bank 0 bits
  46                                           * in MEM bank 1 position. This is
  47                                           * true for OMAP3430
  48                                           */
  49
  50 /*
  51  * Number of memory banks that are power-controllable.  On OMAP3430, the
  52  * maximum is 4.
  53  */
  54 #define PWRDM_MAX_MEM_BANKS     4
  55
  56 /*
  57  * Maximum number of clockdomains that can be associated with a powerdomain.
  58  * CORE powerdomain on OMAP3 is the worst case
  59  */
  60 #define PWRDM_MAX_CLKDMS        4
  61
  62 /* XXX A completely arbitrary number. What is reasonable here? */
  63 #define PWRDM_TRANSITION_BAILOUT 100000
  64
  65 struct clockdomain;
  66 struct powerdomain;
  67
  68 /* Encodes dependencies between powerdomains - statically defined */
  69 struct pwrdm_dep {
  70
  71         /* Powerdomain name */
  72         const char *pwrdm_name;
  73
  74         /* Powerdomain pointer - resolved by the powerdomain code */
  75         struct powerdomain *pwrdm;
  76
  77         /* Flags to mark OMAP chip restrictions, etc. */
  78         const struct omap_chip_id omap_chip;
  79
  80 };
  81
  82 struct powerdomain {
  83
  84         /* Powerdomain name */
  85         const char *name;
  86
  87         /* the address offset from CM_BASE/PRM_BASE */
  88         const s16 prcm_offs;
  89
  90         /* Used to represent the OMAP chip types containing this pwrdm */
  91         const struct omap_chip_id omap_chip;
  92
  93         /* Powerdomains that can be told to wake this powerdomain up */
  94         struct pwrdm_dep *wkdep_srcs;
  95
  96         /* Powerdomains that can be told to keep this pwrdm from inactivity */
  97         struct pwrdm_dep *sleepdep_srcs;
  98
  99         /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
 100         const u8 dep_bit;
 101
 102         /* Possible powerdomain power states */
 103         const u8 pwrsts;
 104
 105         /* Possible logic power states when pwrdm in RETENTION */
 106         const u8 pwrsts_logic_ret;
 107
 108         /* Powerdomain flags */
 109         const u8 flags;
 110
 111         /* Number of software-controllable memory banks in this powerdomain */
 112         const u8 banks;
 113
 114         /* Possible memory bank pwrstates when pwrdm in RETENTION */
 115         const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
 116
 117         /* Possible memory bank pwrstates when pwrdm is ON */
 118         const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
 119
 120         /* Clockdomains in this powerdomain */
 121         struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
 122
 123         struct list_head node;
 124
 125         int state;
 126         unsigned state_counter[PWRDM_MAX_PWRSTS];
 127
 128 #ifdef CONFIG_PM_DEBUG
 129         s64 timer;
 130         s64 state_timer[PWRDM_MAX_PWRSTS];
 131 #endif
 132 };
 133
 134
 135 void pwrdm_init(struct powerdomain **pwrdm_list);
 136
 137 int pwrdm_register(struct powerdomain *pwrdm);
 138 int pwrdm_unregister(struct powerdomain *pwrdm);
 139 struct powerdomain *pwrdm_lookup(const char *name);
 140
 141 int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
 142                         void *user);
 143 int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
 144                         void *user);
 145
 146 int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
 147 int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
 148 int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
 149                          int (*fn)(struct powerdomain *pwrdm,
 150                                    struct clockdomain *clkdm));
 151
 152 int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
 153 int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
 154 int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
 155 int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
 156 int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
 157 int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
 158
 159 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
 160
 161 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
 162 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
 163 int pwrdm_read_pwrst(struct powerdomain *pwrdm);
 164 int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
 165 int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
 166
 167 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
 168 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
 169 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
 170
 171 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
 172 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
 173 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 174 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 175
 176 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
 177 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
 178 bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
 179
 180 int pwrdm_wait_transition(struct powerdomain *pwrdm);
 181
 182 int pwrdm_state_switch(struct powerdomain *pwrdm);
 183 int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
 184 int pwrdm_pre_transition(void);
 185 int pwrdm_post_transition(void);
 186
 187 #endif