arch/arm/plat-s3c24xx/s3c2410-iotiming.c

   1 /* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
   2  *
   3  * Copyright (c) 2006-2009 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/errno.h>
  17 #include <linux/cpufreq.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/io.h>
  20
  21 #include <mach/map.h>
  22 #include <mach/regs-mem.h>
  23 #include <mach/regs-clock.h>
  24
  25 #include <plat/cpu-freq-core.h>
  26
  27 #define print_ns(x) ((x) / 10), ((x) % 10)
  28
  29 /**
  30  * s3c2410_print_timing - print bank timing data for debug purposes
  31  * @pfx: The prefix to put on the output
  32  * @timings: The timing inforamtion to print.
  33 */
  34 static void s3c2410_print_timing(const char *pfx,
  35                                  struct s3c_iotimings *timings)
  36 {
  37         struct s3c2410_iobank_timing *bt;
  38         int bank;
  39
  40         for (bank = 0; bank < MAX_BANKS; bank++) {
  41                 bt = timings->bank[bank].io_2410;
  42                 if (!bt)
  43                         continue;
  44
  45                 printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, "
  46                        "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank,
  47                        print_ns(bt->tacs),
  48                        print_ns(bt->tcos),
  49                        print_ns(bt->tacc),
  50                        print_ns(bt->tcoh),
  51                        print_ns(bt->tcah));
  52         }
  53 }
  54
  55 /**
  56  * bank_reg - convert bank number to pointer to the control register.
  57  * @bank: The IO bank number.
  58  */
  59 static inline void __iomem *bank_reg(unsigned int bank)
  60 {
  61         return S3C2410_BANKCON0 + (bank << 2);
  62 }
  63
  64 /**
  65  * bank_is_io - test whether bank is used for IO
  66  * @bankcon: The bank control register.
  67  *
  68  * This is a simplistic test to see if any BANKCON[x] is not an IO
  69  * bank. It currently does not take into account whether BWSCON has
  70  * an illegal width-setting in it, or if the pin connected to nCS[x]
  71  * is actually being handled as a chip-select.
  72  */
  73 static inline int bank_is_io(unsigned long bankcon)
  74 {
  75         return !(bankcon & S3C2410_BANKCON_SDRAM);
  76 }
  77
  78 /**
  79  * to_div - convert cycle time to divisor
  80  * @cyc: The cycle time, in 10ths of nanoseconds.
  81  * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
  82  *
  83  * Convert the given cycle time into the divisor to use to obtain it from
  84  * HCLK.
  85 */
  86 static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns)
  87 {
  88         if (cyc == 0)
  89                 return 0;
  90
  91         return DIV_ROUND_UP(cyc, hclk_tns);
  92 }
  93
  94 /**
  95  * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
  96  * @cyc: The cycle time, in 10ths of nanoseconds.
  97  * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
  98  * @v: Pointer to register to alter.
  99  * @shift: The shift to get to the control bits.
 100  *
 101  * Calculate the divisor, and turn it into the correct control bits to
 102  * set in the result, @v.
 103  */
 104 static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns,
 105                               unsigned long *v, int shift)
 106 {
 107         unsigned int div = to_div(cyc, hclk_tns);
 108         unsigned long val;
 109
 110         s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n",
 111                        __func__, cyc, hclk_tns, shift, div);
 112
 113         switch (div) {
 114         case 0:
 115                 val = 0;
 116                 break;
 117         case 1:
 118                 val = 1;
 119                 break;
 120         case 2:
 121                 val = 2;
 122                 break;
 123         case 3:
 124         case 4:
 125                 val = 3;
 126                 break;
 127         default:
 128                 return -1;
 129         }
 130
 131         *v |= val << shift;
 132         return 0;
 133 }
 134
 135 int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
 136 {
 137         /* Currently no support for Tacp calculations. */
 138         return 0;
 139 }
 140
 141 /**
 142  * calc_tacc - calculate divisor control for tacc.
 143  * @cyc: The cycle time, in 10ths of nanoseconds.
 144  * @nwait_en: IS nWAIT enabled for this bank.
 145  * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
 146  * @v: Pointer to register to alter.
 147  *
 148  * Calculate the divisor control for tACC, taking into account whether
 149  * the bank has nWAIT enabled. The result is used to modify the value
 150  * pointed to by @v.
 151 */
 152 static int calc_tacc(unsigned int cyc, int nwait_en,
 153                      unsigned long hclk_tns, unsigned long *v)
 154 {
 155         unsigned int div = to_div(cyc, hclk_tns);
 156         unsigned long val;
 157
 158         s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n",
 159                        __func__, cyc, nwait_en, hclk_tns, div);
 160
 161         /* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */
 162         if (nwait_en && div < 4)
 163                 div = 4;
 164
 165         switch (div) {
 166         case 0:
 167                 val = 0;
 168                 break;
 169
 170         case 1:
 171         case 2:
 172         case 3:
 173         case 4:
 174                 val = div - 1;
 175                 break;
 176
 177         case 5:
 178         case 6:
 179                 val = 4;
 180                 break;
 181
 182         case 7:
 183         case 8:
 184                 val = 5;
 185                 break;
 186
 187         case 9:
 188         case 10:
 189                 val = 6;
 190                 break;
 191
 192         case 11:
 193         case 12:
 194         case 13:
 195         case 14:
 196                 val = 7;
 197                 break;
 198
 199         default:
 200                 return -1;
 201         }
 202
 203         *v |= val << 8;
 204         return 0;
 205 }
 206
 207 /**
 208  * s3c2410_calc_bank - calculate bank timing infromation
 209  * @cfg: The configuration we need to calculate for.
 210  * @bt: The bank timing information.
 211  *
 212  * Given the cycle timine for a bank @bt, calculate the new BANKCON
 213  * setting for the @cfg timing. This updates the timing information
 214  * ready for the cpu frequency change.
 215  */
 216 static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg,
 217                              struct s3c2410_iobank_timing *bt)
 218 {
 219         unsigned long hclk = cfg->freq.hclk_tns;
 220         unsigned long res;
 221         int ret;
 222
 223         res  = bt->bankcon;
 224         res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16);
 225
 226         /* tacp: 2,3,4,5 */
 227         /* tcah: 0,1,2,4 */
 228         /* tcoh: 0,1,2,4 */
 229         /* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */
 230         /* tcos: 0,1,2,4 */
 231         /* tacs: 0,1,2,4 */
 232
 233         ret  = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT);
 234         ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT);
 235         ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT);
 236         ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT);
 237
 238         if (ret)
 239                 return -EINVAL;
 240
 241         ret |= calc_tacp(bt->tacp, hclk, &res);
 242         ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res);
 243
 244         if (ret)
 245                 return -EINVAL;
 246
 247         bt->bankcon = res;
 248         return 0;
 249 }
 250
 251 static unsigned int tacc_tab[] = {
 252         [0]     = 1,
 253         [1]     = 2,
 254         [2]     = 3,
 255         [3]     = 4,
 256         [4]     = 6,
 257         [5]     = 9,
 258         [6]     = 10,
 259         [7]     = 14,
 260 };
 261
 262 /**
 263  * get_tacc - turn tACC value into cycle time
 264  * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
 265  * @val: The bank timing register value, shifed down.
 266  */
 267 static unsigned int get_tacc(unsigned long hclk_tns,
 268                              unsigned long val)
 269 {
 270         val &= 7;
 271         return hclk_tns * tacc_tab[val];
 272 }
 273
 274 /**
 275  * get_0124 - turn 0/1/2/4 divider into cycle time
 276  * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
 277  * @val: The bank timing register value, shifed down.
 278  */
 279 static unsigned int get_0124(unsigned long hclk_tns,
 280                              unsigned long val)
 281 {
 282         val &= 3;
 283         return hclk_tns * ((val == 3) ? 4 : val);
 284 }
 285
 286 /**
 287  * s3c2410_iotiming_getbank - turn BANKCON into cycle time information
 288  * @cfg: The frequency configuration
 289  * @bt: The bank timing to fill in (uses cached BANKCON)
 290  *
 291  * Given the BANKCON setting in @bt and the current frequency settings
 292  * in @cfg, update the cycle timing information.
 293  */
 294 void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
 295                               struct s3c2410_iobank_timing *bt)
 296 {
 297         unsigned long bankcon = bt->bankcon;
 298         unsigned long hclk = cfg->freq.hclk_tns;
 299
 300         bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
 301         bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
 302         bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
 303         bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
 304         bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
 305 }
 306
 307 /**
 308  * s3c2410_iotiming_debugfs - debugfs show io bank timing information
 309  * @seq: The seq_file to write output to using seq_printf().
 310  * @cfg: The current configuration.
 311  * @iob: The IO bank information to decode.
 312  */
 313 void s3c2410_iotiming_debugfs(struct seq_file *seq,
 314                               struct s3c_cpufreq_config *cfg,
 315                               union s3c_iobank *iob)
 316 {
 317         struct s3c2410_iobank_timing *bt = iob->io_2410;
 318         unsigned long bankcon = bt->bankcon;
 319         unsigned long hclk = cfg->freq.hclk_tns;
 320         unsigned int tacs;
 321         unsigned int tcos;
 322         unsigned int tacc;
 323         unsigned int tcoh;
 324         unsigned int tcah;
 325
 326         seq_printf(seq, "BANKCON=0x%08lx\n", bankcon);
 327
 328         tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
 329         tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
 330         tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
 331         tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
 332         tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
 333
 334         seq_printf(seq,
 335                    "\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
 336                    print_ns(bt->tacs),
 337                    print_ns(bt->tcos),
 338                    print_ns(bt->tacc),
 339                    print_ns(bt->tcoh),
 340                    print_ns(bt->tcah));
 341
 342         seq_printf(seq,
 343                    "\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
 344                    print_ns(tacs),
 345                    print_ns(tcos),
 346                    print_ns(tacc),
 347                    print_ns(tcoh),
 348                    print_ns(tcah));
 349 }
 350
 351 /**
 352  * s3c2410_iotiming_calc - Calculate bank timing for frequency change.
 353  * @cfg: The frequency configuration
 354  * @iot: The IO timing information to fill out.
 355  *
 356  * Calculate the new values for the banks in @iot based on the new
 357  * frequency information in @cfg. This is then used by s3c2410_iotiming_set()
 358  * to update the timing when necessary.
 359  */
 360 int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
 361                           struct s3c_iotimings *iot)
 362 {
 363         struct s3c2410_iobank_timing *bt;
 364         unsigned long bankcon;
 365         int bank;
 366         int ret;
 367
 368         for (bank = 0; bank < MAX_BANKS; bank++) {
 369                 bankcon = __raw_readl(bank_reg(bank));
 370                 bt = iot->bank[bank].io_2410;
 371
 372                 if (!bt)
 373                         continue;
 374
 375                 bt->bankcon = bankcon;
 376
 377                 ret = s3c2410_calc_bank(cfg, bt);
 378                 if (ret) {
 379                         printk(KERN_ERR "%s: cannot calculate bank %d io\n",
 380                                __func__, bank);
 381                         goto err;
 382                 }
 383
 384                 s3c_freq_iodbg("%s: bank %d: con=%08lx\n",
 385                                __func__, bank, bt->bankcon);
 386         }
 387
 388         return 0;
 389  err:
 390         return ret;
 391 }
 392
 393 /**
 394  * s3c2410_iotiming_set - set the IO timings from the given setup.
 395  * @cfg: The frequency configuration
 396  * @iot: The IO timing information to use.
 397  *
 398  * Set all the currently used IO bank timing information generated
 399  * by s3c2410_iotiming_calc() once the core has validated that all
 400  * the new values are within permitted bounds.
 401  */
 402 void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
 403                           struct s3c_iotimings *iot)
 404 {
 405         struct s3c2410_iobank_timing *bt;
 406         int bank;
 407
 408         /* set the io timings from the specifier */
 409
 410         for (bank = 0; bank < MAX_BANKS; bank++) {
 411                 bt = iot->bank[bank].io_2410;
 412                 if (!bt)
 413                         continue;
 414
 415                 __raw_writel(bt->bankcon, bank_reg(bank));
 416         }
 417 }
 418
 419 /**
 420  * s3c2410_iotiming_get - Get the timing information from current registers.
 421  * @cfg: The frequency configuration
 422  * @timings: The IO timing information to fill out.
 423  *
 424  * Calculate the @timings timing information from the current frequency
 425  * information in @cfg, and the new frequency configur
 426  * through all the IO banks, reading the state and then updating @iot
 427  * as necessary.
 428  *
 429  * This is used at the moment on initialisation to get the current
 430  * configuration so that boards do not have to carry their own setup
 431  * if the timings are correct on initialisation.
 432  */
 433
 434 int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
 435                          struct s3c_iotimings *timings)
 436 {
 437         struct s3c2410_iobank_timing *bt;
 438         unsigned long bankcon;
 439         unsigned long bwscon;
 440         int bank;
 441
 442         bwscon = __raw_readl(S3C2410_BWSCON);
 443
 444         /* look through all banks to see what is currently set. */
 445
 446         for (bank = 0; bank < MAX_BANKS; bank++) {
 447                 bankcon = __raw_readl(bank_reg(bank));
 448
 449                 if (!bank_is_io(bankcon))
 450                         continue;
 451
 452                 s3c_freq_iodbg("%s: bank %d: con %08lx\n",
 453                                __func__, bank, bankcon);
 454
 455                 bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL);
 456                 if (!bt) {
 457                         printk(KERN_ERR "%s: no memory for bank\n", __func__);
 458                         return -ENOMEM;
 459                 }
 460
 461                 /* find out in nWait is enabled for bank. */
 462
 463                 if (bank != 0) {
 464                         unsigned long tmp  = S3C2410_BWSCON_GET(bwscon, bank);
 465                         if (tmp & S3C2410_BWSCON_WS)
 466                                 bt->nwait_en = 1;
 467                 }
 468
 469                 timings->bank[bank].io_2410 = bt;
 470                 bt->bankcon = bankcon;
 471
 472                 s3c2410_iotiming_getbank(cfg, bt);
 473         }
 474
 475         s3c2410_print_timing("get", timings);
 476         return 0;
 477 }