arch/powerpc/platforms/52xx/mpc52xx_pci.c

   1 /*
   2  * PCI code for the Freescale MPC52xx embedded CPU.
   3  *
   4  * Copyright (C) 2006 Secret Lab Technologies Ltd.
   5  *                        Grant Likely <grant.likely@secretlab.ca>
   6  * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2. This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #undef DEBUG
  14
  15 #include <asm/pci.h>
  16 #include <asm/mpc52xx.h>
  17 #include <asm/delay.h>
  18 #include <asm/machdep.h>
  19 #include <linux/kernel.h>
  20
  21
  22 /* ======================================================================== */
  23 /* PCI windows config                                                       */
  24 /* ======================================================================== */
  25
  26 #define MPC52xx_PCI_TARGET_IO   0xf0000000
  27 #define MPC52xx_PCI_TARGET_MEM  0x00000000
  28
  29
  30 /* ======================================================================== */
  31 /* Structures mapping & Defines for PCI Unit                                */
  32 /* ======================================================================== */
  33
  34 #define MPC52xx_PCI_GSCR_BM             0x40000000
  35 #define MPC52xx_PCI_GSCR_PE             0x20000000
  36 #define MPC52xx_PCI_GSCR_SE             0x10000000
  37 #define MPC52xx_PCI_GSCR_XLB2PCI_MASK   0x07000000
  38 #define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT  24
  39 #define MPC52xx_PCI_GSCR_IPG2PCI_MASK   0x00070000
  40 #define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT  16
  41 #define MPC52xx_PCI_GSCR_BME            0x00004000
  42 #define MPC52xx_PCI_GSCR_PEE            0x00002000
  43 #define MPC52xx_PCI_GSCR_SEE            0x00001000
  44 #define MPC52xx_PCI_GSCR_PR             0x00000001
  45
  46
  47 #define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size)       \
  48                 ( ( (proc_ad) & 0xff000000 )                    | \
  49                   ( (((size) - 1) >> 8) & 0x00ff0000 )          | \
  50                   ( ((pci_ad) >> 16) & 0x0000ff00 ) )
  51
  52 #define MPC52xx_PCI_IWCR_PACK(win0,win1,win2)   (((win0) << 24) | \
  53                                                  ((win1) << 16) | \
  54                                                  ((win2) <<  8))
  55
  56 #define MPC52xx_PCI_IWCR_DISABLE        0x0
  57 #define MPC52xx_PCI_IWCR_ENABLE         0x1
  58 #define MPC52xx_PCI_IWCR_READ           0x0
  59 #define MPC52xx_PCI_IWCR_READ_LINE      0x2
  60 #define MPC52xx_PCI_IWCR_READ_MULTI     0x4
  61 #define MPC52xx_PCI_IWCR_MEM            0x0
  62 #define MPC52xx_PCI_IWCR_IO             0x8
  63
  64 #define MPC52xx_PCI_TCR_P               0x01000000
  65 #define MPC52xx_PCI_TCR_LD              0x00010000
  66 #define MPC52xx_PCI_TCR_WCT8            0x00000008
  67
  68 #define MPC52xx_PCI_TBATR_DISABLE       0x0
  69 #define MPC52xx_PCI_TBATR_ENABLE        0x1
  70
  71 struct mpc52xx_pci {
  72         u32     idr;            /* PCI + 0x00 */
  73         u32     scr;            /* PCI + 0x04 */
  74         u32     ccrir;          /* PCI + 0x08 */
  75         u32     cr1;            /* PCI + 0x0C */
  76         u32     bar0;           /* PCI + 0x10 */
  77         u32     bar1;           /* PCI + 0x14 */
  78         u8      reserved1[16];  /* PCI + 0x18 */
  79         u32     ccpr;           /* PCI + 0x28 */
  80         u32     sid;            /* PCI + 0x2C */
  81         u32     erbar;          /* PCI + 0x30 */
  82         u32     cpr;            /* PCI + 0x34 */
  83         u8      reserved2[4];   /* PCI + 0x38 */
  84         u32     cr2;            /* PCI + 0x3C */
  85         u8      reserved3[32];  /* PCI + 0x40 */
  86         u32     gscr;           /* PCI + 0x60 */
  87         u32     tbatr0;         /* PCI + 0x64 */
  88         u32     tbatr1;         /* PCI + 0x68 */
  89         u32     tcr;            /* PCI + 0x6C */
  90         u32     iw0btar;        /* PCI + 0x70 */
  91         u32     iw1btar;        /* PCI + 0x74 */
  92         u32     iw2btar;        /* PCI + 0x78 */
  93         u8      reserved4[4];   /* PCI + 0x7C */
  94         u32     iwcr;           /* PCI + 0x80 */
  95         u32     icr;            /* PCI + 0x84 */
  96         u32     isr;            /* PCI + 0x88 */
  97         u32     arb;            /* PCI + 0x8C */
  98         u8      reserved5[104]; /* PCI + 0x90 */
  99         u32     car;            /* PCI + 0xF8 */
 100         u8      reserved6[4];   /* PCI + 0xFC */
 101 };
 102
 103 /* MPC5200 device tree match tables */
 104 const struct of_device_id mpc52xx_pci_ids[] __initdata = {
 105         { .type = "pci", .compatible = "fsl,mpc5200-pci", },
 106         { .type = "pci", .compatible = "mpc5200-pci", },
 107         {}
 108 };
 109
 110 /* ======================================================================== */
 111 /* PCI configuration acess                                                  */
 112 /* ======================================================================== */
 113
 114 static int
 115 mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 116                                 int offset, int len, u32 *val)
 117 {
 118         struct pci_controller *hose = bus->sysdata;
 119         u32 value;
 120
 121         if (ppc_md.pci_exclude_device)
 122                 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
 123                         return PCIBIOS_DEVICE_NOT_FOUND;
 124
 125         out_be32(hose->cfg_addr,
 126                 (1 << 31) |
 127                 (bus->number << 16) |
 128                 (devfn << 8) |
 129                 (offset & 0xfc));
 130         mb();
 131
 132 #if defined(CONFIG_PPC_MPC5200_BUGFIX)
 133         if (bus->number) {
 134                 /* workaround for the bug 435 of the MPC5200 (L25R);
 135                  * Don't do 32 bits config access during type-1 cycles */
 136                 switch (len) {
 137                       case 1:
 138                         value = in_8(((u8 __iomem *)hose->cfg_data) +
 139                                      (offset & 3));
 140                         break;
 141                       case 2:
 142                         value = in_le16(((u16 __iomem *)hose->cfg_data) +
 143                                         ((offset>>1) & 1));
 144                         break;
 145
 146                       default:
 147                         value = in_le16((u16 __iomem *)hose->cfg_data) |
 148                                 (in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16);
 149                         break;
 150                 }
 151         }
 152         else
 153 #endif
 154         {
 155                 value = in_le32(hose->cfg_data);
 156
 157                 if (len != 4) {
 158                         value >>= ((offset & 0x3) << 3);
 159                         value &= 0xffffffff >> (32 - (len << 3));
 160                 }
 161         }
 162
 163         *val = value;
 164
 165         out_be32(hose->cfg_addr, 0);
 166         mb();
 167
 168         return PCIBIOS_SUCCESSFUL;
 169 }
 170
 171 static int
 172 mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 173                                 int offset, int len, u32 val)
 174 {
 175         struct pci_controller *hose = bus->sysdata;
 176         u32 value, mask;
 177
 178         if (ppc_md.pci_exclude_device)
 179                 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
 180                         return PCIBIOS_DEVICE_NOT_FOUND;
 181
 182         out_be32(hose->cfg_addr,
 183                 (1 << 31) |
 184                 (bus->number << 16) |
 185                 (devfn << 8) |
 186                 (offset & 0xfc));
 187         mb();
 188
 189 #if defined(CONFIG_PPC_MPC5200_BUGFIX)
 190         if (bus->number) {
 191                 /* workaround for the bug 435 of the MPC5200 (L25R);
 192                  * Don't do 32 bits config access during type-1 cycles */
 193                 switch (len) {
 194                       case 1:
 195                         out_8(((u8 __iomem *)hose->cfg_data) +
 196                                 (offset & 3), val);
 197                         break;
 198                       case 2:
 199                         out_le16(((u16 __iomem *)hose->cfg_data) +
 200                                 ((offset>>1) & 1), val);
 201                         break;
 202
 203                       default:
 204                         out_le16((u16 __iomem *)hose->cfg_data,
 205                                 (u16)val);
 206                         out_le16(((u16 __iomem *)hose->cfg_data) + 1,
 207                                 (u16)(val>>16));
 208                         break;
 209                 }
 210         }
 211         else
 212 #endif
 213         {
 214                 if (len != 4) {
 215                         value = in_le32(hose->cfg_data);
 216
 217                         offset = (offset & 0x3) << 3;
 218                         mask = (0xffffffff >> (32 - (len << 3)));
 219                         mask <<= offset;
 220
 221                         value &= ~mask;
 222                         val = value | ((val << offset) & mask);
 223                 }
 224
 225                 out_le32(hose->cfg_data, val);
 226         }
 227         mb();
 228
 229         out_be32(hose->cfg_addr, 0);
 230         mb();
 231
 232         return PCIBIOS_SUCCESSFUL;
 233 }
 234
 235 static struct pci_ops mpc52xx_pci_ops = {
 236         .read  = mpc52xx_pci_read_config,
 237         .write = mpc52xx_pci_write_config
 238 };
 239
 240
 241 /* ======================================================================== */
 242 /* PCI setup                                                                */
 243 /* ======================================================================== */
 244
 245 static void __init
 246 mpc52xx_pci_setup(struct pci_controller *hose,
 247                   struct mpc52xx_pci __iomem *pci_regs)
 248 {
 249         struct resource *res;
 250         u32 tmp;
 251         int iwcr0 = 0, iwcr1 = 0, iwcr2 = 0;
 252
 253         pr_debug("mpc52xx_pci_setup(hose=%p, pci_regs=%p)\n", hose, pci_regs);
 254
 255         /* pci_process_bridge_OF_ranges() found all our addresses for us;
 256          * now store them in the right places */
 257         hose->cfg_addr = &pci_regs->car;
 258         hose->cfg_data = hose->io_base_virt;
 259
 260         /* Control regs */
 261         tmp = in_be32(&pci_regs->scr);
 262         tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 263         out_be32(&pci_regs->scr, tmp);
 264
 265         /* Memory windows */
 266         res = &hose->mem_resources[0];
 267         if (res->flags) {
 268                 pr_debug("mem_resource[0] = "
 269                          "{.start=%llx, .end=%llx, .flags=%llx}\n",
 270                          (unsigned long long)res->start,
 271                          (unsigned long long)res->end,
 272                          (unsigned long long)res->flags);
 273                 out_be32(&pci_regs->iw0btar,
 274                          MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
 275                                   res->end - res->start + 1));
 276                 iwcr0 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM;
 277                 if (res->flags & IORESOURCE_PREFETCH)
 278                         iwcr0 |= MPC52xx_PCI_IWCR_READ_MULTI;
 279                 else
 280                         iwcr0 |= MPC52xx_PCI_IWCR_READ;
 281         }
 282
 283         res = &hose->mem_resources[1];
 284         if (res->flags) {
 285                 pr_debug("mem_resource[1] = {.start=%x, .end=%x, .flags=%lx}\n",
 286                          res->start, res->end, res->flags);
 287                 out_be32(&pci_regs->iw1btar,
 288                          MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
 289                                   res->end - res->start + 1));
 290                 iwcr1 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM;
 291                 if (res->flags & IORESOURCE_PREFETCH)
 292                         iwcr1 |= MPC52xx_PCI_IWCR_READ_MULTI;
 293                 else
 294                         iwcr1 |= MPC52xx_PCI_IWCR_READ;
 295         }
 296
 297         /* IO resources */
 298         res = &hose->io_resource;
 299         if (!res) {
 300                 printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__);
 301                 return;
 302         }
 303         pr_debug(".io_resource={.start=%llx,.end=%llx,.flags=%llx} "
 304                  ".io_base_phys=0x%p\n",
 305                  (unsigned long long)res->start,
 306                  (unsigned long long)res->end,
 307                  (unsigned long long)res->flags, (void*)hose->io_base_phys);
 308         out_be32(&pci_regs->iw2btar,
 309                  MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys,
 310                                                 res->start,
 311                                                 res->end - res->start + 1));
 312         iwcr2 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_IO;
 313
 314         /* Set all the IWCR fields at once; they're in the same reg */
 315         out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(iwcr0, iwcr1, iwcr2));
 316
 317         out_be32(&pci_regs->tbatr0,
 318                 MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO );
 319         out_be32(&pci_regs->tbatr1,
 320                 MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM );
 321
 322         out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD | MPC52xx_PCI_TCR_WCT8);
 323
 324         tmp = in_be32(&pci_regs->gscr);
 325 #if 0
 326         /* Reset the exteral bus ( internal PCI controller is NOT resetted ) */
 327         /* Not necessary and can be a bad thing if for example the bootloader
 328            is displaying a splash screen or ... Just left here for
 329            documentation purpose if anyone need it */
 330         out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR);
 331         udelay(50);
 332 #endif
 333
 334         /* Make sure the PCI bridge is out of reset */
 335         out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR);
 336 }
 337
 338 static void
 339 mpc52xx_pci_fixup_resources(struct pci_dev *dev)
 340 {
 341         int i;
 342
 343         pr_debug("mpc52xx_pci_fixup_resources() %.4x:%.4x\n",
 344                  dev->vendor, dev->device);
 345
 346         /* We don't rely on boot loader for PCI and resets all
 347            devices */
 348         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 349                 struct resource *res = &dev->resource[i];
 350                 if (res->end > res->start) {    /* Only valid resources */
 351                         res->end -= res->start;
 352                         res->start = 0;
 353                         res->flags |= IORESOURCE_UNSET;
 354                 }
 355         }
 356
 357         /* The PCI Host bridge of MPC52xx has a prefetch memory resource
 358            fixed to 1Gb. Doesn't fit in the resource system so we remove it */
 359         if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
 360              (   dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200
 361               || dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200B) ) {
 362                 struct resource *res = &dev->resource[1];
 363                 res->start = res->end = res->flags = 0;
 364         }
 365 }
 366
 367 int __init
 368 mpc52xx_add_bridge(struct device_node *node)
 369 {
 370         int len;
 371         struct mpc52xx_pci __iomem *pci_regs;
 372         struct pci_controller *hose;
 373         const int *bus_range;
 374         struct resource rsrc;
 375
 376         pr_debug("Adding MPC52xx PCI host bridge %s\n", node->full_name);
 377
 378         ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
 379
 380         if (of_address_to_resource(node, 0, &rsrc) != 0) {
 381                 printk(KERN_ERR "Can't get %s resources\n", node->full_name);
 382                 return -EINVAL;
 383         }
 384
 385         bus_range = of_get_property(node, "bus-range", &len);
 386         if (bus_range == NULL || len < 2 * sizeof(int)) {
 387                 printk(KERN_WARNING "Can't get %s bus-range, assume bus 0\n",
 388                        node->full_name);
 389                 bus_range = NULL;
 390         }
 391
 392         /* There are some PCI quirks on the 52xx, register the hook to
 393          * fix them. */
 394         ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources;
 395
 396         /* Alloc and initialize the pci controller.  Values in the device
 397          * tree are needed to configure the 52xx PCI controller.  Rather
 398          * than parse the tree here, let pci_process_bridge_OF_ranges()
 399          * do it for us and extract the values after the fact */
 400         hose = pcibios_alloc_controller(node);
 401         if (!hose)
 402                 return -ENOMEM;
 403
 404         hose->first_busno = bus_range ? bus_range[0] : 0;
 405         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 406
 407         hose->ops = &mpc52xx_pci_ops;
 408
 409         pci_regs = ioremap(rsrc.start, rsrc.end - rsrc.start + 1);
 410         if (!pci_regs)
 411                 return -ENOMEM;
 412
 413         pci_process_bridge_OF_ranges(hose, node, 1);
 414
 415         /* Finish setting up PCI using values obtained by
 416          * pci_proces_bridge_OF_ranges */
 417         mpc52xx_pci_setup(hose, pci_regs);
 418
 419         return 0;
 420 }
 421
 422 void __init mpc52xx_setup_pci(void)
 423 {
 424         struct device_node *pci;
 425
 426         pci = of_find_matching_node(NULL, mpc52xx_pci_ids);
 427         if (!pci)
 428                 return;
 429
 430         mpc52xx_add_bridge(pci);
 431         of_node_put(pci);
 432 }