arch/x86/kernel/smp.c

   1 /*
   2  *      Intel SMP support routines.
   3  *
   4  *      (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
   5  *      (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
   6  *      (c) 2002,2003 Andi Kleen, SuSE Labs.
   7  *
   8  *      i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
   9  *
  10  *      This code is released under the GNU General Public License version 2 or
  11  *      later.
  12  */
  13
  14 #include <linux/init.h>
  15
  16 #include <linux/mm.h>
  17 #include <linux/delay.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/kernel_stat.h>
  20 #include <linux/mc146818rtc.h>
  21 #include <linux/cache.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/cpu.h>
  24
  25 #include <asm/mtrr.h>
  26 #include <asm/tlbflush.h>
  27 #include <asm/mmu_context.h>
  28 #include <asm/proto.h>
  29 #include <mach_ipi.h>
  30 #include <mach_apic.h>
  31 /*
  32  *      Some notes on x86 processor bugs affecting SMP operation:
  33  *
  34  *      Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
  35  *      The Linux implications for SMP are handled as follows:
  36  *
  37  *      Pentium III / [Xeon]
  38  *              None of the E1AP-E3AP errata are visible to the user.
  39  *
  40  *      E1AP.   see PII A1AP
  41  *      E2AP.   see PII A2AP
  42  *      E3AP.   see PII A3AP
  43  *
  44  *      Pentium II / [Xeon]
  45  *              None of the A1AP-A3AP errata are visible to the user.
  46  *
  47  *      A1AP.   see PPro 1AP
  48  *      A2AP.   see PPro 2AP
  49  *      A3AP.   see PPro 7AP
  50  *
  51  *      Pentium Pro
  52  *              None of 1AP-9AP errata are visible to the normal user,
  53  *      except occasional delivery of 'spurious interrupt' as trap #15.
  54  *      This is very rare and a non-problem.
  55  *
  56  *      1AP.    Linux maps APIC as non-cacheable
  57  *      2AP.    worked around in hardware
  58  *      3AP.    fixed in C0 and above steppings microcode update.
  59  *              Linux does not use excessive STARTUP_IPIs.
  60  *      4AP.    worked around in hardware
  61  *      5AP.    symmetric IO mode (normal Linux operation) not affected.
  62  *              'noapic' mode has vector 0xf filled out properly.
  63  *      6AP.    'noapic' mode might be affected - fixed in later steppings
  64  *      7AP.    We do not assume writes to the LVT deassering IRQs
  65  *      8AP.    We do not enable low power mode (deep sleep) during MP bootup
  66  *      9AP.    We do not use mixed mode
  67  *
  68  *      Pentium
  69  *              There is a marginal case where REP MOVS on 100MHz SMP
  70  *      machines with B stepping processors can fail. XXX should provide
  71  *      an L1cache=Writethrough or L1cache=off option.
  72  *
  73  *              B stepping CPUs may hang. There are hardware work arounds
  74  *      for this. We warn about it in case your board doesn't have the work
  75  *      arounds. Basically that's so I can tell anyone with a B stepping
  76  *      CPU and SMP problems "tough".
  77  *
  78  *      Specific items [From Pentium Processor Specification Update]
  79  *
  80  *      1AP.    Linux doesn't use remote read
  81  *      2AP.    Linux doesn't trust APIC errors
  82  *      3AP.    We work around this
  83  *      4AP.    Linux never generated 3 interrupts of the same priority
  84  *              to cause a lost local interrupt.
  85  *      5AP.    Remote read is never used
  86  *      6AP.    not affected - worked around in hardware
  87  *      7AP.    not affected - worked around in hardware
  88  *      8AP.    worked around in hardware - we get explicit CS errors if not
  89  *      9AP.    only 'noapic' mode affected. Might generate spurious
  90  *              interrupts, we log only the first one and count the
  91  *              rest silently.
  92  *      10AP.   not affected - worked around in hardware
  93  *      11AP.   Linux reads the APIC between writes to avoid this, as per
  94  *              the documentation. Make sure you preserve this as it affects
  95  *              the C stepping chips too.
  96  *      12AP.   not affected - worked around in hardware
  97  *      13AP.   not affected - worked around in hardware
  98  *      14AP.   we always deassert INIT during bootup
  99  *      15AP.   not affected - worked around in hardware
 100  *      16AP.   not affected - worked around in hardware
 101  *      17AP.   not affected - worked around in hardware
 102  *      18AP.   not affected - worked around in hardware
 103  *      19AP.   not affected - worked around in BIOS
 104  *
 105  *      If this sounds worrying believe me these bugs are either ___RARE___,
 106  *      or are signal timing bugs worked around in hardware and there's
 107  *      about nothing of note with C stepping upwards.
 108  */
 109
 110 /*
 111  * this function sends a 'reschedule' IPI to another CPU.
 112  * it goes straight through and wastes no time serializing
 113  * anything. Worst case is that we lose a reschedule ...
 114  */
 115 static void native_smp_send_reschedule(int cpu)
 116 {
 117         if (unlikely(cpu_is_offline(cpu))) {
 118                 WARN_ON(1);
 119                 return;
 120         }
 121         send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
 122 }
 123
 124 void native_send_call_func_single_ipi(int cpu)
 125 {
 126         send_IPI_mask(cpumask_of_cpu(cpu), CALL_FUNCTION_SINGLE_VECTOR);
 127 }
 128
 129 void native_send_call_func_ipi(cpumask_t mask)
 130 {
 131         cpumask_t allbutself;
 132
 133         allbutself = cpu_online_map;
 134         cpu_clear(smp_processor_id(), allbutself);
 135
 136         if (cpus_equal(mask, allbutself) &&
 137             cpus_equal(cpu_online_map, cpu_callout_map))
 138                 send_IPI_allbutself(CALL_FUNCTION_VECTOR);
 139         else
 140                 send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
 141 }
 142
 143 static void stop_this_cpu(void *dummy)
 144 {
 145         local_irq_disable();
 146         /*
 147          * Remove this CPU:
 148          */
 149         cpu_clear(smp_processor_id(), cpu_online_map);
 150         disable_local_APIC();
 151         if (hlt_works(smp_processor_id()))
 152                 for (;;) halt();
 153         for (;;);
 154 }
 155
 156 /*
 157  * this function calls the 'stop' function on all other CPUs in the system.
 158  */
 159
 160 static void native_smp_send_stop(void)
 161 {
 162         unsigned long flags;
 163
 164         if (reboot_force)
 165                 return;
 166
 167         smp_call_function(stop_this_cpu, NULL, 0);
 168         local_irq_save(flags);
 169         disable_local_APIC();
 170         local_irq_restore(flags);
 171 }
 172
 173 /*
 174  * Reschedule call back. Nothing to do,
 175  * all the work is done automatically when
 176  * we return from the interrupt.
 177  */
 178 void smp_reschedule_interrupt(struct pt_regs *regs)
 179 {
 180         ack_APIC_irq();
 181 #ifdef CONFIG_X86_32
 182         __get_cpu_var(irq_stat).irq_resched_count++;
 183 #else
 184         add_pda(irq_resched_count, 1);
 185 #endif
 186 }
 187
 188 void smp_call_function_interrupt(struct pt_regs *regs)
 189 {
 190         ack_APIC_irq();
 191         irq_enter();
 192         generic_smp_call_function_interrupt();
 193 #ifdef CONFIG_X86_32
 194         __get_cpu_var(irq_stat).irq_call_count++;
 195 #else
 196         add_pda(irq_call_count, 1);
 197 #endif
 198         irq_exit();
 199 }
 200
 201 void smp_call_function_single_interrupt(struct pt_regs *regs)
 202 {
 203         ack_APIC_irq();
 204         irq_enter();
 205         generic_smp_call_function_single_interrupt();
 206 #ifdef CONFIG_X86_32
 207         __get_cpu_var(irq_stat).irq_call_count++;
 208 #else
 209         add_pda(irq_call_count, 1);
 210 #endif
 211         irq_exit();
 212 }
 213
 214 struct smp_ops smp_ops = {
 215         .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
 216         .smp_prepare_cpus = native_smp_prepare_cpus,
 217         .smp_cpus_done = native_smp_cpus_done,
 218
 219         .smp_send_stop = native_smp_send_stop,
 220         .smp_send_reschedule = native_smp_send_reschedule,
 221
 222         .cpu_up = native_cpu_up,
 223         .cpu_die = native_cpu_die,
 224         .cpu_disable = native_cpu_disable,
 225         .play_dead = native_play_dead,
 226
 227         .send_call_func_ipi = native_send_call_func_ipi,
 228         .send_call_func_single_ipi = native_send_call_func_single_ipi,
 229 };
 230 EXPORT_SYMBOL_GPL(smp_ops);