arch/x86/pci/amd_bus.c

   1 #include <linux/init.h>
   2 #include <linux/pci.h>
   3 #include <linux/topology.h>
   4 #include <linux/cpu.h>
   5 #include "pci.h"
   6
   7 #ifdef CONFIG_X86_64
   8 #include <asm/pci-direct.h>
   9 #include <asm/mpspec.h>
  10 #include <linux/cpumask.h>
  11 #endif
  12
  13 /*
  14  * This discovers the pcibus <-> node mapping on AMD K8.
  15  * also get peer root bus resource for io,mmio
  16  */
  17
  18 #ifdef CONFIG_NUMA
  19
  20 #define BUS_NR 256
  21
  22 #ifdef CONFIG_X86_64
  23
  24 static int mp_bus_to_node[BUS_NR];
  25
  26 void set_mp_bus_to_node(int busnum, int node)
  27 {
  28         if (busnum >= 0 &&  busnum < BUS_NR)
  29                 mp_bus_to_node[busnum] = node;
  30 }
  31
  32 int get_mp_bus_to_node(int busnum)
  33 {
  34         int node = -1;
  35
  36         if (busnum < 0 || busnum > (BUS_NR - 1))
  37                 return node;
  38
  39         node = mp_bus_to_node[busnum];
  40
  41         /*
  42          * let numa_node_id to decide it later in dma_alloc_pages
  43          * if there is no ram on that node
  44          */
  45         if (node != -1 && !node_online(node))
  46                 node = -1;
  47
  48         return node;
  49 }
  50
  51 #else /* CONFIG_X86_32 */
  52
  53 static unsigned char mp_bus_to_node[BUS_NR];
  54
  55 void set_mp_bus_to_node(int busnum, int node)
  56 {
  57         if (busnum >= 0 &&  busnum < BUS_NR)
  58         mp_bus_to_node[busnum] = (unsigned char) node;
  59 }
  60
  61 int get_mp_bus_to_node(int busnum)
  62 {
  63         int node;
  64
  65         if (busnum < 0 || busnum > (BUS_NR - 1))
  66                 return 0;
  67         node = mp_bus_to_node[busnum];
  68         return node;
  69 }
  70
  71 #endif /* CONFIG_X86_32 */
  72
  73 #endif /* CONFIG_NUMA */
  74
  75 #ifdef CONFIG_X86_64
  76
  77 /*
  78  * sub bus (transparent) will use entres from 3 to store extra from root,
  79  * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
  80  */
  81 #define RES_NUM 16
  82 struct pci_root_info {
  83         char name[12];
  84         unsigned int res_num;
  85         struct resource res[RES_NUM];
  86         int bus_min;
  87         int bus_max;
  88         int node;
  89         int link;
  90 };
  91
  92 /* 4 at this time, it may become to 32 */
  93 #define PCI_ROOT_NR 4
  94 static int pci_root_num;
  95 static struct pci_root_info pci_root_info[PCI_ROOT_NR];
  96
  97 void set_pci_bus_resources_arch_default(struct pci_bus *b)
  98 {
  99         int i;
 100         int j;
 101         struct pci_root_info *info;
 102
 103         /* if only one root bus, don't need to anything */
 104         if (pci_root_num < 2)
 105                 return;
 106
 107         for (i = 0; i < pci_root_num; i++) {
 108                 if (pci_root_info[i].bus_min == b->number)
 109                         break;
 110         }
 111
 112         if (i == pci_root_num)
 113                 return;
 114
 115         info = &pci_root_info[i];
 116         for (j = 0; j < info->res_num; j++) {
 117                 struct resource *res;
 118                 struct resource *root;
 119
 120                 res = &info->res[j];
 121                 b->resource[j] = res;
 122                 if (res->flags & IORESOURCE_IO)
 123                         root = &ioport_resource;
 124                 else
 125                         root = &iomem_resource;
 126                 insert_resource(root, res);
 127         }
 128 }
 129
 130 #define RANGE_NUM 16
 131
 132 struct res_range {
 133         size_t start;
 134         size_t end;
 135 };
 136
 137 static void __init update_range(struct res_range *range, size_t start,
 138                                 size_t end)
 139 {
 140         int i;
 141         int j;
 142
 143         for (j = 0; j < RANGE_NUM; j++) {
 144                 if (!range[j].end)
 145                         continue;
 146
 147                 if (start <= range[j].start && end >= range[j].end) {
 148                         range[j].start = 0;
 149                         range[j].end = 0;
 150                         continue;
 151                 }
 152
 153                 if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) {
 154                         range[j].start = end + 1;
 155                         continue;
 156                 }
 157
 158
 159                 if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) {
 160                         range[j].end = start - 1;
 161                         continue;
 162                 }
 163
 164                 if (start > range[j].start && end < range[j].end) {
 165                         /* find the new spare */
 166                         for (i = 0; i < RANGE_NUM; i++) {
 167                                 if (range[i].end == 0)
 168                                         break;
 169                         }
 170                         if (i < RANGE_NUM) {
 171                                 range[i].end = range[j].end;
 172                                 range[i].start = end + 1;
 173                         } else {
 174                                 printk(KERN_ERR "run of slot in ranges\n");
 175                         }
 176                         range[j].end = start - 1;
 177                         continue;
 178                 }
 179         }
 180 }
 181
 182 static void __init update_res(struct pci_root_info *info, size_t start,
 183                               size_t end, unsigned long flags, int merge)
 184 {
 185         int i;
 186         struct resource *res;
 187
 188         if (!merge)
 189                 goto addit;
 190
 191         /* try to merge it with old one */
 192         for (i = 0; i < info->res_num; i++) {
 193                 size_t final_start, final_end;
 194                 size_t common_start, common_end;
 195
 196                 res = &info->res[i];
 197                 if (res->flags != flags)
 198                         continue;
 199
 200                 common_start = max((size_t)res->start, start);
 201                 common_end = min((size_t)res->end, end);
 202                 if (common_start > common_end + 1)
 203                         continue;
 204
 205                 final_start = min((size_t)res->start, start);
 206                 final_end = max((size_t)res->end, end);
 207
 208                 res->start = final_start;
 209                 res->end = final_end;
 210                 return;
 211         }
 212
 213 addit:
 214
 215         /* need to add that */
 216         if (info->res_num >= RES_NUM)
 217                 return;
 218
 219         res = &info->res[info->res_num];
 220         res->name = info->name;
 221         res->flags = flags;
 222         res->start = start;
 223         res->end = end;
 224         res->child = NULL;
 225         info->res_num++;
 226 }
 227
 228 struct pci_hostbridge_probe {
 229         u32 bus;
 230         u32 slot;
 231         u32 vendor;
 232         u32 device;
 233 };
 234
 235 static struct pci_hostbridge_probe pci_probes[] __initdata = {
 236         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
 237         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
 238         { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
 239         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
 240 };
 241
 242 static u64 __initdata fam10h_mmconf_start;
 243 static u64 __initdata fam10h_mmconf_end;
 244 static void __init get_pci_mmcfg_amd_fam10h_range(void)
 245 {
 246         u32 address;
 247         u64 base, msr;
 248         unsigned segn_busn_bits;
 249
 250         /* assume all cpus from fam10h have mmconf */
 251         if (boot_cpu_data.x86 < 0x10)
 252                 return;
 253
 254         address = MSR_FAM10H_MMIO_CONF_BASE;
 255         rdmsrl(address, msr);
 256
 257         /* mmconfig is not enable */
 258         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 259                 return;
 260
 261         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 262
 263         segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 264                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 265
 266         fam10h_mmconf_start = base;
 267         fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
 268 }
 269
 270 /**
 271  * early_fill_mp_bus_to_node()
 272  * called before pcibios_scan_root and pci_scan_bus
 273  * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 274  * Registers found in the K8 northbridge
 275  */
 276 static int __init early_fill_mp_bus_info(void)
 277 {
 278         int i;
 279         int j;
 280         unsigned bus;
 281         unsigned slot;
 282         int found;
 283         int node;
 284         int link;
 285         int def_node;
 286         int def_link;
 287         struct pci_root_info *info;
 288         u32 reg;
 289         struct resource *res;
 290         size_t start;
 291         size_t end;
 292         struct res_range range[RANGE_NUM];
 293         u64 val;
 294         u32 address;
 295
 296 #ifdef CONFIG_NUMA
 297         for (i = 0; i < BUS_NR; i++)
 298                 mp_bus_to_node[i] = -1;
 299 #endif
 300
 301         if (!early_pci_allowed())
 302                 return -1;
 303
 304         found = 0;
 305         for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
 306                 u32 id;
 307                 u16 device;
 308                 u16 vendor;
 309
 310                 bus = pci_probes[i].bus;
 311                 slot = pci_probes[i].slot;
 312                 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
 313
 314                 vendor = id & 0xffff;
 315                 device = (id>>16) & 0xffff;
 316                 if (pci_probes[i].vendor == vendor &&
 317                     pci_probes[i].device == device) {
 318                         found = 1;
 319                         break;
 320                 }
 321         }
 322
 323         if (!found)
 324                 return 0;
 325
 326         pci_root_num = 0;
 327         for (i = 0; i < 4; i++) {
 328                 int min_bus;
 329                 int max_bus;
 330                 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
 331
 332                 /* Check if that register is enabled for bus range */
 333                 if ((reg & 7) != 3)
 334                         continue;
 335
 336                 min_bus = (reg >> 16) & 0xff;
 337                 max_bus = (reg >> 24) & 0xff;
 338                 node = (reg >> 4) & 0x07;
 339 #ifdef CONFIG_NUMA
 340                 for (j = min_bus; j <= max_bus; j++)
 341                         mp_bus_to_node[j] = (unsigned char) node;
 342 #endif
 343                 link = (reg >> 8) & 0x03;
 344
 345                 info = &pci_root_info[pci_root_num];
 346                 info->bus_min = min_bus;
 347                 info->bus_max = max_bus;
 348                 info->node = node;
 349                 info->link = link;
 350                 sprintf(info->name, "PCI Bus #%02x", min_bus);
 351                 pci_root_num++;
 352         }
 353
 354         /* get the default node and link for left over res */
 355         reg = read_pci_config(bus, slot, 0, 0x60);
 356         def_node = (reg >> 8) & 0x07;
 357         reg = read_pci_config(bus, slot, 0, 0x64);
 358         def_link = (reg >> 8) & 0x03;
 359
 360         memset(range, 0, sizeof(range));
 361         range[0].end = 0xffff;
 362         /* io port resource */
 363         for (i = 0; i < 4; i++) {
 364                 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
 365                 if (!(reg & 3))
 366                         continue;
 367
 368                 start = reg & 0xfff000;
 369                 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
 370                 node = reg & 0x07;
 371                 link = (reg >> 4) & 0x03;
 372                 end = (reg & 0xfff000) | 0xfff;
 373
 374                 /* find the position */
 375                 for (j = 0; j < pci_root_num; j++) {
 376                         info = &pci_root_info[j];
 377                         if (info->node == node && info->link == link)
 378                                 break;
 379                 }
 380                 if (j == pci_root_num)
 381                         continue; /* not found */
 382
 383                 info = &pci_root_info[j];
 384                 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
 385                        node, link, (u64)start, (u64)end);
 386
 387                 /* kernel only handle 16 bit only */
 388                 if (end > 0xffff)
 389                         end = 0xffff;
 390                 update_res(info, start, end, IORESOURCE_IO, 1);
 391                 update_range(range, start, end);
 392         }
 393         /* add left over io port range to def node/link, [0, 0xffff] */
 394         /* find the position */
 395         for (j = 0; j < pci_root_num; j++) {
 396                 info = &pci_root_info[j];
 397                 if (info->node == def_node && info->link == def_link)
 398                         break;
 399         }
 400         if (j < pci_root_num) {
 401                 info = &pci_root_info[j];
 402                 for (i = 0; i < RANGE_NUM; i++) {
 403                         if (!range[i].end)
 404                                 continue;
 405
 406                         update_res(info, range[i].start, range[i].end,
 407                                    IORESOURCE_IO, 1);
 408                 }
 409         }
 410
 411         memset(range, 0, sizeof(range));
 412         /* 0xfd00000000-0xffffffffff for HT */
 413         range[0].end = (0xfdULL<<32) - 1;
 414
 415         /* need to take out [0, TOM) for RAM*/
 416         address = MSR_K8_TOP_MEM1;
 417         rdmsrl(address, val);
 418         end = (val & 0xffffff800000ULL);
 419         printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
 420         if (end < (1ULL<<32))
 421                 update_range(range, 0, end - 1);
 422
 423         /* get mmconfig */
 424         get_pci_mmcfg_amd_fam10h_range();
 425         /* need to take out mmconf range */
 426         if (fam10h_mmconf_end) {
 427                 printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
 428                 update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
 429         }
 430
 431         /* mmio resource */
 432         for (i = 0; i < 8; i++) {
 433                 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
 434                 if (!(reg & 3))
 435                         continue;
 436
 437                 start = reg & 0xffffff00; /* 39:16 on 31:8*/
 438                 start <<= 8;
 439                 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
 440                 node = reg & 0x07;
 441                 link = (reg >> 4) & 0x03;
 442                 end = (reg & 0xffffff00);
 443                 end <<= 8;
 444                 end |= 0xffff;
 445
 446                 /* find the position */
 447                 for (j = 0; j < pci_root_num; j++) {
 448                         info = &pci_root_info[j];
 449                         if (info->node == node && info->link == link)
 450                                 break;
 451                 }
 452                 if (j == pci_root_num)
 453                         continue; /* not found */
 454
 455                 info = &pci_root_info[j];
 456
 457                 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
 458                        node, link, (u64)start, (u64)end);
 459                 /*
 460                  * some sick allocation would have range overlap with fam10h
 461                  * mmconf range, so need to update start and end.
 462                  */
 463                 if (fam10h_mmconf_end) {
 464                         int changed = 0;
 465                         u64 endx = 0;
 466                         if (start >= fam10h_mmconf_start &&
 467                             start <= fam10h_mmconf_end) {
 468                                 start = fam10h_mmconf_end + 1;
 469                                 changed = 1;
 470                         }
 471
 472                         if (end >= fam10h_mmconf_start &&
 473                             end <= fam10h_mmconf_end) {
 474                                 end = fam10h_mmconf_start - 1;
 475                                 changed = 1;
 476                         }
 477
 478                         if (start < fam10h_mmconf_start &&
 479                             end > fam10h_mmconf_end) {
 480                                 /* we got a hole */
 481                                 endx = fam10h_mmconf_start - 1;
 482                                 update_res(info, start, endx, IORESOURCE_MEM, 0);
 483                                 update_range(range, start, endx);
 484                                 printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
 485                                 start = fam10h_mmconf_end + 1;
 486                                 changed = 1;
 487                         }
 488                         if (changed) {
 489                                 if (start <= end) {
 490                                         printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
 491                                 } else {
 492                                         printk(KERN_CONT "%s\n", endx?"":" ==> none");
 493                                         continue;
 494                                 }
 495                         }
 496                 }
 497
 498                 update_res(info, start, end, IORESOURCE_MEM, 1);
 499                 update_range(range, start, end);
 500                 printk(KERN_CONT "\n");
 501         }
 502
 503         /* need to take out [4G, TOM2) for RAM*/
 504         /* SYS_CFG */
 505         address = MSR_K8_SYSCFG;
 506         rdmsrl(address, val);
 507         /* TOP_MEM2 is enabled? */
 508         if (val & (1<<21)) {
 509                 /* TOP_MEM2 */
 510                 address = MSR_K8_TOP_MEM2;
 511                 rdmsrl(address, val);
 512                 end = (val & 0xffffff800000ULL);
 513                 printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
 514                 update_range(range, 1ULL<<32, end - 1);
 515         }
 516
 517         /*
 518          * add left over mmio range to def node/link ?
 519          * that is tricky, just record range in from start_min to 4G
 520          */
 521         for (j = 0; j < pci_root_num; j++) {
 522                 info = &pci_root_info[j];
 523                 if (info->node == def_node && info->link == def_link)
 524                         break;
 525         }
 526         if (j < pci_root_num) {
 527                 info = &pci_root_info[j];
 528
 529                 for (i = 0; i < RANGE_NUM; i++) {
 530                         if (!range[i].end)
 531                                 continue;
 532
 533                         update_res(info, range[i].start, range[i].end,
 534                                    IORESOURCE_MEM, 1);
 535                 }
 536         }
 537
 538         for (i = 0; i < pci_root_num; i++) {
 539                 int res_num;
 540                 int busnum;
 541
 542                 info = &pci_root_info[i];
 543                 res_num = info->res_num;
 544                 busnum = info->bus_min;
 545                 printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
 546                        info->bus_min, info->bus_max, info->node, info->link);
 547                 for (j = 0; j < res_num; j++) {
 548                         res = &info->res[j];
 549                         printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
 550                                busnum, j,
 551                                (res->flags & IORESOURCE_IO)?"io port":"mmio",
 552                                res->start, res->end);
 553                 }
 554         }
 555
 556         return 0;
 557 }
 558
 559 #else  /* !CONFIG_X86_64 */
 560
 561 static int __init early_fill_mp_bus_info(void) { return 0; }
 562
 563 #endif /* !CONFIG_X86_64 */
 564
 565 /* common 32/64 bit code */
 566
 567 #define ENABLE_CF8_EXT_CFG      (1ULL << 46)
 568
 569 static void enable_pci_io_ecs(void *unused)
 570 {
 571         u64 reg;
 572         rdmsrl(MSR_AMD64_NB_CFG, reg);
 573         if (!(reg & ENABLE_CF8_EXT_CFG)) {
 574                 reg |= ENABLE_CF8_EXT_CFG;
 575                 wrmsrl(MSR_AMD64_NB_CFG, reg);
 576         }
 577 }
 578
 579 static int __cpuinit amd_cpu_notify(struct notifier_block *self,
 580                                     unsigned long action, void *hcpu)
 581 {
 582         int cpu = (long)hcpu;
 583         switch (action) {
 584         case CPU_ONLINE:
 585         case CPU_ONLINE_FROZEN:
 586                 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
 587                 break;
 588         default:
 589                 break;
 590         }
 591         return NOTIFY_OK;
 592 }
 593
 594 static struct notifier_block __cpuinitdata amd_cpu_notifier = {
 595         .notifier_call  = amd_cpu_notify,
 596 };
 597
 598 static int __init pci_io_ecs_init(void)
 599 {
 600         int cpu;
 601
 602         /* assume all cpus from fam10h have IO ECS */
 603         if (boot_cpu_data.x86 < 0x10)
 604                 return 0;
 605
 606         register_cpu_notifier(&amd_cpu_notifier);
 607         for_each_online_cpu(cpu)
 608                 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
 609                                (void *)(long)cpu);
 610         pci_probe |= PCI_HAS_IO_ECS;
 611
 612         return 0;
 613 }
 614
 615 static int __init amd_postcore_init(void)
 616 {
 617         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
 618                 return 0;
 619
 620         early_fill_mp_bus_info();
 621         pci_io_ecs_init();
 622
 623         return 0;
 624 }
 625
 626 postcore_initcall(amd_postcore_init);