2 * Apple Peripheral System Controller (PSC)
4 * The PSC is used on the AV Macs to control IO functions not handled
5 * by the VIAs (Ethernet, DSP, SCC).
9 * Try to figure out what's going on in pIFR5 and pIFR6. There seem to be
10 * persisant interrupt conditions in those registers and I have no idea what
11 * they are. Granted it doesn't affect since we're not enabling any interrupts
12 * on those levels at the moment, but it would be nice to know. I have a feeling
13 * they aren't actually interrupt lines but data lines (to the DSP?)
16 #include <linux/types.h>
17 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/irq.h>
23 #include <asm/traps.h>
24 #include <asm/macintosh.h>
25 #include <asm/macints.h>
26 #include <asm/mac_psc.h>
34 * Debugging dump, used in various places to see what's going on.
37 static void psc_debug_dump(void)
41 if (!psc_present
) return;
42 for (i
= 0x30 ; i
< 0x70 ; i
+= 0x10) {
43 printk("PSC #%d: IFR = 0x%02X IER = 0x%02X\n",
45 (int) psc_read_byte(pIFRbase
+ i
),
46 (int) psc_read_byte(pIERbase
+ i
));
51 * Try to kill all DMA channels on the PSC. Not sure how this his
52 * supposed to work; this is code lifted from macmace.c and then
53 * expanded to cover what I think are the other 7 channels.
56 static __init
void psc_dma_die_die_die(void)
60 printk("Killing all PSC DMA channels...");
61 for (i
= 0 ; i
< 9 ; i
++) {
62 psc_write_word(PSC_CTL_BASE
+ (i
<< 4), 0x8800);
63 psc_write_word(PSC_CTL_BASE
+ (i
<< 4), 0x1000);
64 psc_write_word(PSC_CMD_BASE
+ (i
<< 5), 0x1100);
65 psc_write_word(PSC_CMD_BASE
+ (i
<< 5) + 0x10, 0x1100);
71 * Initialize the PSC. For now this just involves shutting down all
72 * interrupt sources using the IERs.
75 void __init
psc_init(void)
79 if (macintosh_config
->ident
!= MAC_MODEL_C660
80 && macintosh_config
->ident
!= MAC_MODEL_Q840
)
88 * The PSC is always at the same spot, but using psc
89 * keeps things consistent with the psc_xxxx functions.
92 psc
= (void *) PSC_BASE
;
95 printk("PSC detected at %p\n", psc
);
97 psc_dma_die_die_die();
103 * Mask and clear all possible interrupts
106 for (i
= 0x30 ; i
< 0x70 ; i
+= 0x10) {
107 psc_write_byte(pIERbase
+ i
, 0x0F);
108 psc_write_byte(pIFRbase
+ i
, 0x0F);
113 * PSC interrupt handler. It's a lot like the VIA interrupt handler.
116 static void psc_irq(unsigned int irq
, struct irq_desc
*desc
)
118 unsigned int offset
= (unsigned int)irq_desc_get_handler_data(desc
);
119 int pIFR
= pIFRbase
+ offset
;
120 int pIER
= pIERbase
+ offset
;
122 unsigned char irq_bit
, events
;
125 printk("psc_irq: irq %u pIFR = 0x%02X pIER = 0x%02X\n",
126 irq
, (int) psc_read_byte(pIFR
), (int) psc_read_byte(pIER
));
129 events
= psc_read_byte(pIFR
) & psc_read_byte(pIER
) & 0xF;
136 if (events
& irq_bit
) {
137 psc_write_byte(pIFR
, irq_bit
);
138 generic_handle_irq(irq_num
);
142 } while (events
>= irq_bit
);
146 * Register the PSC interrupt dispatchers for autovector interrupts 3-6.
149 void __init
psc_register_interrupts(void)
151 irq_set_chained_handler_and_data(IRQ_AUTO_3
, psc_irq
, (void *)0x30);
152 irq_set_chained_handler_and_data(IRQ_AUTO_4
, psc_irq
, (void *)0x40);
153 irq_set_chained_handler_and_data(IRQ_AUTO_5
, psc_irq
, (void *)0x50);
154 irq_set_chained_handler_and_data(IRQ_AUTO_6
, psc_irq
, (void *)0x60);
157 void psc_irq_enable(int irq
) {
158 int irq_src
= IRQ_SRC(irq
);
159 int irq_idx
= IRQ_IDX(irq
);
160 int pIER
= pIERbase
+ (irq_src
<< 4);
163 printk("psc_irq_enable(%d)\n", irq
);
165 psc_write_byte(pIER
, (1 << irq_idx
) | 0x80);
168 void psc_irq_disable(int irq
) {
169 int irq_src
= IRQ_SRC(irq
);
170 int irq_idx
= IRQ_IDX(irq
);
171 int pIER
= pIERbase
+ (irq_src
<< 4);
174 printk("psc_irq_disable(%d)\n", irq
);
176 psc_write_byte(pIER
, 1 << irq_idx
);